GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <string.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/console.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <plat_private.h>
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#include <soc.h>
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#include "ddr_parameter.h"
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/*
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* The miniloader delivers the parameters about ddr usage info from address
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* 0x02000000 and the data format is defined as below figure. It tells ATF the
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* areas of ddr that are used by platform, we treat them as non-secure regions
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* by default. Then we should parse the other part regions and configurate them
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* as secure regions to avoid illegal access.
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*
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* [ddr usage info data format]
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* 0x02000000
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* -----------------------------------------------------------------------------
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* | <name> | <size> | <description> |
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* -----------------------------------------------------------------------------
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* | count | 4byte | the array numbers of the |
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* | | | 'addr_array' and 'size_array' |
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* -----------------------------------------------------------------------------
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* | reserved | 4byte | just for 'addr_array' 8byte aligned |
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* -----------------------------------------------------------------------------
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* | addr_array[count] | per 8byte | memory region base address |
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* -----------------------------------------------------------------------------
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* | size_array[count] | per 8byte | memory region size (byte) |
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* -----------------------------------------------------------------------------
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*/
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/*
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* function: read parameters info(ns-regions) and try to parse s-regions info
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*
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* @addr: head address to the ddr usage struct from miniloader
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* @max_mb: the max ddr capacity(MB) that the platform support
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*/
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struct param_ddr_usage ddr_region_usage_parse(uint64_t addr, uint64_t max_mb)
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{
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uint64_t base, top;
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uint32_t i, addr_offset, size_offset;
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struct param_ddr_usage p;
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memset(&p, 0, sizeof(p));
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/* read how many blocks of ns-regions, read from offset: 0x0 */
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p.ns_nr = mmio_read_32(addr + REGION_NR_OFFSET);
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if ((p.ns_nr > DDR_REGION_NR_MAX) || (p.ns_nr == 0)) {
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ERROR("over or zero region, nr=%d, max=%d\n",
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p.ns_nr, DDR_REGION_NR_MAX);
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return p;
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}
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/* whole ddr regions boundary, it will be used when parse s-regions */
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p.boundary = max_mb;
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/* calculate ns-region base addr and size offset */
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addr_offset = REGION_ADDR_OFFSET;
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size_offset = REGION_ADDR_OFFSET + p.ns_nr * REGION_DATA_PER_BYTES;
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/* read all ns-regions base and top address */
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for (i = 0; i < p.ns_nr; i++) {
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base = mmio_read_64(addr + addr_offset);
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top = base + mmio_read_64(addr + size_offset);
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/*
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* translate byte to MB and store info,
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* Miniloader will promise every ns-region is MB aligned.
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*/
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p.ns_base[i] = RG_SIZE_MB(base);
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p.ns_top[i] = RG_SIZE_MB(top);
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addr_offset += REGION_DATA_PER_BYTES;
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size_offset += REGION_DATA_PER_BYTES;
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}
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/*
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* a s-region's base starts from previous ns-region's top, and a
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* s-region's top ends with next ns-region's base. maybe like this:
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*
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* case1: ns-regison start from 0MB
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* -----------------------------------------------
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* | ns0 | S0 | ns1 | S1 | ns2 |
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* 0----------------------------------------------- max_mb
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*
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*
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* case2: ns-regison not start from 0MB
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* -----------------------------------------------
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* | S0 | ns0 | ns1 | ns2 | S1 |
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* 0----------------------------------------------- max_mb
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*/
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/* like above case2 figure, ns-region is not start from 0MB */
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if (p.ns_base[0] != 0) {
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p.s_base[p.s_nr] = 0;
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p.s_top[p.s_nr] = p.ns_base[0];
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p.s_nr++;
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}
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/*
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* notice: if ns-regions not start from 0MB, p.s_nr = 1 now, otherwise 0
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*/
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for (i = 0; i < p.ns_nr; i++) {
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/*
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* if current ns-regions top covers boundary,
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* that means s-regions are all parsed yet, so finsh.
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*/
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if (p.ns_top[i] == p.boundary)
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goto out;
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/* s-region's base starts from previous ns-region's top */
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p.s_base[p.s_nr] = p.ns_top[i];
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/* s-region's top ends with next ns-region's base */
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if (i + 1 < p.ns_nr)
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p.s_top[p.s_nr] = p.ns_base[i + 1];
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else
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p.s_top[p.s_nr] = p.boundary;
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p.s_nr++;
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}
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out:
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return p;
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}
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+44
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DDR_PARAMETER_H
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#define DDR_PARAMETER_H
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#include <string.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/console.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <plat_private.h>
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#include <soc.h>
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#define DDR_REGION_NR_MAX 10
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#define REGION_NR_OFFSET 0
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#define REGION_ADDR_OFFSET 8
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#define REGION_DATA_PER_BYTES 8
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#define RG_SIZE_MB(byte) ((byte) >> 20)
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/* unit: MB */
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struct param_ddr_usage {
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uint64_t boundary;
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uint32_t ns_nr;
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uint64_t ns_base[DDR_REGION_NR_MAX];
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uint64_t ns_top[DDR_REGION_NR_MAX];
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uint32_t s_nr;
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uint64_t s_base[DDR_REGION_NR_MAX + 1];
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uint64_t s_top[DDR_REGION_NR_MAX + 1];
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};
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struct param_ddr_usage ddr_region_usage_parse(uint64_t addr, uint64_t max_mb);
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#endif /* DDR_PARAMETER_H */
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+122
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PMU_COM_H
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#define PMU_COM_H
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#ifndef CHECK_CPU_WFIE_BASE
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#define CHECK_CPU_WFIE_BASE (PMU_BASE + PMU_CORE_PWR_ST)
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#endif
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/*
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* Use this macro to instantiate lock before it is used in below
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* rockchip_pd_lock_xxx() macros
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*/
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DECLARE_BAKERY_LOCK(rockchip_pd_lock);
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/*
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* These are wrapper macros to the powe domain Bakery Lock API.
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*/
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#define rockchip_pd_lock_init() bakery_lock_init(&rockchip_pd_lock)
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#define rockchip_pd_lock_get() bakery_lock_get(&rockchip_pd_lock)
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#define rockchip_pd_lock_rls() bakery_lock_release(&rockchip_pd_lock)
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/*****************************************************************************
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* power domain on or off
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*****************************************************************************/
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enum pmu_pd_state {
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pmu_pd_on = 0,
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pmu_pd_off = 1
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};
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#pragma weak plat_ic_get_pending_interrupt_id
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#pragma weak pmu_power_domain_ctr
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#pragma weak check_cpu_wfie
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static inline uint32_t pmu_power_domain_st(uint32_t pd)
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{
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uint32_t pwrdn_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & BIT(pd);
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if (pwrdn_st)
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return pmu_pd_off;
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else
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return pmu_pd_on;
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}
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static int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state)
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{
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uint32_t val;
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uint32_t loop = 0;
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int ret = 0;
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rockchip_pd_lock_get();
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val = mmio_read_32(PMU_BASE + PMU_PWRDN_CON);
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if (pd_state == pmu_pd_off)
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val |= BIT(pd);
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else
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val &= ~BIT(pd);
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mmio_write_32(PMU_BASE + PMU_PWRDN_CON, val);
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dsb();
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while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) {
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udelay(1);
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loop++;
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}
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if (pmu_power_domain_st(pd) != pd_state) {
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WARN("%s: %d, %d, error!\n", __func__, pd, pd_state);
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ret = -EINVAL;
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}
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rockchip_pd_lock_rls();
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return ret;
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}
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static int check_cpu_wfie(uint32_t cpu_id, uint32_t wfie_msk)
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{
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uint32_t cluster_id, loop = 0;
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if (cpu_id >= PLATFORM_CLUSTER0_CORE_COUNT) {
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cluster_id = 1;
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cpu_id -= PLATFORM_CLUSTER0_CORE_COUNT;
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} else {
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cluster_id = 0;
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}
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/*
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* wfe/wfi tracking not possible, hopefully the host
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* was sucessful in enabling wfe/wfi.
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* We'll give a bit of additional time, like the kernel does.
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*/
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if ((cluster_id && clstb_cpu_wfe < 0) ||
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(!cluster_id && clstl_cpu_wfe < 0)) {
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mdelay(1);
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return 0;
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}
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if (cluster_id)
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wfie_msk <<= (clstb_cpu_wfe + cpu_id);
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else
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wfie_msk <<= (clstl_cpu_wfe + cpu_id);
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while (!(mmio_read_32(CHECK_CPU_WFIE_BASE) & wfie_msk) &&
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(loop < CHK_CPU_LOOP)) {
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udelay(1);
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loop++;
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}
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if ((mmio_read_32(CHECK_CPU_WFIE_BASE) & wfie_msk) == 0) {
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WARN("%s: %d, %d, %d, error!\n", __func__,
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cluster_id, cpu_id, wfie_msk);
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return -EINVAL;
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}
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return 0;
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}
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#endif /* PMU_COM_H */
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