GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ROCKCHIP_PLAT_MACROS_S
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#define ROCKCHIP_PLAT_MACROS_S
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#include <drivers/arm/cci.h>
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#include <drivers/arm/gic_common.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/arm/gicv3.h>
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#include <platform_def.h>
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.section .rodata.gic_reg_name, "aS"
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/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */
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gicc_regs:
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.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
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/* Applicable only to GICv3 with SRE enabled */
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icc_regs:
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.asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", ""
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/* Registers common to both GICv2 and GICv3 */
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gicd_pend_reg:
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.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
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" Offset:\t\t\tvalue\n"
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newline:
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.asciz "\n"
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spacer:
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.asciz ":\t\t0x"
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.section .rodata.cci_reg_name, "aS"
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cci_iface_regs:
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.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
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/* ---------------------------------------------
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* The below utility macro prints out relevant GIC
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* and CCI registers whenever an unhandled
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* exception is taken in BL31.
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* Expects: GICD base in x26, GICC base in x27
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* Clobbers: x0 - x10, sp
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* ---------------------------------------------
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*/
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.macro plat_crash_print_regs
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mov_imm x26, PLAT_RK_GICD_BASE
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mov_imm x27, PLAT_RK_GICC_BASE
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/* Check for GICv3 system register access */
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mrs x7, id_aa64pfr0_el1
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ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
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cmp x7, #1
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b.ne print_gicv2
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/* Check for SRE enable */
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mrs x8, ICC_SRE_EL3
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tst x8, #ICC_SRE_SRE_BIT
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b.eq print_gicv2
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/* Load the icc reg list to x6 */
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adr x6, icc_regs
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/* Load the icc regs to gp regs used by str_in_crash_buf_print */
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mrs x8, ICC_HPPIR0_EL1
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mrs x9, ICC_HPPIR1_EL1
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mrs x10, ICC_CTLR_EL3
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/* Store to the crash buf and print to console */
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bl str_in_crash_buf_print
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b print_gic_common
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print_gicv2:
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/* Load the gicc reg list to x6 */
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adr x6, gicc_regs
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/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
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ldr w8, [x27, #GICC_HPPIR]
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ldr w9, [x27, #GICC_AHPPIR]
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ldr w10, [x27, #GICC_CTLR]
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/* Store to the crash buf and print to console */
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bl str_in_crash_buf_print
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print_gic_common:
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/* Print the GICD_ISPENDR regs */
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add x7, x26, #GICD_ISPENDR
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adr x4, gicd_pend_reg
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bl asm_print_str
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gicd_ispendr_loop:
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sub x4, x7, x26
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cmp x4, #0x280
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b.eq exit_print_gic_regs
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bl asm_print_hex
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adr x4, spacer
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bl asm_print_str
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ldr x4, [x7], #8
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bl asm_print_hex
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adr x4, newline
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bl asm_print_str
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b gicd_ispendr_loop
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exit_print_gic_regs:
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#if PLATFORM_CLUSTER_COUNT > 1
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adr x6, cci_iface_regs
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/* Store in x7 the base address of the first interface */
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mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \
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PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX))
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ldr w8, [x7, #SNOOP_CTRL_REG]
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/* Store in x7 the base address of the second interface */
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mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \
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PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX))
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ldr w9, [x7, #SNOOP_CTRL_REG]
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/* Store to the crash buf and print to console */
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bl str_in_crash_buf_print
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#endif
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.endm
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#endif /* ROCKCHIP_PLAT_MACROS_S */
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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_PARAMS_H
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#define PLAT_PARAMS_H
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#include <stdint.h>
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#include <export/plat/rockchip/common/plat_params_exp.h>
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#endif /* PLAT_PARAMS_H */
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/*
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* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_PRIVATE_H
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#define PLAT_PRIVATE_H
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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#include <lib/psci/psci.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <lib/mmio.h>
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#include <plat_params.h>
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#define __sramdata __attribute__((section(".sram.data")))
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#define __sramconst __attribute__((section(".sram.rodata")))
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#define __sramfunc __attribute__((section(".sram.text")))
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#define __pmusramdata __attribute__((section(".pmusram.data")))
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#define __pmusramconst __attribute__((section(".pmusram.rodata")))
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#define __pmusramfunc __attribute__((section(".pmusram.text")))
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extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end;
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extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end;
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extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end;
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extern uint32_t __bl31_sram_text_real_end, __bl31_sram_data_real_end;
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extern uint32_t __sram_incbin_start, __sram_incbin_end;
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extern uint32_t __sram_incbin_real_end;
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/******************************************************************************
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* The register have write-mask bits, it is mean, if you want to set the bits,
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* you needs set the write-mask bits at the same time,
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* The write-mask bits is in high 16-bits.
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* The fllowing macro definition helps access write-mask bits reg efficient!
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******************************************************************************/
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#define REG_MSK_SHIFT 16
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#ifndef WMSK_BIT
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#define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT)
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#endif
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/* set one bit with write mask */
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#ifndef BIT_WITH_WMSK
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#define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr))
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#endif
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#ifndef BITS_SHIFT
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#define BITS_SHIFT(bits, shift) (bits << (shift))
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#endif
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#ifndef BITS_WITH_WMASK
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#define BITS_WITH_WMASK(bits, msk, shift)\
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(BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT)))
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#endif
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/******************************************************************************
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* Function and variable prototypes
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*****************************************************************************/
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#ifdef __aarch64__
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void plat_configure_mmu_el3(unsigned long total_base,
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unsigned long total_size,
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unsigned long,
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unsigned long,
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unsigned long,
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unsigned long);
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void rockchip_plat_mmu_el3(void);
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#else
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void plat_configure_mmu_svc_mon(unsigned long total_base,
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unsigned long total_size,
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unsigned long,
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unsigned long,
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unsigned long,
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unsigned long);
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void rockchip_plat_mmu_svc_mon(void);
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#endif
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void plat_cci_init(void);
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void plat_cci_enable(void);
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void plat_cci_disable(void);
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void plat_delay_timer_init(void);
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void params_early_setup(u_register_t plat_params_from_bl2);
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void plat_rockchip_gic_driver_init(void);
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void plat_rockchip_gic_init(void);
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void plat_rockchip_gic_cpuif_enable(void);
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void plat_rockchip_gic_cpuif_disable(void);
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void plat_rockchip_gic_pcpu_init(void);
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void plat_rockchip_pmu_init(void);
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void plat_rockchip_soc_init(void);
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uintptr_t plat_get_sec_entrypoint(void);
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void platform_cpu_warmboot(void);
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struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void);
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struct bl_aux_gpio_info *plat_get_rockchip_gpio_poweroff(void);
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struct bl_aux_gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count);
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struct bl_aux_rk_apio_info *plat_get_rockchip_suspend_apio(void);
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void plat_rockchip_gpio_init(void);
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void plat_rockchip_save_gpio(void);
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void plat_rockchip_restore_gpio(void);
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int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint);
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int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
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plat_local_state_t lvl_state);
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int rockchip_soc_cores_pwr_dm_off(void);
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int rockchip_soc_sys_pwr_dm_suspend(void);
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int rockchip_soc_cores_pwr_dm_suspend(void);
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int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl,
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plat_local_state_t lvl_state);
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int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
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plat_local_state_t lvl_state);
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int rockchip_soc_cores_pwr_dm_on_finish(void);
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int rockchip_soc_sys_pwr_dm_resume(void);
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int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl,
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plat_local_state_t lvl_state);
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int rockchip_soc_cores_pwr_dm_resume(void);
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void __dead2 rockchip_soc_soft_reset(void);
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void __dead2 rockchip_soc_system_off(void);
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void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(
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const psci_power_state_t *target_state);
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void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void);
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extern const unsigned char rockchip_power_domain_tree_desc[];
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extern void *pmu_cpuson_entrypoint;
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extern u_register_t cpuson_entry_point[PLATFORM_CORE_COUNT];
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extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT];
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extern const mmap_region_t plat_rk_mmap[];
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uint32_t rockchip_get_uart_base(void);
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uint32_t rockchip_get_uart_baudrate(void);
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uint32_t rockchip_get_uart_clock(void);
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#endif /* __ASSEMBLER__ */
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/******************************************************************************
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* cpu up status
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* The bits of macro value is not more than 12 bits for cmp instruction!
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******************************************************************************/
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#define PMU_CPU_HOTPLUG 0xf00
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#define PMU_CPU_AUTO_PWRDN 0xf0
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#define PMU_CLST_RET 0xa5
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#endif /* PLAT_PRIVATE_H */
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+27
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ROCKCHIP_SIP_SVC_H
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#define ROCKCHIP_SIP_SVC_H
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/* SMC function IDs for SiP Service queries */
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#define SIP_SVC_CALL_COUNT 0x8200ff00
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#define SIP_SVC_UID 0x8200ff01
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#define SIP_SVC_VERSION 0x8200ff03
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/* rockchip SiP Service Calls version numbers */
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#define RK_SIP_SVC_VERSION_MAJOR 0x0
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#define RK_SIP_SVC_VERSION_MINOR 0x1
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/* Number of ROCKCHIP SiP Calls implemented */
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#define RK_COMMON_SIP_NUM_CALLS 0x3
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enum {
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RK_SIP_E_SUCCESS = 0,
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RK_SIP_E_INVALID_PARAM = -1
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};
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#endif /* ROCKCHIP_SIP_SVC_H */
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