GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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.globl clst_warmboot_data
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.macro func_rockchip_clst_warmboot
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.endm
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.macro rockchip_clst_warmboot_data
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clst_warmboot_data:
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.rept PLATFORM_CLUSTER_COUNT
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.word 0
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.endr
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.endm
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File diff suppressed because it is too large
Load Diff
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PMU_H__
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#define __PMU_H__
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/* Needed aligned 16 bytes for sp stack top */
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#define PSRAM_SP_TOP ((PMUSRAM_BASE + PMUSRAM_RSIZE) & ~0xf)
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/*****************************************************************************
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* pmu con,reg
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*****************************************************************************/
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#define PMU_WKUP_CFG0_LO 0x00
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#define PMU_WKUP_CFG0_HI 0x04
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#define PMU_WKUP_CFG1_LO 0x08
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#define PMU_WKUP_CFG1_HI 0x0c
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#define PMU_WKUP_CFG2_LO 0x10
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#define PMU_PWRDN_CON 0x18
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#define PMU_PWRDN_ST 0x20
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#define PMU_PWRMODE_CORE_LO 0x24
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#define PMU_PWRMODE_CORE_HI 0x28
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#define PMU_PWRMODE_COMMON_CON_LO 0x2c
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#define PMU_PWRMODE_COMMON_CON_HI 0x30
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#define PMU_SFT_CON 0x34
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#define PMU_INT_ST 0x44
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#define PMU_BUS_IDLE_REQ 0x64
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#define PMU_BUS_IDLE_ST 0x6c
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#define PMU_OSC_CNT_LO 0x74
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#define PMU_OSC_CNT_HI 0x78
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#define PMU_PLLLOCK_CNT_LO 0x7c
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#define PMU_PLLLOCK_CNT_HI 0x80
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#define PMU_PLLRST_CNT_LO 0x84
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#define PMU_PLLRST_CNT_HI 0x88
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#define PMU_STABLE_CNT_LO 0x8c
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#define PMU_STABLE_CNT_HI 0x90
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#define PMU_WAKEUP_RST_CLR_LO 0x9c
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#define PMU_WAKEUP_RST_CLR_HI 0xa0
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#define PMU_DDR_SREF_ST 0xa4
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#define PMU_SYS_REG0_LO 0xa8
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#define PMU_SYS_REG0_HI 0xac
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#define PMU_SYS_REG1_LO 0xb0
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#define PMU_SYS_REG1_HI 0xb4
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#define PMU_SYS_REG2_LO 0xb8
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#define PMU_SYS_REG2_HI 0xbc
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#define PMU_SYS_REG3_LO 0xc0
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#define PMU_SYS_REG3_HI 0xc4
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#define PMU_SCU_PWRDN_CNT_LO 0xc8
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#define PMU_SCU_PWRDN_CNT_HI 0xcc
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#define PMU_SCU_PWRUP_CNT_LO 0xd0
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#define PMU_SCU_PWRUP_CNT_HI 0xd4
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#define PMU_TIMEOUT_CNT_LO 0xd8
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#define PMU_TIMEOUT_CNT_HI 0xdc
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#define PMU_CPUAPM_CON(cpu) (0xe0 + (cpu) * 0x4)
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#define CORES_PM_DISABLE 0x0
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#define CLST_CPUS_MSK 0xf
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#define PD_CTR_LOOP 500
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#define PD_CHECK_LOOP 500
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#define WFEI_CHECK_LOOP 500
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#define BUS_IDLE_LOOP 1000
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enum pmu_wkup_cfg2 {
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pmu_cluster_wkup_en = 0,
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pmu_gpio_wkup_en = 2,
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pmu_sdio_wkup_en = 3,
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pmu_sdmmc_wkup_en = 4,
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pmu_uart0_wkup_en = 5,
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pmu_timer_wkup_en = 6,
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pmu_usbdev_wkup_en = 7,
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pmu_sft_wkup_en = 8,
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pmu_timeout_wkup_en = 10,
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};
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enum pmu_powermode_core_lo {
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pmu_global_int_dis = 0,
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pmu_core_src_gt = 1,
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pmu_cpu0_pd = 3,
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pmu_clr_core = 5,
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pmu_scu_pd = 6,
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pmu_l2_idle = 8,
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pmu_l2_flush = 9,
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pmu_clr_bus2main = 10,
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pmu_clr_peri2msch = 11,
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};
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enum pmu_powermode_core_hi {
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pmu_apll_pd_en = 3,
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pmu_dpll_pd_en = 4,
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pmu_cpll_pd_en = 5,
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pmu_gpll_pd_en = 6,
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pmu_npll_pd_en = 7,
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};
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enum pmu_powermode_common_lo {
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pmu_mode_en = 0,
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pmu_ddr_pd_en = 1,
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pmu_wkup_rst = 3,
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pmu_pll_pd = 4,
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pmu_pmu_use_if = 6,
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pmu_alive_use_if = 7,
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pmu_osc_dis = 8,
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pmu_input_clamp = 9,
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pmu_sref_enter = 10,
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pmu_ddrc_gt = 11,
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pmu_ddrio_ret = 12,
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pmu_ddrio_ret_deq = 13,
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pmu_clr_pmu = 14,
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pmu_clr_peri_pmu = 15,
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};
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enum pmu_powermode_common_hi {
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pmu_clr_bus = 0,
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pmu_clr_mmc = 1,
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pmu_clr_msch = 2,
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pmu_clr_nandc = 3,
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pmu_clr_gmac = 4,
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pmu_clr_vo = 5,
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pmu_clr_vi = 6,
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pmu_clr_gpu = 7,
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pmu_clr_usb = 8,
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pmu_clr_vpu = 9,
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pmu_clr_crypto = 10,
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pmu_wakeup_begin_cfg = 11,
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pmu_peri_clk_src_gt = 12,
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pmu_bus_clk_src_gt = 13,
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};
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enum pmu_pd_id {
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PD_CPU0 = 0,
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PD_CPU1 = 1,
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PD_CPU2 = 2,
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PD_CPU3 = 3,
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PD_SCU = 4,
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PD_USB = 5,
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PD_DDR = 6,
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PD_SDCARD = 8,
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PD_CRYPTO = 9,
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PD_GMAC = 10,
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PD_MMC_NAND = 11,
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PD_VPU = 12,
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PD_VO = 13,
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PD_VI = 14,
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PD_GPU = 15,
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PD_END = 16,
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};
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enum pmu_bus_id {
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BUS_ID_BUS = 0,
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BUS_ID_BUS2MAIN = 1,
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BUS_ID_GPU = 2,
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BUS_ID_CORE = 3,
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BUS_ID_CRYPTO = 4,
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BUS_ID_MMC = 5,
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BUS_ID_GMAC = 6,
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BUS_ID_VO = 7,
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BUS_ID_VI = 8,
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BUS_ID_SDCARD = 9,
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BUS_ID_USB = 10,
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BUS_ID_MSCH = 11,
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BUS_ID_PERI = 12,
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BUS_ID_PMU = 13,
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BUS_ID_VPU = 14,
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BUS_ID_PERI2MSCH = 15,
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};
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enum pmu_pd_state {
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pmu_pd_on = 0,
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pmu_pd_off = 1
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};
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enum pmu_bus_state {
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bus_active = 0,
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bus_idle = 1,
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};
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enum cores_pm_ctr_mode {
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core_pwr_pd = 0,
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core_pwr_wfi = 1,
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core_pwr_wfi_int = 2
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};
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enum pmu_cores_pm_by_wfi {
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core_pm_en = 0,
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core_pm_int_wakeup_en,
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core_pm_dis_int,
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core_pm_sft_wakeup_en
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};
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/*****************************************************************************
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* pmu_sgrf
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*****************************************************************************/
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#define PMUSGRF_SOC_CON(i) ((i) * 0x4)
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/*****************************************************************************
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* pmu_grf
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*****************************************************************************/
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#define GPIO0A_IOMUX 0x0
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#define GPIO0B_IOMUX 0x4
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#define GPIO0C_IOMUX 0x8
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#define GPIO0A_PULL 0x10
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#define GPIO0L_SMT 0x38
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#define GPIO0H_SMT 0x3c
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#define PMUGRF_SOC_CON(i) (0x100 + (i) * 4)
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#define PMUGRF_PVTM_CON0 0x180
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#define PMUGRF_PVTM_CON1 0x184
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#define PMUGRF_PVTM_ST0 0x190
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#define PMUGRF_PVTM_ST1 0x194
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#define PVTM_CALC_CNT 0x200
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#define PMUGRF_OS_REG(n) (0x200 + (n) * 4)
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#define GPIO0A6_IOMUX_MSK (0x3 << 12)
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#define GPIO0A6_IOMUX_GPIO (0x0 << 12)
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#define GPIO0A6_IOMUX_RSTOUT (0x1 << 12)
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#define GPIO0A6_IOMUX_SHTDN (0x2 << 12)
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enum px30_pmugrf_pvtm_con0 {
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pgrf_pvtm_st = 0,
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pgrf_pvtm_en = 1,
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pgrf_pvtm_div = 2,
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};
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/*****************************************************************************
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* pmu_cru
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*****************************************************************************/
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#define CRU_PMU_MODE 0x20
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#define CRU_PMU_CLKSEL_CON 0x40
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#define CRU_PMU_CLKSELS_CON(i) (CRU_PMU_CLKSEL_CON + (i) * 4)
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#define CRU_PMU_CLKSEL_CON_CNT 5
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#define CRU_PMU_CLKGATE_CON 0x80
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#define CRU_PMU_CLKGATES_CON(i) (CRU_PMU_CLKGATE_CON + (i) * 4)
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#define CRU_PMU_CLKGATE_CON_CNT 2
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#define CRU_PMU_ATCS_CON 0xc0
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#define CRU_PMU_ATCSS_CON(i) (CRU_PMU_ATCS_CON + (i) * 4)
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#define CRU_PMU_ATCS_CON_CNT 2
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/*****************************************************************************
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* pmusgrf
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*****************************************************************************/
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#define PMUSGRF_RSTOUT_EN (0x7 << 10)
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#define PMUSGRF_RSTOUT_FST 10
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#define PMUSGRF_RSTOUT_TSADC 11
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#define PMUSGRF_RSTOUT_WDT 12
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#define PMUGRF_SOC_CON2_US_WMSK (0x1fff << 16)
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#define PMUGRF_SOC_CON2_MAX_341US 0x1fff
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#define PMUGRF_SOC_CON2_200US 0x12c0
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#define PMUGRF_FAILSAFE_SHTDN_TSADC BIT(0)
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#define PMUGRF_FAILSAFE_SHTDN_WDT BIT(1)
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/*****************************************************************************
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* QOS
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*****************************************************************************/
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#define CPU_AXI_QOS_ID_COREID 0x00
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#define CPU_AXI_QOS_REVISIONID 0x04
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#define CPU_AXI_QOS_PRIORITY 0x08
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#define CPU_AXI_QOS_MODE 0x0c
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#define CPU_AXI_QOS_BANDWIDTH 0x10
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#define CPU_AXI_QOS_SATURATION 0x14
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#define CPU_AXI_QOS_EXTCONTROL 0x18
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#define CPU_AXI_QOS_NUM_REGS 0x07
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#define CPU_AXI_CPU_QOS_BASE 0xff508000
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#define CPU_AXI_GPU_QOS_BASE 0xff520000
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#define CPU_AXI_ISP_128M_QOS_BASE 0xff548000
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#define CPU_AXI_ISP_RD_QOS_BASE 0xff548080
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#define CPU_AXI_ISP_WR_QOS_BASE 0xff548100
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#define CPU_AXI_ISP_M1_QOS_BASE 0xff548180
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#define CPU_AXI_VIP_QOS_BASE 0xff548200
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#define CPU_AXI_RGA_RD_QOS_BASE 0xff550000
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#define CPU_AXI_RGA_WR_QOS_BASE 0xff550080
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#define CPU_AXI_VOP_M0_QOS_BASE 0xff550100
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#define CPU_AXI_VOP_M1_QOS_BASE 0xff550180
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#define CPU_AXI_VPU_QOS_BASE 0xff558000
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#define CPU_AXI_VPU_R128_QOS_BASE 0xff558080
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#define CPU_AXI_DCF_QOS_BASE 0xff500000
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#define CPU_AXI_DMAC_QOS_BASE 0xff500080
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#define CPU_AXI_CRYPTO_QOS_BASE 0xff510000
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#define CPU_AXI_GMAC_QOS_BASE 0xff518000
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#define CPU_AXI_EMMC_QOS_BASE 0xff538000
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#define CPU_AXI_NAND_QOS_BASE 0xff538080
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#define CPU_AXI_SDIO_QOS_BASE 0xff538100
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#define CPU_AXI_SFC_QOS_BASE 0xff538180
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#define CPU_AXI_SDMMC_QOS_BASE 0xff52c000
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#define CPU_AXI_USB_HOST_QOS_BASE 0xff540000
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#define CPU_AXI_USB_OTG_QOS_BASE 0xff540080
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#define PX30_CPU_AXI_SAVE_QOS(array, base) do { \
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array[0] = mmio_read_32(base + CPU_AXI_QOS_ID_COREID); \
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array[1] = mmio_read_32(base + CPU_AXI_QOS_REVISIONID); \
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array[2] = mmio_read_32(base + CPU_AXI_QOS_PRIORITY); \
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array[3] = mmio_read_32(base + CPU_AXI_QOS_MODE); \
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array[4] = mmio_read_32(base + CPU_AXI_QOS_BANDWIDTH); \
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array[5] = mmio_read_32(base + CPU_AXI_QOS_SATURATION); \
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array[6] = mmio_read_32(base + CPU_AXI_QOS_EXTCONTROL); \
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} while (0)
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#define PX30_CPU_AXI_RESTORE_QOS(array, base) do { \
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mmio_write_32(base + CPU_AXI_QOS_ID_COREID, array[0]); \
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mmio_write_32(base + CPU_AXI_QOS_REVISIONID, array[1]); \
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mmio_write_32(base + CPU_AXI_QOS_PRIORITY, array[2]); \
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mmio_write_32(base + CPU_AXI_QOS_MODE, array[3]); \
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mmio_write_32(base + CPU_AXI_QOS_BANDWIDTH, array[4]); \
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mmio_write_32(base + CPU_AXI_QOS_SATURATION, array[5]); \
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mmio_write_32(base + CPU_AXI_QOS_EXTCONTROL, array[6]); \
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} while (0)
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#define SAVE_QOS(array, NAME) \
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PX30_CPU_AXI_SAVE_QOS(array, CPU_AXI_##NAME##_QOS_BASE)
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#define RESTORE_QOS(array, NAME) \
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PX30_CPU_AXI_RESTORE_QOS(array, CPU_AXI_##NAME##_QOS_BASE)
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#endif /* __PMU_H__ */
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+103
@@ -0,0 +1,103 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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||||
* SPDX-License-Identifier: BSD-3-Clause
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||||
*/
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#include <assert.h>
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#include <ddr_parameter.h>
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#include <plat_private.h>
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#include <secure.h>
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#include <px30_def.h>
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/**
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* There are 8 regions for DDR security control
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* @rgn - the DDR regions 0 ~ 7 which are can be configured.
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* @st - start address to set as secure
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* @sz - length of area to set as secure
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* The internal unit is megabytes, so memory areas need to be aligned
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* to megabyte borders.
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*/
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static void secure_ddr_region(uint32_t rgn,
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uintptr_t st, size_t sz)
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{
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uintptr_t ed = st + sz;
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uintptr_t st_mb, ed_mb;
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uint32_t val;
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assert(rgn <= 7);
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assert(st < ed);
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/* check aligned 1MB */
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assert(st % SIZE_M(1) == 0);
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assert(ed % SIZE_M(1) == 0);
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st_mb = st / SIZE_M(1);
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ed_mb = ed / SIZE_M(1);
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/* map top and base */
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mmio_write_32(FIREWALL_DDR_BASE +
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FIREWALL_DDR_FW_DDR_RGN(rgn),
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RG_MAP_SECURE(ed_mb, st_mb));
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/* enable secure */
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val = mmio_read_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_CON_REG);
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val |= BIT(rgn);
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mmio_write_32(FIREWALL_DDR_BASE +
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FIREWALL_DDR_FW_DDR_CON_REG, val);
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}
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void secure_timer_init(void)
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{
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mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
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TIMER_DIS);
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||||
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mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff);
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mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff);
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/* auto reload & enable the timer */
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mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
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TIMER_EN | TIMER_FMODE);
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||||
}
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||||
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||||
void sgrf_init(void)
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||||
{
|
||||
#ifdef PLAT_RK_SECURE_DDR_MINILOADER
|
||||
uint32_t i;
|
||||
struct param_ddr_usage usg;
|
||||
|
||||
/* general secure regions */
|
||||
usg = ddr_region_usage_parse(DDR_PARAM_BASE,
|
||||
PLAT_MAX_DDR_CAPACITY_MB);
|
||||
|
||||
/* region-0 for TF-A, region-1 for optional OP-TEE */
|
||||
assert(usg.s_nr < 7);
|
||||
|
||||
for (i = 0; i < usg.s_nr; i++)
|
||||
secure_ddr_region(7 - i, usg.s_top[i], usg.s_base[i]);
|
||||
#endif
|
||||
|
||||
/* secure the trustzone ram */
|
||||
secure_ddr_region(0, TZRAM_BASE, TZRAM_SIZE);
|
||||
|
||||
/* set all slave ip into no-secure, except stimer */
|
||||
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS);
|
||||
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS);
|
||||
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS);
|
||||
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS);
|
||||
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000);
|
||||
|
||||
/* set master crypto to no-secure, dcf to secure */
|
||||
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003);
|
||||
|
||||
/* set DMAC into no-secure */
|
||||
mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS);
|
||||
mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0);
|
||||
mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16);
|
||||
mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS);
|
||||
|
||||
/* soft reset dma before use */
|
||||
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ);
|
||||
udelay(5);
|
||||
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS);
|
||||
}
|
||||
+65
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SECURE_H
|
||||
#define SECURE_H
|
||||
|
||||
/***************************************************************************
|
||||
* SGRF
|
||||
***************************************************************************/
|
||||
#define SGRF_SOC_CON(i) ((i) * 0x4)
|
||||
#define SGRF_DMAC_CON(i) (0x30 + (i) * 0x4)
|
||||
|
||||
#define SGRF_MST_S_ALL_NS 0xffffffff
|
||||
#define SGRF_SLV_S_ALL_NS 0xffff0000
|
||||
#define DMA_IRQ_BOOT_NS 0xffffffff
|
||||
#define DMA_PERI_CH_NS_15_0 0xffffffff
|
||||
#define DMA_PERI_CH_NS_19_16 0x000f000f
|
||||
#define DMA_MANAGER_BOOT_NS 0x00010001
|
||||
#define DMA_SOFTRST_REQ BITS_WITH_WMASK(1, 0x1, 12)
|
||||
#define DMA_SOFTRST_RLS BITS_WITH_WMASK(0, 0x1, 12)
|
||||
|
||||
/***************************************************************************
|
||||
* DDR FIREWALL
|
||||
***************************************************************************/
|
||||
#define FIREWALL_DDR_FW_DDR_RGN(i) ((i) * 0x4)
|
||||
#define FIREWALL_DDR_FW_DDR_MST(i) (0x20 + (i) * 0x4)
|
||||
#define FIREWALL_DDR_FW_DDR_CON_REG 0x40
|
||||
#define FIREWALL_DDR_FW_DDR_RGN_NUM 8
|
||||
#define FIREWALL_DDR_FW_DDR_MST_NUM 6
|
||||
|
||||
#define PLAT_MAX_DDR_CAPACITY_MB 4096
|
||||
#define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base))
|
||||
|
||||
/**************************************************
|
||||
* secure timer
|
||||
**************************************************/
|
||||
|
||||
/* chanal0~5 */
|
||||
#define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
|
||||
|
||||
#define TIMER_LOAD_COUNT0 0x0
|
||||
#define TIMER_LOAD_COUNT1 0x4
|
||||
|
||||
#define TIMER_CUR_VALUE0 0x8
|
||||
#define TIMER_CUR_VALUE1 0xc
|
||||
|
||||
#define TIMER_CONTROL_REG 0x10
|
||||
#define TIMER_INTSTATUS 0x18
|
||||
|
||||
#define TIMER_DIS 0x0
|
||||
#define TIMER_EN 0x1
|
||||
|
||||
#define TIMER_FMODE (0x0 << 1)
|
||||
#define TIMER_RMODE (0x1 << 1)
|
||||
|
||||
#define TIMER_LOAD_COUNT0_MSK (0xffffffff)
|
||||
#define TIMER_LOAD_COUNT1_MSK (0xffffffff00000000)
|
||||
|
||||
void secure_timer_init(void);
|
||||
void sgrf_init(void);
|
||||
|
||||
#endif /* SECURE_H */
|
||||
@@ -0,0 +1,134 @@
|
||||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/console.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
#include <pmu.h>
|
||||
#include <px30_def.h>
|
||||
#include <secure.h>
|
||||
#include <soc.h>
|
||||
#include <rockchip_sip_svc.h>
|
||||
|
||||
/* Aggregate of all devices in the first GB */
|
||||
#define PX30_DEV_RNG0_BASE 0xff000000
|
||||
#define PX30_DEV_RNG0_SIZE 0x00ff0000
|
||||
|
||||
const mmap_region_t plat_rk_mmap[] = {
|
||||
MAP_REGION_FLAT(PX30_DEV_RNG0_BASE, PX30_DEV_RNG0_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(SHARE_MEM_BASE, SHARE_MEM_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(DDR_PARAM_BASE, DDR_PARAM_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_SECURE),
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
/* The RockChip power domain tree descriptor */
|
||||
const unsigned char rockchip_power_domain_tree_desc[] = {
|
||||
/* No of root nodes */
|
||||
PLATFORM_SYSTEM_COUNT,
|
||||
/* No of children for the root node */
|
||||
PLATFORM_CLUSTER_COUNT,
|
||||
/* No of children for the first cluster node */
|
||||
PLATFORM_CLUSTER0_CORE_COUNT,
|
||||
};
|
||||
|
||||
void clk_gate_con_save(uint32_t *clkgt_save)
|
||||
{
|
||||
uint32_t i, j;
|
||||
|
||||
for (i = 0; i < CRU_CLKGATES_CON_CNT; i++)
|
||||
clkgt_save[i] =
|
||||
mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i));
|
||||
j = i;
|
||||
for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++)
|
||||
clkgt_save[j] =
|
||||
mmio_read_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i));
|
||||
}
|
||||
|
||||
void clk_gate_con_restore(uint32_t *clkgt_save)
|
||||
{
|
||||
uint32_t i, j;
|
||||
|
||||
for (i = 0; i < CRU_CLKGATES_CON_CNT; i++)
|
||||
mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i),
|
||||
WITH_16BITS_WMSK(clkgt_save[i]));
|
||||
|
||||
j = i;
|
||||
for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++)
|
||||
mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i),
|
||||
WITH_16BITS_WMSK(clkgt_save[j]));
|
||||
}
|
||||
|
||||
void clk_gate_con_disable(void)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < CRU_CLKGATES_CON_CNT; i++)
|
||||
mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i),
|
||||
0xffff0000);
|
||||
|
||||
for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++)
|
||||
mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i),
|
||||
0xffff0000);
|
||||
}
|
||||
|
||||
static void soc_reset_config_all(void)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
/* tsadc and wdt can trigger a first rst */
|
||||
tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON);
|
||||
tmp |= CRU_GLB_RST_TSADC_FST | CRU_GLB_RST_WDT_FST;
|
||||
mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp);
|
||||
return;
|
||||
tmp = mmio_read_32(PMUGRF_BASE + PMUGRF_SOC_CON(3));
|
||||
tmp &= ~(PMUGRF_FAILSAFE_SHTDN_TSADC | PMUGRF_FAILSAFE_SHTDN_WDT);
|
||||
mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(3), tmp);
|
||||
|
||||
/* wdt pin rst eable */
|
||||
mmio_write_32(GRF_BASE + GRF_SOC_CON(2),
|
||||
BIT_WITH_WMSK(GRF_SOC_CON2_NSWDT_RST_EN));
|
||||
}
|
||||
|
||||
void px30_soc_reset_config(void)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
/* enable soc ip rst hold time cfg */
|
||||
tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON);
|
||||
tmp |= BIT(CRU_GLB_RST_TSADC_EXT) | BIT(CRU_GLB_RST_WDT_EXT);
|
||||
mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp);
|
||||
/* soc ip rst hold time, 24m */
|
||||
tmp = mmio_read_32(CRU_BASE + CRU_GLB_CNT_TH);
|
||||
tmp &= ~CRU_GLB_CNT_RST_MSK;
|
||||
tmp |= (CRU_GLB_CNT_RST_1MS / 2);
|
||||
mmio_write_32(CRU_BASE + CRU_GLB_CNT_TH, tmp);
|
||||
|
||||
mmio_write_32(PMUSGRF_BASE + PMUSGRF_SOC_CON(0),
|
||||
BIT_WITH_WMSK(PMUSGRF_RSTOUT_FST) |
|
||||
BIT_WITH_WMSK(PMUSGRF_RSTOUT_TSADC) |
|
||||
BIT_WITH_WMSK(PMUSGRF_RSTOUT_WDT));
|
||||
|
||||
/* rst_out pulse time */
|
||||
mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(2),
|
||||
PMUGRF_SOC_CON2_MAX_341US | PMUGRF_SOC_CON2_US_WMSK);
|
||||
|
||||
soc_reset_config_all();
|
||||
}
|
||||
|
||||
void plat_rockchip_soc_init(void)
|
||||
{
|
||||
secure_timer_init();
|
||||
sgrf_init();
|
||||
}
|
||||
@@ -0,0 +1,118 @@
|
||||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOC_H__
|
||||
#define __SOC_H__
|
||||
|
||||
#include <plat_private.h>
|
||||
|
||||
#ifndef BITS_WMSK
|
||||
#define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT))
|
||||
#endif
|
||||
|
||||
enum plls_id {
|
||||
APLL_ID = 0,
|
||||
DPLL_ID,
|
||||
CPLL_ID,
|
||||
NPLL_ID,
|
||||
GPLL_ID,
|
||||
END_PLL_ID,
|
||||
};
|
||||
|
||||
enum pll_mode {
|
||||
SLOW_MODE,
|
||||
NORM_MODE,
|
||||
DEEP_SLOW_MODE,
|
||||
};
|
||||
|
||||
/***************************************************************************
|
||||
* GRF
|
||||
***************************************************************************/
|
||||
#define GRF_SOC_CON(i) (0x0400 + (i) * 4)
|
||||
#define GRF_PD_VO_CON0 0x0434
|
||||
#define GRF_SOC_STATUS0 0x0480
|
||||
#define GRF_CPU_STATUS0 0x0520
|
||||
#define GRF_CPU_STATUS1 0x0524
|
||||
#define GRF_SOC_NOC_CON0 0x0530
|
||||
#define GRF_SOC_NOC_CON1 0x0534
|
||||
|
||||
#define CKECK_WFE_MSK 0x1
|
||||
#define CKECK_WFI_MSK 0x10
|
||||
#define CKECK_WFEI_MSK 0x11
|
||||
|
||||
#define GRF_SOC_CON2_NSWDT_RST_EN 12
|
||||
|
||||
/***************************************************************************
|
||||
* cru
|
||||
***************************************************************************/
|
||||
#define CRU_MODE 0xa0
|
||||
#define CRU_MISC 0xa4
|
||||
#define CRU_GLB_CNT_TH 0xb0
|
||||
#define CRU_GLB_RST_ST 0xb4
|
||||
#define CRU_GLB_SRST_FST 0xb8
|
||||
#define CRU_GLB_SRST_SND 0xbc
|
||||
#define CRU_GLB_RST_CON 0xc0
|
||||
|
||||
#define CRU_CLKSEL_CON 0x100
|
||||
#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + (i) * 4)
|
||||
#define CRU_CLKSEL_CON_CNT 60
|
||||
|
||||
#define CRU_CLKGATE_CON 0x200
|
||||
#define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + (i) * 4)
|
||||
#define CRU_CLKGATES_CON_CNT 18
|
||||
|
||||
#define CRU_SOFTRST_CON 0x300
|
||||
#define CRU_SOFTRSTS_CON(n) (CRU_SOFTRST_CON + ((n) * 4))
|
||||
#define CRU_SOFTRSTS_CON_CNT 12
|
||||
|
||||
#define CRU_AUTOCS_CON0(id) (0x400 + (id) * 8)
|
||||
#define CRU_AUTOCS_CON1(id) (0x404 + (id) * 8)
|
||||
|
||||
#define CRU_CONS_GATEID(i) (16 * (i))
|
||||
#define GATE_ID(reg, bit) ((reg) * 16 + (bit))
|
||||
|
||||
#define CRU_GLB_SRST_FST_VALUE 0xfdb9
|
||||
#define CRU_GLB_SRST_SND_VALUE 0xeca8
|
||||
|
||||
#define CRU_GLB_RST_TSADC_EXT 6
|
||||
#define CRU_GLB_RST_WDT_EXT 7
|
||||
|
||||
#define CRU_GLB_CNT_RST_MSK 0xffff
|
||||
#define CRU_GLB_CNT_RST_1MS 0x5DC0
|
||||
|
||||
#define CRU_GLB_RST_TSADC_FST BIT(0)
|
||||
#define CRU_GLB_RST_WDT_FST BIT(1)
|
||||
|
||||
/***************************************************************************
|
||||
* pll
|
||||
***************************************************************************/
|
||||
#define CRU_PLL_CONS(id, i) ((id) * 0x20 + (i) * 4)
|
||||
#define PLL_CON(i) ((i) * 4)
|
||||
#define PLL_CON_CNT 5
|
||||
#define PLL_LOCK_MSK BIT(10)
|
||||
#define PLL_MODE_SHIFT(id) ((id) == CPLL_ID ? \
|
||||
2 : \
|
||||
((id) == DPLL_ID ? 4 : 2 * (id)))
|
||||
#define PLL_MODE_MSK(id) (0x3 << PLL_MODE_SHIFT(id))
|
||||
|
||||
#define PLL_LOCKED_TIMEOUT 600000U
|
||||
|
||||
/***************************************************************************
|
||||
* GPIO
|
||||
***************************************************************************/
|
||||
#define SWPORTA_DR 0x00
|
||||
#define SWPORTA_DDR 0x04
|
||||
#define GPIO_INTEN 0x30
|
||||
#define GPIO_INT_STATUS 0x40
|
||||
#define GPIO_NUMS 4
|
||||
|
||||
void clk_gate_con_save(uint32_t *clkgt_save);
|
||||
void clk_gate_con_restore(uint32_t *clkgt_save);
|
||||
void clk_gate_con_disable(void);
|
||||
|
||||
void px30_soc_reset_config(void);
|
||||
|
||||
#endif /* __SOC_H__ */
|
||||
Reference in New Issue
Block a user