GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/console.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#include <pmu.h>
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#include <px30_def.h>
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#include <secure.h>
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#include <soc.h>
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#include <rockchip_sip_svc.h>
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/* Aggregate of all devices in the first GB */
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#define PX30_DEV_RNG0_BASE 0xff000000
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#define PX30_DEV_RNG0_SIZE 0x00ff0000
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const mmap_region_t plat_rk_mmap[] = {
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MAP_REGION_FLAT(PX30_DEV_RNG0_BASE, PX30_DEV_RNG0_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(SHARE_MEM_BASE, SHARE_MEM_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DDR_PARAM_BASE, DDR_PARAM_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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{ 0 }
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};
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/* The RockChip power domain tree descriptor */
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const unsigned char rockchip_power_domain_tree_desc[] = {
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/* No of root nodes */
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PLATFORM_SYSTEM_COUNT,
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/* No of children for the root node */
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PLATFORM_CLUSTER_COUNT,
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/* No of children for the first cluster node */
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PLATFORM_CLUSTER0_CORE_COUNT,
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};
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void clk_gate_con_save(uint32_t *clkgt_save)
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{
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uint32_t i, j;
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for (i = 0; i < CRU_CLKGATES_CON_CNT; i++)
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clkgt_save[i] =
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mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i));
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j = i;
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for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++)
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clkgt_save[j] =
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mmio_read_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i));
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}
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void clk_gate_con_restore(uint32_t *clkgt_save)
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{
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uint32_t i, j;
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for (i = 0; i < CRU_CLKGATES_CON_CNT; i++)
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mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i),
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WITH_16BITS_WMSK(clkgt_save[i]));
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j = i;
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for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++)
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mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i),
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WITH_16BITS_WMSK(clkgt_save[j]));
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}
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void clk_gate_con_disable(void)
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{
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uint32_t i;
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for (i = 0; i < CRU_CLKGATES_CON_CNT; i++)
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mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i),
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0xffff0000);
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for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++)
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mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i),
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0xffff0000);
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}
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static void soc_reset_config_all(void)
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{
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uint32_t tmp;
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/* tsadc and wdt can trigger a first rst */
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tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON);
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tmp |= CRU_GLB_RST_TSADC_FST | CRU_GLB_RST_WDT_FST;
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mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp);
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return;
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tmp = mmio_read_32(PMUGRF_BASE + PMUGRF_SOC_CON(3));
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tmp &= ~(PMUGRF_FAILSAFE_SHTDN_TSADC | PMUGRF_FAILSAFE_SHTDN_WDT);
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mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(3), tmp);
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/* wdt pin rst eable */
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mmio_write_32(GRF_BASE + GRF_SOC_CON(2),
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BIT_WITH_WMSK(GRF_SOC_CON2_NSWDT_RST_EN));
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}
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void px30_soc_reset_config(void)
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{
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uint32_t tmp;
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/* enable soc ip rst hold time cfg */
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tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON);
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tmp |= BIT(CRU_GLB_RST_TSADC_EXT) | BIT(CRU_GLB_RST_WDT_EXT);
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mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp);
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/* soc ip rst hold time, 24m */
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tmp = mmio_read_32(CRU_BASE + CRU_GLB_CNT_TH);
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tmp &= ~CRU_GLB_CNT_RST_MSK;
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tmp |= (CRU_GLB_CNT_RST_1MS / 2);
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mmio_write_32(CRU_BASE + CRU_GLB_CNT_TH, tmp);
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mmio_write_32(PMUSGRF_BASE + PMUSGRF_SOC_CON(0),
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BIT_WITH_WMSK(PMUSGRF_RSTOUT_FST) |
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BIT_WITH_WMSK(PMUSGRF_RSTOUT_TSADC) |
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BIT_WITH_WMSK(PMUSGRF_RSTOUT_WDT));
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/* rst_out pulse time */
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mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(2),
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PMUGRF_SOC_CON2_MAX_341US | PMUGRF_SOC_CON2_US_WMSK);
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soc_reset_config_all();
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}
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void plat_rockchip_soc_init(void)
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{
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secure_timer_init();
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sgrf_init();
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}
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@@ -0,0 +1,118 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SOC_H__
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#define __SOC_H__
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#include <plat_private.h>
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#ifndef BITS_WMSK
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#define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT))
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#endif
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enum plls_id {
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APLL_ID = 0,
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DPLL_ID,
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CPLL_ID,
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NPLL_ID,
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GPLL_ID,
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END_PLL_ID,
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};
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enum pll_mode {
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SLOW_MODE,
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NORM_MODE,
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DEEP_SLOW_MODE,
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};
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/***************************************************************************
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* GRF
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***************************************************************************/
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#define GRF_SOC_CON(i) (0x0400 + (i) * 4)
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#define GRF_PD_VO_CON0 0x0434
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#define GRF_SOC_STATUS0 0x0480
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#define GRF_CPU_STATUS0 0x0520
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#define GRF_CPU_STATUS1 0x0524
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#define GRF_SOC_NOC_CON0 0x0530
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#define GRF_SOC_NOC_CON1 0x0534
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#define CKECK_WFE_MSK 0x1
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#define CKECK_WFI_MSK 0x10
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#define CKECK_WFEI_MSK 0x11
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#define GRF_SOC_CON2_NSWDT_RST_EN 12
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/***************************************************************************
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* cru
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***************************************************************************/
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#define CRU_MODE 0xa0
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#define CRU_MISC 0xa4
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#define CRU_GLB_CNT_TH 0xb0
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#define CRU_GLB_RST_ST 0xb4
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#define CRU_GLB_SRST_FST 0xb8
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#define CRU_GLB_SRST_SND 0xbc
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#define CRU_GLB_RST_CON 0xc0
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#define CRU_CLKSEL_CON 0x100
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#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + (i) * 4)
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#define CRU_CLKSEL_CON_CNT 60
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#define CRU_CLKGATE_CON 0x200
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#define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + (i) * 4)
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#define CRU_CLKGATES_CON_CNT 18
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#define CRU_SOFTRST_CON 0x300
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#define CRU_SOFTRSTS_CON(n) (CRU_SOFTRST_CON + ((n) * 4))
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#define CRU_SOFTRSTS_CON_CNT 12
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#define CRU_AUTOCS_CON0(id) (0x400 + (id) * 8)
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#define CRU_AUTOCS_CON1(id) (0x404 + (id) * 8)
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#define CRU_CONS_GATEID(i) (16 * (i))
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#define GATE_ID(reg, bit) ((reg) * 16 + (bit))
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#define CRU_GLB_SRST_FST_VALUE 0xfdb9
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#define CRU_GLB_SRST_SND_VALUE 0xeca8
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#define CRU_GLB_RST_TSADC_EXT 6
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#define CRU_GLB_RST_WDT_EXT 7
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#define CRU_GLB_CNT_RST_MSK 0xffff
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#define CRU_GLB_CNT_RST_1MS 0x5DC0
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#define CRU_GLB_RST_TSADC_FST BIT(0)
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#define CRU_GLB_RST_WDT_FST BIT(1)
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/***************************************************************************
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* pll
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***************************************************************************/
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#define CRU_PLL_CONS(id, i) ((id) * 0x20 + (i) * 4)
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#define PLL_CON(i) ((i) * 4)
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#define PLL_CON_CNT 5
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#define PLL_LOCK_MSK BIT(10)
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#define PLL_MODE_SHIFT(id) ((id) == CPLL_ID ? \
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2 : \
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((id) == DPLL_ID ? 4 : 2 * (id)))
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#define PLL_MODE_MSK(id) (0x3 << PLL_MODE_SHIFT(id))
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#define PLL_LOCKED_TIMEOUT 600000U
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/***************************************************************************
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* GPIO
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***************************************************************************/
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#define SWPORTA_DR 0x00
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#define SWPORTA_DDR 0x04
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#define GPIO_INTEN 0x30
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#define GPIO_INT_STATUS 0x40
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#define GPIO_NUMS 4
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void clk_gate_con_save(uint32_t *clkgt_save);
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void clk_gate_con_restore(uint32_t *clkgt_save);
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void clk_gate_con_disable(void);
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void px30_soc_reset_config(void);
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#endif /* __SOC_H__ */
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