GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <plat_private.h>
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#include <secure.h>
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#include <soc.h>
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static void sgrf_ddr_rgn_global_bypass(uint32_t bypass)
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{
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if (bypass)
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/* set bypass (non-secure regions) for whole ddr regions */
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(21),
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SGRF_DDR_RGN_BYPS);
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else
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/* cancel bypass for whole ddr regions */
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(21),
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SGRF_DDR_RGN_NO_BYPS);
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}
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/**
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* There are 8 + 1 regions for DDR secure control:
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* DDR_RGN_0 ~ DDR_RGN_7: Per DDR_RGNs grain size is 1MB
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* DDR_RGN_X - the memories of exclude DDR_RGN_0 ~ DDR_RGN_7
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*
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* SGRF_SOC_CON6 - start address of RGN_0 + control
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* SGRF_SOC_CON7 - end address of RGN_0
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* ...
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* SGRF_SOC_CON20 - start address of the RGN_7 + control
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* SGRF_SOC_CON21 - end address of the RGN_7 + RGN_X control
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*
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* @rgn - the DDR regions 0 ~ 7 which are can be configured.
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* @st - start address to set as secure
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* @sz - length of area to set as secure
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* The @st_mb and @ed_mb indicate the start and end addresses for which to set
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* the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the
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* address range 0x0 ~ 0xfffff is secure.
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*
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* For example, if we would like to set the range [0, 32MB) is security via
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* DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31.
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*/
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static void sgrf_ddr_rgn_config(uint32_t rgn, uintptr_t st, size_t sz)
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{
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uintptr_t ed = st + sz;
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uintptr_t st_mb, ed_mb;
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assert(rgn <= 7);
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assert(st < ed);
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/* check aligned 1MB */
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assert(st % SIZE_M(1) == 0);
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assert(ed % SIZE_M(1) == 0);
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st_mb = st / SIZE_M(1);
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ed_mb = ed / SIZE_M(1);
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/* set ddr region addr start */
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)),
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BITS_WITH_WMASK(st_mb, SGRF_DDR_RGN_ADDR_WMSK, 0));
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/* set ddr region addr end */
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2) + 1),
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BITS_WITH_WMASK((ed_mb - 1), SGRF_DDR_RGN_ADDR_WMSK, 0));
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/* select region security */
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)),
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SGRF_DDR_RGN_SECURE_SEL);
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/* enable region security */
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)),
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SGRF_DDR_RGN_SECURE_EN);
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}
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void secure_watchdog_gate(void)
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{
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), SGRF_PCLK_WDT_GATE);
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}
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void secure_watchdog_ungate(void)
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{
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), SGRF_PCLK_WDT_UNGATE);
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}
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__pmusramfunc void sram_secure_timer_init(void)
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{
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mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, 0);
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mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT0, 0xffffffff);
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mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT1, 0xffffffff);
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/* auto reload & enable the timer */
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mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN);
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}
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void secure_gic_init(void)
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{
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/* (re-)enable non-secure access to the gic*/
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mmio_write_32(CORE_AXI_BUS_BASE + CORE_AXI_SECURITY0,
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AXI_SECURITY0_GIC);
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}
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void secure_timer_init(void)
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{
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mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, 0);
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mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT0, 0xffffffff);
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mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT1, 0xffffffff);
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/* auto reload & enable the timer */
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mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN);
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}
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void secure_sgrf_init(void)
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{
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/*
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* We use the first sram part to talk to the bootrom,
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* so make it secure.
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*/
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mmio_write_32(TZPC_BASE + TZPC_R0SIZE, TZPC_SRAM_SECURE_4K(1));
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secure_gic_init();
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/* set all master ip to non-secure */
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), SGRF_SOC_CON2_MST_NS);
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), SGRF_SOC_CON3_MST_NS);
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/* setting all configurable ip into non-secure */
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4),
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SGRF_SOC_CON4_SECURE_WMSK /*TODO:|SGRF_STIMER_SECURE*/);
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SOC_CON5_SECURE_WMSK);
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/* secure dma to non-secure */
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mmio_write_32(TZPC_BASE + TZPC_DECPROT1SET, 0xff);
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mmio_write_32(TZPC_BASE + TZPC_DECPROT2SET, 0xff);
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mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(1), 0x3800);
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dsb();
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/* rst dma1 */
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mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1),
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RST_DMA1_MSK | (RST_DMA1_MSK << 16));
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/* rst dma2 */
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mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4),
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RST_DMA2_MSK | (RST_DMA2_MSK << 16));
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dsb();
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/* release dma1 rst*/
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mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16));
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/* release dma2 rst*/
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mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16));
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}
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void secure_sgrf_ddr_rgn_init(void)
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{
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sgrf_ddr_rgn_config(0, TZRAM_BASE, TZRAM_SIZE);
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sgrf_ddr_rgn_global_bypass(0);
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}
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+102
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SECURE_H
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#define SECURE_H
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/******************************************************************************
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* TZPC TrustZone controller
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******************************************************************************/
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#define TZPC_R0SIZE 0x0
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#define TZPC_SRAM_SECURE_4K(n) ((n) > 0x200 ? 0x200 : (n))
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#define TZPC_DECPROT1STAT 0x80c
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#define TZPC_DECPROT1SET 0x810
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#define TZPC_DECPROT1CLR 0x814
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#define TZPC_DECPROT2STAT 0x818
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#define TZPC_DECPROT2SET 0x818
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#define TZPC_DECPROT2CLR 0x820
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/**************************************************
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* sgrf reg, offset
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**************************************************/
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/*
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* soc_con0-5 start at 0x0, soc_con6-... start art 0x50
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* adjusted for the 5 lower registers
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*/
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#define SGRF_SOC_CON(n) ((((n) < 6) ? 0x0 : 0x38) + (n) * 4)
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#define SGRF_BUSDMAC_CON(n) (0x20 + (n) * 4)
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#define SGRF_CPU_CON(n) (0x40 + (n) * 4)
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#define SGRF_SOC_STATUS(n) (0x100 + (n) * 4)
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#define SGRF_FAST_BOOT_ADDR 0x120
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/* SGRF_SOC_CON0 */
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#define SGRF_FAST_BOOT_ENA BIT_WITH_WMSK(8)
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#define SGRF_FAST_BOOT_DIS WMSK_BIT(8)
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#define SGRF_PCLK_WDT_GATE BIT_WITH_WMSK(6)
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#define SGRF_PCLK_WDT_UNGATE WMSK_BIT(6)
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#define SGRF_PCLK_STIMER_GATE BIT_WITH_WMSK(4)
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#define SGRF_SOC_CON2_MST_NS 0xffe0ffe0
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#define SGRF_SOC_CON3_MST_NS 0x003f003f
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/* SGRF_SOC_CON4 */
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#define SGRF_SOC_CON4_SECURE_WMSK 0xffff0000
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#define SGRF_DDRC1_SECURE BIT_WITH_WMSK(12)
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#define SGRF_DDRC0_SECURE BIT_WITH_WMSK(11)
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#define SGRF_PMUSRAM_SECURE BIT_WITH_WMSK(8)
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#define SGRF_WDT_SECURE BIT_WITH_WMSK(7)
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#define SGRF_STIMER_SECURE BIT_WITH_WMSK(6)
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/* SGRF_SOC_CON5 */
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#define SGRF_SLV_SEC_BYPS BIT_WITH_WMSK(15)
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#define SGRF_SLV_SEC_NO_BYPS WMSK_BIT(15)
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#define SGRF_SOC_CON5_SECURE_WMSK 0x00ff0000
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/* ddr regions in SGRF_SOC_CON6 and following */
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#define SGRF_DDR_RGN_SECURE_SEL BIT_WITH_WMSK(15)
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#define SGRF_DDR_RGN_SECURE_EN BIT_WITH_WMSK(14)
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#define SGRF_DDR_RGN_ADDR_WMSK 0x0fff
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/* SGRF_SOC_CON21 */
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/* All security of the DDR RGNs are bypassed */
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#define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(15)
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#define SGRF_DDR_RGN_NO_BYPS WMSK_BIT(15)
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/* SGRF_CPU_CON0 */
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#define SGRF_DAPDEVICE_ENA BIT_WITH_WMSK(0)
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#define SGRF_DAPDEVICE_MSK WMSK_BIT(0)
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/*****************************************************************************
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* core-axi
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*****************************************************************************/
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#define CORE_AXI_SECURITY0 0x08
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#define AXI_SECURITY0_GIC BIT(0)
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/*****************************************************************************
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* secure timer
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*****************************************************************************/
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#define TIMER_LOAD_COUNT0 0x00
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#define TIMER_LOAD_COUNT1 0x04
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#define TIMER_CURRENT_VALUE0 0x08
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#define TIMER_CURRENT_VALUE1 0x0C
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#define TIMER_CONTROL_REG 0x10
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#define TIMER_INTSTATUS 0x18
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#define TIMER_EN 0x1
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#define STIMER1_BASE (STIME_BASE + 0x20)
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/* export secure operating APIs */
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void secure_watchdog_gate(void);
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void secure_watchdog_ungate(void);
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void secure_gic_init(void);
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void secure_timer_init(void);
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void secure_sgrf_init(void);
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void secure_sgrf_ddr_rgn_init(void);
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__pmusramfunc void sram_secure_timer_init(void);
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#endif /* SECURE_H */
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