GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/console.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <ddr_parameter.h>
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#include <plat_private.h>
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#include <rk3328_def.h>
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#include <soc.h>
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/* Table of regions to map using the MMU. */
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const mmap_region_t plat_rk_mmap[] = {
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MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(UART1_BASE, UART1_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(UART2_BASE, UART2_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(GPIO0_BASE, GPIO0_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(GPIO1_BASE, GPIO1_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(GPIO2_BASE, GPIO2_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(GPIO3_BASE, GPIO3_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(GRF_BASE, GRF_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(FIREWALL_DDR_BASE, FIREWALL_DDR_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(FIREWALL_CFG_BASE, FIREWALL_CFG_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(STIME_BASE, STIME_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(GIC400_BASE, GIC400_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(SHARE_MEM_BASE, SHARE_MEM_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DDR_GRF_BASE, DDR_GRF_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DDR_UPCTL_BASE, DDR_UPCTL_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(PWM_BASE, PWM_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DDR_PARAM_BASE, DDR_PARAM_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(EFUSE8_BASE, EFUSE8_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(EFUSE32_BASE, EFUSE32_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DDR_PHY_BASE, DDR_PHY_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(SERVER_MSCH_BASE, SERVER_MSCH_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DDR_MONITOR_BASE, DDR_MONITOR_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(VOP_BASE, VOP_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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{ 0 }
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};
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/* The RockChip power domain tree descriptor */
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const unsigned char rockchip_power_domain_tree_desc[] = {
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/* No of root nodes */
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PLATFORM_SYSTEM_COUNT,
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/* No of children for the root node */
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PLATFORM_CLUSTER_COUNT,
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/* No of children for the first cluster node */
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PLATFORM_CLUSTER0_CORE_COUNT,
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};
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void secure_timer_init(void)
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{
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mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOADE_COUNT0, 0xffffffff);
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mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOADE_COUNT1, 0xffffffff);
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/* auto reload & enable the timer */
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mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN);
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}
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void sgrf_init(void)
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{
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#ifdef PLAT_RK_SECURE_DDR_MINILOADER
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uint32_t i, val;
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struct param_ddr_usage usg;
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/* general secure regions */
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usg = ddr_region_usage_parse(DDR_PARAM_BASE,
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PLAT_MAX_DDR_CAPACITY_MB);
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for (i = 0; i < usg.s_nr; i++) {
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/* enable secure */
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val = mmio_read_32(FIREWALL_DDR_BASE +
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FIREWALL_DDR_FW_DDR_CON_REG);
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val |= BIT(7 - i);
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mmio_write_32(FIREWALL_DDR_BASE +
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FIREWALL_DDR_FW_DDR_CON_REG, val);
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/* map top and base */
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mmio_write_32(FIREWALL_DDR_BASE +
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FIREWALL_DDR_FW_DDR_RGN(7 - i),
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RG_MAP_SECURE(usg.s_top[i], usg.s_base[i]));
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}
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#endif
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/* set ddr rgn0_top and rga0_top as 0 */
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mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0);
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/* set all slave ip into no-secure, except stimer */
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mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(0),
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SGRF_SLV_S_ALL_NS);
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mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(1),
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SGRF_SLV_S_ALL_NS);
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mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(2),
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SGRF_SLV_S_ALL_NS | STIMER_S);
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mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(3),
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SGRF_SLV_S_ALL_NS);
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/* set all master ip into no-secure */
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), 0xf0000000);
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), SGRF_MST_S_ALL_NS);
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_MST_S_ALL_NS);
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/* set DMAC into no-secure */
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mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_IRQ_BOOT_NS);
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mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(4), DMA_PERI_CH_NS_15_0);
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mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(5), DMA_PERI_CH_NS_19_16);
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mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(5), DMA_MANAGER_BOOT_NS);
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/* soft reset dma before use */
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mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_REQ);
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udelay(5);
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mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_RLS);
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}
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void plat_rockchip_soc_init(void)
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{
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secure_timer_init();
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sgrf_init();
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NOTICE("BL31:Rockchip release version: v%d.%d\n",
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MAJOR_VERSION, MINOR_VERSION);
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}
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+111
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOC_H
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#define SOC_H
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/******************************* stimer ***************************************/
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#define TIMER_LOADE_COUNT0 0x00
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#define TIMER_LOADE_COUNT1 0x04
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#define TIMER_CURRENT_VALUE0 0x08
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#define TIMER_CURRENT_VALUE1 0x0C
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#define TIMER_CONTROL_REG 0x10
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#define TIMER_INTSTATUS 0x18
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#define TIMER_EN 0x1
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/**************************** read/write **************************************/
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#ifndef BITS_WMSK
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#define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT))
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#endif
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/**************************** cru *********************************************/
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enum plls_id {
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APLL_ID = 0,
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DPLL_ID,
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CPLL_ID,
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GPLL_ID,
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REVERVE,
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NPLL_ID,
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MAX_PLL,
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};
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#define CRU_CRU_MODE 0x0080
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#define CRU_CRU_MISC 0x0084
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#define CRU_GLB_SRST_FST 0x009c
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#define CRU_GLB_SRST_FST_VALUE 0xfdb9
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#define PLL_CONS(id, i) (0x020 * (id) + ((i) * 4))
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#define CRU_CLKSEL_CON(i) (0x100 + ((i) * 4))
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#define CRU_CLKSEL_NUMS 53
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#define CRU_CLKGATE_CON(i) (0x200 + ((i) * 4))
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#define CRU_CLKGATE_NUMS 29
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#define CRU_SOFTRSTS_CON(n) (0x300 + ((n) * 4))
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#define CRU_SOFTRSTS_NUMS 12
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#define CRU_PLL_CON_NUMS 5
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/* PLLn_CON1 */
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#define PLL_IS_LOCKED BIT(10)
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/* PLLn_CON0 */
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#define PLL_BYPASS BITS_WITH_WMASK(1, 0x1, 15)
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#define PLL_NO_BYPASS BITS_WITH_WMASK(0, 0x1, 15)
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/* CRU_MODE */
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#define PLL_SLOW_MODE(id) ((id) == NPLL_ID) ? \
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BITS_WITH_WMASK(0, 0x1, 1) : \
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BITS_WITH_WMASK(0, 0x1, ((id) * 4))
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#define PLL_NORM_MODE(id) ((id) == NPLL_ID) ? \
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BITS_WITH_WMASK(1, 0x1, 1) : \
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BITS_WITH_WMASK(1, 0x1, ((id) * 4))
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#define CRU_GATEID_CONS(ID) (0x200 + (ID / 16) * 4)
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#define CRU_CONS_GATEID(i) (16 * (i))
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#define GATE_ID(reg, bit) ((reg * 16) + bit)
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#define PLL_LOCKED_TIMEOUT 600000U
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#define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
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/************************** config regs ***************************************/
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#define FIREWALL_CFG_FW_SYS_CON(n) (0x000 + (n) * 4)
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#define FIREWALL_DDR_FW_DDR_RGN(n) (0x000 + (n) * 4)
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#define FIREWALL_DDR_FW_DDR_MST(n) (0x020 + (n) * 4)
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#define FIREWALL_DDR_FW_DDR_CON_REG (0x040)
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#define GRF_SOC_CON(n) (0x400 + (n) * 4)
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#define GRF_SOC_STATUS(n) (0x480 + (n) * 4)
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#define GRF_CPU_STATUS(n) (0x520 + (n) * 4)
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#define GRF_OS_REG(n) (0x5c8 + (n) * 4)
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#define DDRGRF_SOC_CON(n) (0x000 + (n) * 4)
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#define DDRGRF_SOC_STATUS(n) (0x100 + (n) * 4)
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#define SGRF_SOC_CON(n) (0x000 + (n) * 4)
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#define SGRF_DMAC_CON(n) (0x100 + (n) * 4)
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#define SGRF_HDCP_KEY_CON(n) (0x280 + (n) * 4)
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#define DDR_PCTL2_PWRCTL 0x30
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/************************** regs func *****************************************/
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#define STIMER_S BIT(23)
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#define SGRF_SLV_S_ALL_NS 0x0
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#define SGRF_MST_S_ALL_NS 0xffffffff
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#define DMA_IRQ_BOOT_NS 0xffffffff
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#define DMA_MANAGER_BOOT_NS 0x80008000
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#define DMA_PERI_CH_NS_15_0 0xffffffff
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#define DMA_PERI_CH_NS_19_16 0x000f000f
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#define DMA_SOFTRST_REQ 0x01000100
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#define DMA_SOFTRST_RLS 0x01000000
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#define SELFREF_EN BIT(0)
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/************************** cpu ***********************************************/
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#define CPU_BOOT_ADDR_WMASK 0xffff0000
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#define CPU_BOOT_ADDR_ALIGN 16
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/************************** ddr secure region *********************************/
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#define PLAT_MAX_DDR_CAPACITY_MB 4096
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#define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base))
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/************************** gpio2_d2 ******************************************/
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#define SWPORTA_DR 0x00
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#define SWPORTA_DDR 0x04
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#define GPIO2_D2 BIT(26)
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#define GPIO2_D2_GPIO_MODE 0x30
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#define GRF_GPIO2D_IOMUX 0x34
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#endif /* SOC_H */
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