GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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.macro func_rockchip_clst_warmboot
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/* Nothing to do for rk3368 */
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.endm
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.macro rockchip_clst_warmboot_data
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/* Nothing to do for rk3368 */
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.endm
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+373
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#include <ddr_rk3368.h>
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#include <plat_private.h>
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#include <pmu.h>
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#include <pmu_com.h>
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#include <rk3368_def.h>
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#include <soc.h>
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DEFINE_BAKERY_LOCK(rockchip_pd_lock);
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static uint32_t cpu_warm_boot_addr;
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void rk3368_flash_l2_b(void)
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{
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uint32_t wait_cnt = 0;
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regs_updata_bit_set(PMU_BASE + PMU_SFT_CON, pmu_sft_l2flsh_clst_b);
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dsb();
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while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)
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& BIT(clst_b_l2_flsh_done))) {
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wait_cnt++;
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if (!(wait_cnt % MAX_WAIT_CONUT))
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WARN("%s:reg %x,wait\n", __func__,
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mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST));
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}
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regs_updata_bit_clr(PMU_BASE + PMU_SFT_CON, pmu_sft_l2flsh_clst_b);
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}
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static inline int rk3368_pmu_bus_idle(uint32_t req, uint32_t idle)
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{
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uint32_t mask = BIT(req);
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uint32_t idle_mask = 0;
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uint32_t idle_target = 0;
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uint32_t val;
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uint32_t wait_cnt = 0;
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switch (req) {
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case bus_ide_req_clst_l:
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idle_mask = BIT(pmu_idle_ack_cluster_l);
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idle_target = (idle << pmu_idle_ack_cluster_l);
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break;
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case bus_ide_req_clst_b:
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idle_mask = BIT(pmu_idle_ack_cluster_b);
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idle_target = (idle << pmu_idle_ack_cluster_b);
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break;
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case bus_ide_req_cxcs:
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idle_mask = BIT(pmu_idle_ack_cxcs);
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idle_target = ((!idle) << pmu_idle_ack_cxcs);
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break;
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case bus_ide_req_cci400:
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idle_mask = BIT(pmu_idle_ack_cci400);
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idle_target = ((!idle) << pmu_idle_ack_cci400);
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break;
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case bus_ide_req_gpu:
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idle_mask = BIT(pmu_idle_ack_gpu) | BIT(pmu_idle_gpu);
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idle_target = (idle << pmu_idle_ack_gpu) |
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(idle << pmu_idle_gpu);
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break;
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case bus_ide_req_core:
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idle_mask = BIT(pmu_idle_ack_core) | BIT(pmu_idle_core);
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idle_target = (idle << pmu_idle_ack_core) |
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(idle << pmu_idle_core);
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break;
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case bus_ide_req_bus:
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idle_mask = BIT(pmu_idle_ack_bus) | BIT(pmu_idle_bus);
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idle_target = (idle << pmu_idle_ack_bus) |
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(idle << pmu_idle_bus);
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break;
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case bus_ide_req_dma:
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idle_mask = BIT(pmu_idle_ack_dma) | BIT(pmu_idle_dma);
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idle_target = (idle << pmu_idle_ack_dma) |
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(idle << pmu_idle_dma);
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break;
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case bus_ide_req_peri:
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idle_mask = BIT(pmu_idle_ack_peri) | BIT(pmu_idle_peri);
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idle_target = (idle << pmu_idle_ack_peri) |
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(idle << pmu_idle_peri);
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break;
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case bus_ide_req_video:
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idle_mask = BIT(pmu_idle_ack_video) | BIT(pmu_idle_video);
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idle_target = (idle << pmu_idle_ack_video) |
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(idle << pmu_idle_video);
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break;
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case bus_ide_req_vio:
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idle_mask = BIT(pmu_idle_ack_vio) | BIT(pmu_idle_vio);
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idle_target = (pmu_idle_ack_vio) |
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(idle << pmu_idle_vio);
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break;
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case bus_ide_req_alive:
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idle_mask = BIT(pmu_idle_ack_alive) | BIT(pmu_idle_alive);
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idle_target = (idle << pmu_idle_ack_alive) |
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(idle << pmu_idle_alive);
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break;
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case bus_ide_req_pmu:
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idle_mask = BIT(pmu_idle_ack_pmu) | BIT(pmu_idle_pmu);
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idle_target = (idle << pmu_idle_ack_pmu) |
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(idle << pmu_idle_pmu);
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break;
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case bus_ide_req_msch:
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idle_mask = BIT(pmu_idle_ack_msch) | BIT(pmu_idle_msch);
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idle_target = (idle << pmu_idle_ack_msch) |
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(idle << pmu_idle_msch);
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break;
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case bus_ide_req_cci:
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idle_mask = BIT(pmu_idle_ack_cci) | BIT(pmu_idle_cci);
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idle_target = (idle << pmu_idle_ack_cci) |
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(idle << pmu_idle_cci);
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break;
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default:
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ERROR("%s: Unsupported the idle request\n", __func__);
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break;
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}
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val = mmio_read_32(PMU_BASE + PMU_BUS_IDE_REQ);
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if (idle)
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val |= mask;
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else
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val &= ~mask;
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mmio_write_32(PMU_BASE + PMU_BUS_IDE_REQ, val);
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while ((mmio_read_32(PMU_BASE +
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PMU_BUS_IDE_ST) & idle_mask) != idle_target) {
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wait_cnt++;
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if (!(wait_cnt % MAX_WAIT_CONUT))
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WARN("%s:st=%x(%x)\n", __func__,
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mmio_read_32(PMU_BASE + PMU_BUS_IDE_ST),
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idle_mask);
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}
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return 0;
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}
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void pmu_scu_b_pwrup(void)
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{
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regs_updata_bit_clr(PMU_BASE + PMU_SFT_CON, pmu_sft_acinactm_clst_b);
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rk3368_pmu_bus_idle(bus_ide_req_clst_b, 0);
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}
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static void pmu_scu_b_pwrdn(void)
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{
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uint32_t wait_cnt = 0;
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if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) &
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PM_PWRDM_CPUSB_MSK) != PM_PWRDM_CPUSB_MSK) {
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ERROR("%s: not all cpus is off\n", __func__);
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return;
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}
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rk3368_flash_l2_b();
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regs_updata_bit_set(PMU_BASE + PMU_SFT_CON, pmu_sft_acinactm_clst_b);
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while (!(mmio_read_32(PMU_BASE +
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PMU_CORE_PWR_ST) & BIT(clst_b_l2_wfi))) {
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wait_cnt++;
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if (!(wait_cnt % MAX_WAIT_CONUT))
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ERROR("%s:wait cluster-b l2(%x)\n", __func__,
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mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST));
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}
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rk3368_pmu_bus_idle(bus_ide_req_clst_b, 1);
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}
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static void pmu_sleep_mode_config(void)
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{
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uint32_t pwrmd_core, pwrmd_com;
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pwrmd_core = BIT(pmu_mdcr_cpu0_pd) |
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BIT(pmu_mdcr_scu_l_pd) |
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BIT(pmu_mdcr_l2_flush) |
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BIT(pmu_mdcr_l2_idle) |
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BIT(pmu_mdcr_clr_clst_l) |
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BIT(pmu_mdcr_clr_core) |
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BIT(pmu_mdcr_clr_cci) |
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BIT(pmu_mdcr_core_pd);
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pwrmd_com = BIT(pmu_mode_en) |
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BIT(pmu_mode_sref_enter) |
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BIT(pmu_mode_pwr_off);
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regs_updata_bit_set(PMU_BASE + PMU_WKUP_CFG2, pmu_cluster_l_wkup_en);
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regs_updata_bit_set(PMU_BASE + PMU_WKUP_CFG2, pmu_cluster_b_wkup_en);
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regs_updata_bit_clr(PMU_BASE + PMU_WKUP_CFG2, pmu_gpio_wkup_en);
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mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_24M_CNT_MS(2));
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mmio_write_32(PMU_BASE + PMU_PLLRST_CNT, CYCL_24M_CNT_US(100));
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mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_24M_CNT_MS(2));
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mmio_write_32(PMU_BASE + PMU_PWRMD_CORE, pwrmd_core);
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mmio_write_32(PMU_BASE + PMU_PWRMD_COM, pwrmd_com);
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dsb();
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}
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static void pmu_set_sleep_mode(void)
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{
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pmu_sleep_mode_config();
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soc_sleep_config();
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regs_updata_bit_set(PMU_BASE + PMU_PWRMD_CORE, pmu_mdcr_global_int_dis);
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regs_updata_bit_set(PMU_BASE + PMU_SFT_CON, pmu_sft_glbl_int_dis_b);
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pmu_scu_b_pwrdn();
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
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((uintptr_t)&pmu_cpuson_entrypoint >>
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CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK);
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2),
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((uintptr_t)&pmu_cpuson_entrypoint >>
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CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK);
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}
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static int cpus_id_power_domain(uint32_t cluster,
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uint32_t cpu,
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uint32_t pd_state,
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uint32_t wfie_msk)
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{
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uint32_t pd;
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uint64_t mpidr;
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if (cluster)
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pd = PD_CPUB0 + cpu;
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else
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pd = PD_CPUL0 + cpu;
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if (pmu_power_domain_st(pd) == pd_state)
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return 0;
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if (pd_state == pmu_pd_off) {
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mpidr = (cluster << MPIDR_AFF1_SHIFT) | cpu;
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if (check_cpu_wfie(mpidr, wfie_msk))
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return -EINVAL;
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}
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return pmu_power_domain_ctr(pd, pd_state);
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}
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static void nonboot_cpus_off(void)
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{
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uint32_t boot_cpu, boot_cluster, cpu;
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boot_cpu = MPIDR_AFFLVL0_VAL(read_mpidr_el1());
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boot_cluster = MPIDR_AFFLVL1_VAL(read_mpidr_el1());
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/* turn off noboot cpus */
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for (cpu = 0; cpu < PLATFORM_CLUSTER0_CORE_COUNT; cpu++) {
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if (!boot_cluster && (cpu == boot_cpu))
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continue;
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cpus_id_power_domain(0, cpu, pmu_pd_off, CKECK_WFEI_MSK);
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}
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for (cpu = 0; cpu < PLATFORM_CLUSTER1_CORE_COUNT; cpu++) {
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if (boot_cluster && (cpu == boot_cpu))
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continue;
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cpus_id_power_domain(1, cpu, pmu_pd_off, CKECK_WFEI_MSK);
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}
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}
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void sram_save(void)
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{
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/* TODO: support the sdram save for rk3368 SoCs*/
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}
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void sram_restore(void)
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{
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/* TODO: support the sdram restore for rk3368 SoCs */
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}
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int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint)
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{
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uint32_t cpu, cluster;
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uint32_t cpuon_id;
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cpu = MPIDR_AFFLVL0_VAL(mpidr);
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cluster = MPIDR_AFFLVL1_VAL(mpidr);
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/* Make sure the cpu is off,Before power up the cpu! */
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cpus_id_power_domain(cluster, cpu, pmu_pd_off, CKECK_WFEI_MSK);
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cpuon_id = (cluster * PLATFORM_CLUSTER0_CORE_COUNT) + cpu;
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assert(cpuon_id < PLATFORM_CORE_COUNT);
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assert(cpuson_flags[cpuon_id] == 0);
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cpuson_flags[cpuon_id] = PMU_CPU_HOTPLUG;
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cpuson_entry_point[cpuon_id] = entrypoint;
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/* Switch boot addr to pmusram */
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1 + cluster),
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(cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) |
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CPU_BOOT_ADDR_WMASK);
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dsb();
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cpus_id_power_domain(cluster, cpu, pmu_pd_on, CKECK_WFEI_MSK);
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1 + cluster),
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(COLD_BOOT_BASE >> CPU_BOOT_ADDR_ALIGN) |
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CPU_BOOT_ADDR_WMASK);
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return 0;
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}
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int rockchip_soc_cores_pwr_dm_on_finish(void)
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{
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return 0;
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}
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int rockchip_soc_sys_pwr_dm_resume(void)
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{
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
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(COLD_BOOT_BASE >> CPU_BOOT_ADDR_ALIGN) |
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CPU_BOOT_ADDR_WMASK);
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2),
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(COLD_BOOT_BASE >> CPU_BOOT_ADDR_ALIGN) |
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CPU_BOOT_ADDR_WMASK);
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pm_plls_resume();
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pmu_scu_b_pwrup();
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return 0;
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}
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int rockchip_soc_sys_pwr_dm_suspend(void)
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{
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nonboot_cpus_off();
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pmu_set_sleep_mode();
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return 0;
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}
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void rockchip_plat_mmu_el3(void)
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{
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/* TODO: support the el3 for rk3368 SoCs */
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}
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void plat_rockchip_pmu_init(void)
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{
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uint32_t cpu;
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/* register requires 32bits mode, switch it to 32 bits */
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cpu_warm_boot_addr = (uint64_t)platform_cpu_warmboot;
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for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++)
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cpuson_flags[cpu] = 0;
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nonboot_cpus_off();
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INFO("%s(%d): pd status %x\n", __func__, __LINE__,
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mmio_read_32(PMU_BASE + PMU_PWRDN_ST));
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}
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+207
@@ -0,0 +1,207 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
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#ifndef PMU_H
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#define PMU_H
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/* Allocate sp reginon in pmusram */
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#define PSRAM_SP_SIZE 0x80
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#define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE)
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/*****************************************************************************
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* pmu con,reg
|
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*****************************************************************************/
|
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#define PMU_WKUP_CFG0 0x0
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#define PMU_WKUP_CFG1 0x4
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#define PMU_WKUP_CFG2 0x8
|
||||
#define PMU_TIMEOUT_CNT 0x7c
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#define PMU_PWRDN_CON 0xc
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#define PMU_PWRDN_ST 0x10
|
||||
#define PMU_CORE_PWR_ST 0x38
|
||||
|
||||
#define PMU_PWRMD_CORE 0x14
|
||||
#define PMU_PWRMD_COM 0x18
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||||
#define PMU_SFT_CON 0x1c
|
||||
#define PMU_BUS_IDE_REQ 0x3c
|
||||
#define PMU_BUS_IDE_ST 0x40
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||||
#define PMU_OSC_CNT 0x48
|
||||
#define PMU_PLLLOCK_CNT 0x4c
|
||||
#define PMU_PLLRST_CNT 0x50
|
||||
#define PMU_STABLE_CNT 0x54
|
||||
#define PMU_DDRIO_PWR_CNT 0x58
|
||||
#define PMU_WKUPRST_CNT 0x5c
|
||||
|
||||
enum pmu_powermode_core {
|
||||
pmu_mdcr_global_int_dis = 0,
|
||||
pmu_mdcr_core_src_gt,
|
||||
pmu_mdcr_clr_cci,
|
||||
pmu_mdcr_cpu0_pd,
|
||||
pmu_mdcr_clr_clst_l = 4,
|
||||
pmu_mdcr_clr_core,
|
||||
pmu_mdcr_scu_l_pd,
|
||||
pmu_mdcr_core_pd,
|
||||
pmu_mdcr_l2_idle = 8,
|
||||
pmu_mdcr_l2_flush
|
||||
};
|
||||
|
||||
/*
|
||||
* the shift of bits for cores status
|
||||
*/
|
||||
enum pmu_core_pwrst_shift {
|
||||
clstl_cpu_wfe = 2,
|
||||
clstl_cpu_wfi = 6,
|
||||
clstb_cpu_wfe = 12,
|
||||
clstb_cpu_wfi = 16
|
||||
};
|
||||
|
||||
enum pmu_pdid {
|
||||
PD_CPUL0 = 0,
|
||||
PD_CPUL1,
|
||||
PD_CPUL2,
|
||||
PD_CPUL3,
|
||||
PD_SCUL,
|
||||
PD_CPUB0 = 5,
|
||||
PD_CPUB1,
|
||||
PD_CPUB2,
|
||||
PD_CPUB3,
|
||||
PD_SCUB = 9,
|
||||
PD_PERI = 13,
|
||||
PD_VIDEO,
|
||||
PD_VIO,
|
||||
PD_GPU0,
|
||||
PD_GPU1,
|
||||
PD_END
|
||||
};
|
||||
|
||||
enum pmu_bus_ide {
|
||||
bus_ide_req_clst_l = 0,
|
||||
bus_ide_req_clst_b,
|
||||
bus_ide_req_gpu,
|
||||
bus_ide_req_core,
|
||||
bus_ide_req_bus = 4,
|
||||
bus_ide_req_dma,
|
||||
bus_ide_req_peri,
|
||||
bus_ide_req_video,
|
||||
bus_ide_req_vio = 8,
|
||||
bus_ide_req_res0,
|
||||
bus_ide_req_cxcs,
|
||||
bus_ide_req_alive,
|
||||
bus_ide_req_pmu = 12,
|
||||
bus_ide_req_msch,
|
||||
bus_ide_req_cci,
|
||||
bus_ide_req_cci400 = 15,
|
||||
bus_ide_req_end
|
||||
};
|
||||
|
||||
enum pmu_powermode_common {
|
||||
pmu_mode_en = 0,
|
||||
pmu_mode_res0,
|
||||
pmu_mode_bus_pd,
|
||||
pmu_mode_wkup_rst,
|
||||
pmu_mode_pll_pd = 4,
|
||||
pmu_mode_pwr_off,
|
||||
pmu_mode_pmu_use_if,
|
||||
pmu_mode_pmu_alive_use_if,
|
||||
pmu_mode_osc_dis = 8,
|
||||
pmu_mode_input_clamp,
|
||||
pmu_mode_sref_enter,
|
||||
pmu_mode_ddrc_gt,
|
||||
pmu_mode_ddrio_ret = 12,
|
||||
pmu_mode_ddrio_ret_deq,
|
||||
pmu_mode_clr_pmu,
|
||||
pmu_mode_clr_alive,
|
||||
pmu_mode_clr_bus = 16,
|
||||
pmu_mode_clr_dma,
|
||||
pmu_mode_clr_msch,
|
||||
pmu_mode_clr_peri,
|
||||
pmu_mode_clr_video = 20,
|
||||
pmu_mode_clr_vio,
|
||||
pmu_mode_clr_gpu,
|
||||
pmu_mode_clr_mcu,
|
||||
pmu_mode_clr_cxcs = 24,
|
||||
pmu_mode_clr_cci400,
|
||||
pmu_mode_res1,
|
||||
pmu_mode_res2,
|
||||
pmu_mode_res3 = 28,
|
||||
pmu_mode_mclst
|
||||
};
|
||||
|
||||
enum pmu_core_power_st {
|
||||
clst_l_cpu_wfe = 2,
|
||||
clst_l_cpu_wfi = 6,
|
||||
clst_b_l2_flsh_done = 10,
|
||||
clst_b_l2_wfi = 11,
|
||||
clst_b_cpu_wfe = 12,
|
||||
clst_b_cpu_wfi = 16,
|
||||
mcu_sleeping = 20,
|
||||
};
|
||||
|
||||
enum pmu_sft_con {
|
||||
pmu_sft_acinactm_clst_b = 5,
|
||||
pmu_sft_l2flsh_clst_b,
|
||||
pmu_sft_glbl_int_dis_b = 9,
|
||||
pmu_sft_ddrio_ret_cfg = 11,
|
||||
};
|
||||
|
||||
enum pmu_wkup_cfg2 {
|
||||
pmu_cluster_l_wkup_en = 0,
|
||||
pmu_cluster_b_wkup_en,
|
||||
pmu_gpio_wkup_en,
|
||||
pmu_sdio_wkup_en,
|
||||
pmu_sdmmc_wkup_en,
|
||||
pmu_sim_wkup_en,
|
||||
pmu_timer_wkup_en,
|
||||
pmu_usbdev_wkup_en,
|
||||
pmu_sft_wkup_en,
|
||||
pmu_wdt_mcu_wkup_en,
|
||||
pmu_timeout_wkup_en,
|
||||
};
|
||||
|
||||
enum pmu_bus_idle_st {
|
||||
pmu_idle_ack_cluster_l = 0,
|
||||
pmu_idle_ack_cluster_b,
|
||||
pmu_idle_ack_gpu,
|
||||
pmu_idle_ack_core,
|
||||
pmu_idle_ack_bus,
|
||||
pmu_idle_ack_dma,
|
||||
pmu_idle_ack_peri,
|
||||
pmu_idle_ack_video,
|
||||
pmu_idle_ack_vio,
|
||||
pmu_idle_ack_cci = 10,
|
||||
pmu_idle_ack_msch,
|
||||
pmu_idle_ack_alive,
|
||||
pmu_idle_ack_pmu,
|
||||
pmu_idle_ack_cxcs,
|
||||
pmu_idle_ack_cci400,
|
||||
pmu_inactive_cluster_l,
|
||||
pmu_inactive_cluster_b,
|
||||
pmu_idle_gpu,
|
||||
pmu_idle_core,
|
||||
pmu_idle_bus,
|
||||
pmu_idle_dma,
|
||||
pmu_idle_peri,
|
||||
pmu_idle_video,
|
||||
pmu_idle_vio,
|
||||
pmu_idle_cci = 26,
|
||||
pmu_idle_msch,
|
||||
pmu_idle_alive,
|
||||
pmu_idle_pmu,
|
||||
pmu_active_cxcs,
|
||||
pmu_active_cci,
|
||||
};
|
||||
|
||||
#define PM_PWRDM_CPUSB_MSK (0xf << 5)
|
||||
|
||||
#define CKECK_WFE_MSK 0x1
|
||||
#define CKECK_WFI_MSK 0x10
|
||||
#define CKECK_WFEI_MSK 0x11
|
||||
|
||||
#define PD_CTR_LOOP 500
|
||||
#define CHK_CPU_LOOP 500
|
||||
|
||||
#define MAX_WAIT_CONUT 1000
|
||||
|
||||
#endif /* PMU_H */
|
||||
Reference in New Issue
Block a user