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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
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source/trusted-firmware/trusted-firmware-a-2.8/plat/rockchip/rk3399/drivers/dram/dfs.c
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source/trusted-firmware/trusted-firmware-a-2.8/plat/rockchip/rk3399/drivers/dram/dfs.h
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/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef DFS_H
#define DFS_H
#include <stdint.h>
struct rk3399_sdram_default_config {
unsigned char bl;
/* 1:auto precharge, 0:never auto precharge */
unsigned char ap;
/* dram driver strength */
unsigned char dramds;
/* dram ODT, if odt=0, this parameter invalid */
unsigned char dramodt;
/* ca ODT, if odt=0, this parameter invalid
* only used by LPDDR4
*/
unsigned char caodt;
unsigned char burst_ref_cnt;
/* zqcs period, unit(s) */
unsigned char zqcsi;
};
struct drv_odt_lp_config {
uint32_t pd_idle;
uint32_t sr_idle;
uint32_t sr_mc_gate_idle;
uint32_t srpd_lite_idle;
uint32_t standby_idle;
uint32_t odt_en;
uint32_t dram_side_drv;
uint32_t dram_side_dq_odt;
uint32_t dram_side_ca_odt;
};
uint32_t ddr_set_rate(uint32_t hz);
uint32_t ddr_round_rate(uint32_t hz);
uint32_t ddr_get_rate(void);
uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2);
void dram_dfs_init(void);
void ddr_prepare_for_sys_suspend(void);
void ddr_prepare_for_sys_resume(void);
#endif /* DFS_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/rockchip/rk3399/drivers/dram/dram.c
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/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <dram.h>
#include <plat_private.h>
#include <rk3399_def.h>
#include <secure.h>
#include <soc.h>
__pmusramdata struct rk3399_sdram_params sdram_config;
void dram_init(void)
{
uint32_t os_reg2_val, i;
os_reg2_val = mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2));
sdram_config.dramtype = SYS_REG_DEC_DDRTYPE(os_reg2_val);
sdram_config.num_channels = SYS_REG_DEC_NUM_CH(os_reg2_val);
sdram_config.stride = (mmio_read_32(SGRF_BASE + SGRF_SOC_CON3_7(4)) >>
10) & 0x1f;
for (i = 0; i < 2; i++) {
struct rk3399_sdram_channel *ch = &sdram_config.ch[i];
struct rk3399_msch_timings *noc = &ch->noc_timings;
if (!(SYS_REG_DEC_CHINFO(os_reg2_val, i)))
continue;
ch->rank = SYS_REG_DEC_RANK(os_reg2_val, i);
ch->col = SYS_REG_DEC_COL(os_reg2_val, i);
ch->bk = SYS_REG_DEC_BK(os_reg2_val, i);
ch->bw = SYS_REG_DEC_BW(os_reg2_val, i);
ch->dbw = SYS_REG_DEC_DBW(os_reg2_val, i);
ch->row_3_4 = SYS_REG_DEC_ROW_3_4(os_reg2_val, i);
ch->cs0_row = SYS_REG_DEC_CS0_ROW(os_reg2_val, i);
ch->cs1_row = SYS_REG_DEC_CS1_ROW(os_reg2_val, i);
ch->ddrconfig = mmio_read_32(MSCH_BASE(i) + MSCH_DEVICECONF);
noc->ddrtiminga0.d32 = mmio_read_32(MSCH_BASE(i) +
MSCH_DDRTIMINGA0);
noc->ddrtimingb0.d32 = mmio_read_32(MSCH_BASE(i) +
MSCH_DDRTIMINGB0);
noc->ddrtimingc0.d32 = mmio_read_32(MSCH_BASE(i) +
MSCH_DDRTIMINGC0);
noc->devtodev0.d32 = mmio_read_32(MSCH_BASE(i) +
MSCH_DEVTODEV0);
noc->ddrmode.d32 = mmio_read_32(MSCH_BASE(i) + MSCH_DDRMODE);
noc->agingx0 = mmio_read_32(MSCH_BASE(i) + MSCH_AGINGX0);
}
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/rockchip/rk3399/drivers/dram/dram.h
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/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef DRAM_H
#define DRAM_H
#include <stdint.h>
#include <dram_regs.h>
#include <plat_private.h>
enum {
DDR3 = 3,
LPDDR2 = 5,
LPDDR3 = 6,
LPDDR4 = 7,
UNUSED = 0xff
};
struct rk3399_ddr_pctl_regs {
uint32_t denali_ctl[CTL_REG_NUM];
};
struct rk3399_ddr_publ_regs {
/*
* PHY registers from 0 to 90 for slice1.
* These are used to restore slice1-4 on resume.
*/
uint32_t phy0[91];
/*
* PHY registers from 512 to 895.
* Only registers 0-37 of each 128 register range are used.
*/
uint32_t phy512[3][38];
uint32_t phy896[63];
};
struct rk3399_ddr_pi_regs {
uint32_t denali_pi[PI_REG_NUM];
};
union noc_ddrtiminga0 {
uint32_t d32;
struct {
unsigned acttoact : 6;
unsigned reserved0 : 2;
unsigned rdtomiss : 6;
unsigned reserved1 : 2;
unsigned wrtomiss : 6;
unsigned reserved2 : 2;
unsigned readlatency : 8;
} b;
};
union noc_ddrtimingb0 {
uint32_t d32;
struct {
unsigned rdtowr : 5;
unsigned reserved0 : 3;
unsigned wrtord : 5;
unsigned reserved1 : 3;
unsigned rrd : 4;
unsigned reserved2 : 4;
unsigned faw : 6;
unsigned reserved3 : 2;
} b;
};
union noc_ddrtimingc0 {
uint32_t d32;
struct {
unsigned burstpenalty : 4;
unsigned reserved0 : 4;
unsigned wrtomwr : 6;
unsigned reserved1 : 18;
} b;
};
union noc_devtodev0 {
uint32_t d32;
struct {
unsigned busrdtord : 3;
unsigned reserved0 : 1;
unsigned busrdtowr : 3;
unsigned reserved1 : 1;
unsigned buswrtord : 3;
unsigned reserved2 : 1;
unsigned buswrtowr : 3;
unsigned reserved3 : 17;
} b;
};
union noc_ddrmode {
uint32_t d32;
struct {
unsigned autoprecharge : 1;
unsigned bypassfiltering : 1;
unsigned fawbank : 1;
unsigned burstsize : 2;
unsigned mwrsize : 2;
unsigned reserved2 : 1;
unsigned forceorder : 8;
unsigned forceorderstate : 8;
unsigned reserved3 : 8;
} b;
};
struct rk3399_msch_timings {
union noc_ddrtiminga0 ddrtiminga0;
union noc_ddrtimingb0 ddrtimingb0;
union noc_ddrtimingc0 ddrtimingc0;
union noc_devtodev0 devtodev0;
union noc_ddrmode ddrmode;
uint32_t agingx0;
};
struct rk3399_sdram_channel {
unsigned char rank;
/* col = 0, means this channel is invalid */
unsigned char col;
/* 3:8bank, 2:4bank */
unsigned char bk;
/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
unsigned char bw;
/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
unsigned char dbw;
/* row_3_4 = 1: 6Gb or 12Gb die
* row_3_4 = 0: normal die, power of 2
*/
unsigned char row_3_4;
unsigned char cs0_row;
unsigned char cs1_row;
uint32_t ddrconfig;
struct rk3399_msch_timings noc_timings;
};
struct rk3399_sdram_params {
struct rk3399_sdram_channel ch[2];
uint32_t ddr_freq;
unsigned char dramtype;
unsigned char num_channels;
unsigned char stride;
unsigned char odt;
struct rk3399_ddr_pctl_regs pctl_regs;
struct rk3399_ddr_pi_regs pi_regs;
struct rk3399_ddr_publ_regs phy_regs;
uint32_t rx_cal_dqs[2][4];
};
extern struct rk3399_sdram_params sdram_config;
void dram_init(void);
#endif /* DRAM_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
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source/trusted-firmware/trusted-firmware-a-2.8/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h
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/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef DRAM_SPEC_TIMING_H
#define DRAM_SPEC_TIMING_H
#include <stdint.h>
enum ddr3_speed_rate {
/* 5-5-5 */
DDR3_800D = 0,
/* 6-6-6 */
DDR3_800E = 1,
/* 6-6-6 */
DDR3_1066E = 2,
/* 7-7-7 */
DDR3_1066F = 3,
/* 8-8-8 */
DDR3_1066G = 4,
/* 7-7-7 */
DDR3_1333F = 5,
/* 8-8-8 */
DDR3_1333G = 6,
/* 9-9-9 */
DDR3_1333H = 7,
/* 10-10-10 */
DDR3_1333J = 8,
/* 8-8-8 */
DDR3_1600G = 9,
/* 9-9-9 */
DDR3_1600H = 10,
/* 10-10-10 */
DDR3_1600J = 11,
/* 11-11-11 */
DDR3_1600K = 12,
/* 10-10-10 */
DDR3_1866J = 13,
/* 11-11-11 */
DDR3_1866K = 14,
/* 12-12-12 */
DDR3_1866L = 15,
/* 13-13-13 */
DDR3_1866M = 16,
/* 11-11-11 */
DDR3_2133K = 17,
/* 12-12-12 */
DDR3_2133L = 18,
/* 13-13-13 */
DDR3_2133M = 19,
/* 14-14-14 */
DDR3_2133N = 20,
DDR3_DEFAULT = 21,
};
#define max(a, b) (((a) > (b)) ? (a) : (b))
#define range(mi, val, ma) (((ma) > (val)) ? (max(mi, val)) : (ma))
struct dram_timing_t {
/* unit MHz */
uint32_t mhz;
/* some timing unit is us */
uint32_t tinit1;
uint32_t tinit2;
uint32_t tinit3;
uint32_t tinit4;
uint32_t tinit5;
/* reset low, DDR3:200us */
uint32_t trstl;
/* reset high to CKE high, DDR3:500us */
uint32_t trsth;
uint32_t trefi;
/* base */
uint32_t trcd;
/* trp per bank */
uint32_t trppb;
/* trp all bank */
uint32_t trp;
uint32_t twr;
uint32_t tdal;
uint32_t trtp;
uint32_t trc;
uint32_t trrd;
uint32_t tccd;
uint32_t twtr;
uint32_t trtw;
uint32_t tras_max;
uint32_t tras_min;
uint32_t tfaw;
uint32_t trfc;
uint32_t tdqsck;
uint32_t tdqsck_max;
/* pd or sr */
uint32_t txsr;
uint32_t txsnr;
uint32_t txp;
uint32_t txpdll;
uint32_t tdllk;
uint32_t tcke;
uint32_t tckesr;
uint32_t tcksre;
uint32_t tcksrx;
uint32_t tdpd;
/* mode regiter timing */
uint32_t tmod;
uint32_t tmrd;
uint32_t tmrr;
uint32_t tmrri;
/* ODT */
uint32_t todton;
/* ZQ */
uint32_t tzqinit;
uint32_t tzqcs;
uint32_t tzqoper;
uint32_t tzqreset;
/* Write Leveling */
uint32_t twlmrd;
uint32_t twlo;
uint32_t twldqsen;
/* CA Training */
uint32_t tcackel;
uint32_t tcaent;
uint32_t tcamrd;
uint32_t tcackeh;
uint32_t tcaext;
uint32_t tadr;
uint32_t tmrz;
uint32_t tcacd;
/* mode register */
uint32_t mr[4];
uint32_t mr11;
/* lpddr4 spec */
uint32_t mr12;
uint32_t mr13;
uint32_t mr14;
uint32_t mr16;
uint32_t mr17;
uint32_t mr20;
uint32_t mr22;
uint32_t tccdmw;
uint32_t tppd;
uint32_t tescke;
uint32_t tsr;
uint32_t tcmdcke;
uint32_t tcscke;
uint32_t tckelcs;
uint32_t tcsckeh;
uint32_t tckehcs;
uint32_t tmrwckel;
uint32_t tzqcal;
uint32_t tzqlat;
uint32_t tzqcke;
uint32_t tvref_long;
uint32_t tvref_short;
uint32_t tvrcg_enable;
uint32_t tvrcg_disable;
uint32_t tfc_long;
uint32_t tckfspe;
uint32_t tckfspx;
uint32_t tckehcmd;
uint32_t tckelcmd;
uint32_t tckelpd;
uint32_t tckckel;
/* other */
uint32_t al;
uint32_t cl;
uint32_t cwl;
uint32_t bl;
};
struct dram_info_t {
/* speed_rate only used when DDR3 */
enum ddr3_speed_rate speed_rate;
/* 1: use CS0, 2: use CS0 and CS1 */
uint32_t cs_cnt;
/* give the max per-die capability on each rank/cs */
uint32_t per_die_capability[2];
};
struct timing_related_config {
struct dram_info_t dram_info[2];
uint32_t dram_type;
/* MHz */
uint32_t freq;
uint32_t ch_cnt;
uint32_t bl;
/* 1:auto precharge, 0:never auto precharge */
uint32_t ap;
/*
* 1:dll bypass, 0:dll normal
* dram and controller dll bypass at the same time
*/
uint32_t dllbp;
/* 1:odt enable, 0:odt disable */
uint32_t odt;
/* 1:enable, 0:disabe */
uint32_t rdbi;
uint32_t wdbi;
/* dram driver strength */
uint32_t dramds;
/* dram ODT, if odt=0, this parameter invalid */
uint32_t dramodt;
/*
* ca ODT, if odt=0, this parameter invalid
* it only used by LPDDR4
*/
uint32_t caodt;
};
/* mr0 for ddr3 */
#define DDR3_BL8 (0)
#define DDR3_BC4_8 (1)
#define DDR3_BC4 (2)
#define DDR3_CL(n) (((((n) - 4) & 0x7) << 4)\
| ((((n) - 4) & 0x8) >> 1))
#define DDR3_WR(n) (((n) & 0x7) << 9)
#define DDR3_DLL_RESET (1 << 8)
#define DDR3_DLL_DERESET (0 << 8)
/* mr1 for ddr3 */
#define DDR3_DLL_ENABLE (0)
#define DDR3_DLL_DISABLE (1)
#define DDR3_MR1_AL(n) (((n) & 0x3) << 3)
#define DDR3_DS_40 (0)
#define DDR3_DS_34 (1 << 1)
#define DDR3_RTT_NOM_DIS (0)
#define DDR3_RTT_NOM_60 (1 << 2)
#define DDR3_RTT_NOM_120 (1 << 6)
#define DDR3_RTT_NOM_40 ((1 << 2) | (1 << 6))
#define DDR3_TDQS (1 << 11)
/* mr2 for ddr3 */
#define DDR3_MR2_CWL(n) ((((n) - 5) & 0x7) << 3)
#define DDR3_RTT_WR_DIS (0)
#define DDR3_RTT_WR_60 (1 << 9)
#define DDR3_RTT_WR_120 (2 << 9)
/*
* MR0 (Device Information)
* 0:DAI complete, 1:DAI still in progress
*/
#define LPDDR2_DAI (0x1)
/* 0:S2 or S4 SDRAM, 1:NVM */
#define LPDDR2_DI (0x1 << 1)
/* 0:DNV not supported, 1:DNV supported */
#define LPDDR2_DNVI (0x1 << 2)
#define LPDDR2_RZQI (0x3 << 3)
/*
* 00:RZQ self test not supported,
* 01:ZQ-pin may connect to VDDCA or float
* 10:ZQ-pin may short to GND.
* 11:ZQ-pin self test completed, no error condition detected.
*/
/* MR1 (Device Feature) */
#define LPDDR2_BL4 (0x2)
#define LPDDR2_BL8 (0x3)
#define LPDDR2_BL16 (0x4)
#define LPDDR2_N_WR(n) (((n) - 2) << 5)
/* MR2 (Device Feature 2) */
#define LPDDR2_RL3_WL1 (0x1)
#define LPDDR2_RL4_WL2 (0x2)
#define LPDDR2_RL5_WL2 (0x3)
#define LPDDR2_RL6_WL3 (0x4)
#define LPDDR2_RL7_WL4 (0x5)
#define LPDDR2_RL8_WL4 (0x6)
/* MR3 (IO Configuration 1) */
#define LPDDR2_DS_34 (0x1)
#define LPDDR2_DS_40 (0x2)
#define LPDDR2_DS_48 (0x3)
#define LPDDR2_DS_60 (0x4)
#define LPDDR2_DS_80 (0x6)
/* optional */
#define LPDDR2_DS_120 (0x7)
/* MR4 (Device Temperature) */
#define LPDDR2_TREF_MASK (0x7)
#define LPDDR2_4_TREF (0x1)
#define LPDDR2_2_TREF (0x2)
#define LPDDR2_1_TREF (0x3)
#define LPDDR2_025_TREF (0x5)
#define LPDDR2_025_TREF_DERATE (0x6)
#define LPDDR2_TUF (0x1 << 7)
/* MR8 (Basic configuration 4) */
#define LPDDR2_S4 (0x0)
#define LPDDR2_S2 (0x1)
#define LPDDR2_N (0x2)
/* Unit:MB */
#define LPDDR2_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf))
#define LPDDR2_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3))
/* MR10 (Calibration) */
#define LPDDR2_ZQINIT (0xff)
#define LPDDR2_ZQCL (0xab)
#define LPDDR2_ZQCS (0x56)
#define LPDDR2_ZQRESET (0xc3)
/* MR16 (PASR Bank Mask), S2 SDRAM Only */
#define LPDDR2_PASR_FULL (0x0)
#define LPDDR2_PASR_1_2 (0x1)
#define LPDDR2_PASR_1_4 (0x2)
#define LPDDR2_PASR_1_8 (0x3)
/*
* MR0 (Device Information)
* 0:DAI complete,
* 1:DAI still in progress
*/
#define LPDDR3_DAI (0x1)
/*
* 00:RZQ self test not supported,
* 01:ZQ-pin may connect to VDDCA or float
* 10:ZQ-pin may short to GND.
* 11:ZQ-pin self test completed, no error condition detected.
*/
#define LPDDR3_RZQI (0x3 << 3)
/*
* 0:DRAM does not support WL(Set B),
* 1:DRAM support WL(Set B)
*/
#define LPDDR3_WL_SUPOT (1 << 6)
/*
* 0:DRAM does not support RL=3,nWR=3,WL=1;
* 1:DRAM supports RL=3,nWR=3,WL=1 for frequencies <=166
*/
#define LPDDR3_RL3_SUPOT (1 << 7)
/* MR1 (Device Feature) */
#define LPDDR3_BL8 (0x3)
#define LPDDR3_N_WR(n) ((n) << 5)
/* MR2 (Device Feature 2), WL Set A,default */
/* <=166MHz,optional*/
#define LPDDR3_RL3_WL1 (0x1)
/* <=400MHz*/
#define LPDDR3_RL6_WL3 (0x4)
/* <=533MHz*/
#define LPDDR3_RL8_WL4 (0x6)
/* <=600MHz*/
#define LPDDR3_RL9_WL5 (0x7)
/* <=667MHz,default*/
#define LPDDR3_RL10_WL6 (0x8)
/* <=733MHz*/
#define LPDDR3_RL11_WL6 (0x9)
/* <=800MHz*/
#define LPDDR3_RL12_WL6 (0xa)
/* <=933MHz*/
#define LPDDR3_RL14_WL8 (0xc)
/* <=1066MHz*/
#define LPDDR3_RL16_WL8 (0xe)
/* WL Set B, optional */
/* <=667MHz,default*/
#define LPDDR3_RL10_WL8 (0x8)
/* <=733MHz*/
#define LPDDR3_RL11_WL9 (0x9)
/* <=800MHz*/
#define LPDDR3_RL12_WL9 (0xa)
/* <=933MHz*/
#define LPDDR3_RL14_WL11 (0xc)
/* <=1066MHz*/
#define LPDDR3_RL16_WL13 (0xe)
/* 1:enable nWR programming > 9(default)*/
#define LPDDR3_N_WRE (1 << 4)
/* 1:Select WL Set B*/
#define LPDDR3_WL_S (1 << 6)
/* 1:enable*/
#define LPDDR3_WR_LEVEL (1 << 7)
/* MR3 (IO Configuration 1) */
#define LPDDR3_DS_34 (0x1)
#define LPDDR3_DS_40 (0x2)
#define LPDDR3_DS_48 (0x3)
#define LPDDR3_DS_60 (0x4)
#define LPDDR3_DS_80 (0x6)
#define LPDDR3_DS_34D_40U (0x9)
#define LPDDR3_DS_40D_48U (0xa)
#define LPDDR3_DS_34D_48U (0xb)
/* MR4 (Device Temperature) */
#define LPDDR3_TREF_MASK (0x7)
/* SDRAM Low temperature operating limit exceeded */
#define LPDDR3_LT_EXED (0x0)
#define LPDDR3_4_TREF (0x1)
#define LPDDR3_2_TREF (0x2)
#define LPDDR3_1_TREF (0x3)
#define LPDDR3_05_TREF (0x4)
#define LPDDR3_025_TREF (0x5)
#define LPDDR3_025_TREF_DERATE (0x6)
/* SDRAM High temperature operating limit exceeded */
#define LPDDR3_HT_EXED (0x7)
/* 1:value has changed since last read of MR4 */
#define LPDDR3_TUF (0x1 << 7)
/* MR8 (Basic configuration 4) */
#define LPDDR3_S8 (0x3)
#define LPDDR3_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf))
#define LPDDR3_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3))
/* MR10 (Calibration) */
#define LPDDR3_ZQINIT (0xff)
#define LPDDR3_ZQCL (0xab)
#define LPDDR3_ZQCS (0x56)
#define LPDDR3_ZQRESET (0xc3)
/* MR11 (ODT Control) */
#define LPDDR3_ODT_60 (1)
#define LPDDR3_ODT_120 (2)
#define LPDDR3_ODT_240 (3)
#define LPDDR3_ODT_DIS (0)
/* MR2 (Device Feature 2) */
/* RL & nRTP for DBI-RD Disabled */
#define LPDDR4_RL6_NRTP8 (0x0)
#define LPDDR4_RL10_NRTP8 (0x1)
#define LPDDR4_RL14_NRTP8 (0x2)
#define LPDDR4_RL20_NRTP8 (0x3)
#define LPDDR4_RL24_NRTP10 (0x4)
#define LPDDR4_RL28_NRTP12 (0x5)
#define LPDDR4_RL32_NRTP14 (0x6)
#define LPDDR4_RL36_NRTP16 (0x7)
/* RL & nRTP for DBI-RD Disabled */
#define LPDDR4_RL12_NRTP8 (0x1)
#define LPDDR4_RL16_NRTP8 (0x2)
#define LPDDR4_RL22_NRTP8 (0x3)
#define LPDDR4_RL28_NRTP10 (0x4)
#define LPDDR4_RL32_NRTP12 (0x5)
#define LPDDR4_RL36_NRTP14 (0x6)
#define LPDDR4_RL40_NRTP16 (0x7)
/* WL Set A,default */
#define LPDDR4_A_WL4 (0x0)
#define LPDDR4_A_WL6 (0x1)
#define LPDDR4_A_WL8 (0x2)
#define LPDDR4_A_WL10 (0x3)
#define LPDDR4_A_WL12 (0x4)
#define LPDDR4_A_WL14 (0x5)
#define LPDDR4_A_WL16 (0x6)
#define LPDDR4_A_WL18 (0x7)
/* WL Set B, optional */
#define LPDDR4_B_WL4 (0x0 << 3)
#define LPDDR4_B_WL8 (0x1 << 3)
#define LPDDR4_B_WL12 (0x2 << 3)
#define LPDDR4_B_WL18 (0x3 << 3)
#define LPDDR4_B_WL22 (0x4 << 3)
#define LPDDR4_B_WL26 (0x5 << 3)
#define LPDDR4_B_WL30 (0x6 << 3)
#define LPDDR4_B_WL34 (0x7 << 3)
/* 1:Select WL Set B*/
#define LPDDR4_WL_B (1 << 6)
/* 1:enable*/
#define LPDDR4_WR_LEVEL (1 << 7)
/* MR3 */
#define LPDDR4_VDDQ_2_5 (0)
#define LPDDR4_VDDQ_3 (1)
#define LPDDR4_WRPST_0_5_TCK (0 << 1)
#define LPDDR4_WRPST_1_5_TCK (1 << 1)
#define LPDDR4_PPR_EN (1 << 2)
/* PDDS */
#define LPDDR4_PDDS_240 (0x1 << 3)
#define LPDDR4_PDDS_120 (0x2 << 3)
#define LPDDR4_PDDS_80 (0x3 << 3)
#define LPDDR4_PDDS_60 (0x4 << 3)
#define LPDDR4_PDDS_48 (0x5 << 3)
#define LPDDR4_PDDS_40 (0x6 << 3)
#define LPDDR4_DBI_RD_EN (1 << 6)
#define LPDDR4_DBI_WR_EN (1 << 7)
/* MR11 (ODT Control) */
#define LPDDR4_DQODT_240 (1)
#define LPDDR4_DQODT_120 (2)
#define LPDDR4_DQODT_80 (3)
#define LPDDR4_DQODT_60 (4)
#define LPDDR4_DQODT_48 (5)
#define LPDDR4_DQODT_40 (6)
#define LPDDR4_DQODT_DIS (0)
#define LPDDR4_CAODT_240 (1 << 4)
#define LPDDR4_CAODT_120 (2 << 4)
#define LPDDR4_CAODT_80 (3 << 4)
#define LPDDR4_CAODT_60 (4 << 4)
#define LPDDR4_CAODT_48 (5 << 4)
#define LPDDR4_CAODT_40 (6 << 4)
#define LPDDR4_CAODT_DIS (0 << 4)
/*
* Description: depend on input parameter "timing_config",
* and calculate correspond "dram_type"
* spec timing to "pdram_timing"
* parameters:
* input: timing_config
* output: pdram_timing
* NOTE: MR ODT is set, need to disable by controller
*/
void dram_get_parameter(struct timing_related_config *timing_config,
struct dram_timing_t *pdram_timing);
#endif /* DRAM_SPEC_TIMING_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/rockchip/rk3399/drivers/dram/suspend.c
+852
View File
@@ -0,0 +1,852 @@
/*
* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <platform_def.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <dram.h>
#include <plat_private.h>
#include <pmu.h>
#include <pmu_bits.h>
#include <pmu_regs.h>
#include <rk3399_def.h>
#include <secure.h>
#include <soc.h>
#include <suspend.h>
#define PMUGRF_OS_REG0 0x300
#define PMUGRF_OS_REG1 0x304
#define PMUGRF_OS_REG2 0x308
#define PMUGRF_OS_REG3 0x30c
#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
((n) << (8 + (ch) * 4)))
#define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \
((n) << (9 + (ch) * 4)))
#define FBDIV_ENC(n) ((n) << 16)
#define FBDIV_DEC(n) (((n) >> 16) & 0xfff)
#define POSTDIV2_ENC(n) ((n) << 12)
#define POSTDIV2_DEC(n) (((n) >> 12) & 0x7)
#define POSTDIV1_ENC(n) ((n) << 8)
#define POSTDIV1_DEC(n) (((n) >> 8) & 0x7)
#define REFDIV_ENC(n) (n)
#define REFDIV_DEC(n) ((n) & 0x3f)
/* PMU CRU */
#define PMUCRU_RSTNHOLD_CON0 0x120
#define PMUCRU_RSTNHOLD_CON1 0x124
#define PRESET_GPIO0_HOLD(n) (((n) << 7) | WMSK_BIT(7))
#define PRESET_GPIO1_HOLD(n) (((n) << 8) | WMSK_BIT(8))
#define SYS_COUNTER_FREQ_IN_MHZ (SYS_COUNTER_FREQ_IN_TICKS / 1000000)
__pmusramdata uint32_t dpll_data[PLL_CON_COUNT];
__pmusramdata uint32_t cru_clksel_con6;
__pmusramdata uint8_t pmu_enable_watchdog0;
/*
* Copy @num registers from @src to @dst
*/
static __pmusramfunc void sram_regcpy(uintptr_t dst, uintptr_t src,
uint32_t num)
{
while (num--) {
mmio_write_32(dst, mmio_read_32(src));
dst += sizeof(uint32_t);
src += sizeof(uint32_t);
}
}
/*
* Copy @num registers from @src to @dst
* This is intentionally a copy of the sram_regcpy function. PMUSRAM functions
* cannot be called from code running in DRAM.
*/
static void dram_regcpy(uintptr_t dst, uintptr_t src, uint32_t num)
{
while (num--) {
mmio_write_32(dst, mmio_read_32(src));
dst += sizeof(uint32_t);
src += sizeof(uint32_t);
}
}
static __pmusramfunc uint32_t sram_get_timer_value(void)
{
/*
* Generic delay timer implementation expects the timer to be a down
* counter. We apply bitwise NOT operator to the tick values returned
* by read_cntpct_el0() to simulate the down counter.
*/
return (uint32_t)(~read_cntpct_el0());
}
static __pmusramfunc void sram_udelay(uint32_t usec)
{
uint32_t start, cnt, delta, total_ticks;
/* counter is decreasing */
start = sram_get_timer_value();
total_ticks = usec * SYS_COUNTER_FREQ_IN_MHZ;
do {
cnt = sram_get_timer_value();
if (cnt > start) {
delta = UINT32_MAX - cnt;
delta += start;
} else
delta = start - cnt;
} while (delta <= total_ticks);
}
static __pmusramfunc void configure_sgrf(void)
{
/*
* SGRF_DDR_RGN_DPLL_CLK and SGRF_DDR_RGN_RTC_CLK:
* IC ECO bug, need to set this register.
*
* SGRF_DDR_RGN_BYPS:
* After the PD_CENTER suspend/resume, the DDR region
* related registers in the SGRF will be reset, we
* need to re-initialize them.
*/
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
SGRF_DDR_RGN_DPLL_CLK |
SGRF_DDR_RGN_RTC_CLK |
SGRF_DDR_RGN_BYPS);
}
static __pmusramfunc void rkclk_ddr_reset(uint32_t channel, uint32_t ctl,
uint32_t phy)
{
channel &= 0x1;
ctl &= 0x1;
phy &= 0x1;
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(4),
CRU_SFTRST_DDR_CTRL(channel, ctl) |
CRU_SFTRST_DDR_PHY(channel, phy));
}
static __pmusramfunc void phy_pctrl_reset(uint32_t ch)
{
rkclk_ddr_reset(ch, 1, 1);
sram_udelay(10);
rkclk_ddr_reset(ch, 1, 0);
sram_udelay(10);
rkclk_ddr_reset(ch, 0, 0);
sram_udelay(10);
}
static __pmusramfunc void set_cs_training_index(uint32_t ch, uint32_t rank)
{
uint32_t byte;
/* PHY_8/136/264/392 phy_per_cs_training_index_X 1bit offset_24 */
for (byte = 0; byte < 4; byte++)
mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 24,
rank << 24);
}
static __pmusramfunc void select_per_cs_training_index(uint32_t ch,
uint32_t rank)
{
/* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
if ((mmio_read_32(PHY_REG(ch, 84)) >> 16) & 1)
set_cs_training_index(ch, rank);
}
static __pmusramfunc void override_write_leveling_value(uint32_t ch)
{
uint32_t byte;
for (byte = 0; byte < 4; byte++) {
/*
* PHY_8/136/264/392
* phy_per_cs_training_multicast_en_X 1bit offset_16
*/
mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 16,
1 << 16);
mmio_clrsetbits_32(PHY_REG(ch, 63 + (128 * byte)),
0xffffu << 16,
0x200 << 16);
}
/* CTL_200 ctrlupd_req 1bit offset_8 */
mmio_clrsetbits_32(CTL_REG(ch, 200), 0x1 << 8, 0x1 << 8);
}
static __pmusramfunc int data_training(uint32_t ch,
struct rk3399_sdram_params *sdram_params,
uint32_t training_flag)
{
uint32_t obs_0, obs_1, obs_2, obs_3, obs_err = 0;
uint32_t rank = sdram_params->ch[ch].rank;
uint32_t rank_mask;
uint32_t i, tmp;
if (sdram_params->dramtype == LPDDR4)
rank_mask = (rank == 1) ? 0x5 : 0xf;
else
rank_mask = (rank == 1) ? 0x1 : 0x3;
/* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
mmio_setbits_32(PHY_REG(ch, 927), (1 << 22));
if (training_flag == PI_FULL_TRAINING) {
if (sdram_params->dramtype == LPDDR4) {
training_flag = PI_WRITE_LEVELING |
PI_READ_GATE_TRAINING |
PI_READ_LEVELING |
PI_WDQ_LEVELING;
} else if (sdram_params->dramtype == LPDDR3) {
training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
PI_READ_GATE_TRAINING;
} else if (sdram_params->dramtype == DDR3) {
training_flag = PI_WRITE_LEVELING |
PI_READ_GATE_TRAINING |
PI_READ_LEVELING;
}
}
/* ca training(LPDDR4,LPDDR3 support) */
if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
for (i = 0; i < 4; i++) {
if (!(rank_mask & (1 << i)))
continue;
select_per_cs_training_index(ch, i);
/* PI_100 PI_CALVL_EN:RW:8:2 */
mmio_clrsetbits_32(PI_REG(ch, 100), 0x3 << 8, 0x2 << 8);
/* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
mmio_clrsetbits_32(PI_REG(ch, 92),
(0x1 << 16) | (0x3 << 24),
(0x1 << 16) | (i << 24));
while (1) {
/* PI_174 PI_INT_STATUS:RD:8:18 */
tmp = mmio_read_32(PI_REG(ch, 174)) >> 8;
/*
* check status obs
* PHY_532/660/788 phy_adr_calvl_obs1_:0:32
*/
obs_0 = mmio_read_32(PHY_REG(ch, 532));
obs_1 = mmio_read_32(PHY_REG(ch, 660));
obs_2 = mmio_read_32(PHY_REG(ch, 788));
if (((obs_0 >> 30) & 0x3) ||
((obs_1 >> 30) & 0x3) ||
((obs_2 >> 30) & 0x3))
obs_err = 1;
if ((((tmp >> 11) & 0x1) == 0x1) &&
(((tmp >> 13) & 0x1) == 0x1) &&
(((tmp >> 5) & 0x1) == 0x0) &&
(obs_err == 0))
break;
else if ((((tmp >> 5) & 0x1) == 0x1) ||
(obs_err == 1))
return -1;
}
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
mmio_write_32(PI_REG(ch, 175), 0x00003f7c);
}
mmio_clrbits_32(PI_REG(ch, 100), 0x3 << 8);
}
/* write leveling(LPDDR4,LPDDR3,DDR3 support) */
if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
for (i = 0; i < rank; i++) {
select_per_cs_training_index(ch, i);
/* PI_60 PI_WRLVL_EN:RW:8:2 */
mmio_clrsetbits_32(PI_REG(ch, 60), 0x3 << 8, 0x2 << 8);
/* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
mmio_clrsetbits_32(PI_REG(ch, 59),
(0x1 << 8) | (0x3 << 16),
(0x1 << 8) | (i << 16));
while (1) {
/* PI_174 PI_INT_STATUS:RD:8:18 */
tmp = mmio_read_32(PI_REG(ch, 174)) >> 8;
/*
* check status obs, if error maybe can not
* get leveling done PHY_40/168/296/424
* phy_wrlvl_status_obs_X:0:13
*/
obs_0 = mmio_read_32(PHY_REG(ch, 40));
obs_1 = mmio_read_32(PHY_REG(ch, 168));
obs_2 = mmio_read_32(PHY_REG(ch, 296));
obs_3 = mmio_read_32(PHY_REG(ch, 424));
if (((obs_0 >> 12) & 0x1) ||
((obs_1 >> 12) & 0x1) ||
((obs_2 >> 12) & 0x1) ||
((obs_3 >> 12) & 0x1))
obs_err = 1;
if ((((tmp >> 10) & 0x1) == 0x1) &&
(((tmp >> 13) & 0x1) == 0x1) &&
(((tmp >> 4) & 0x1) == 0x0) &&
(obs_err == 0))
break;
else if ((((tmp >> 4) & 0x1) == 0x1) ||
(obs_err == 1))
return -1;
}
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
mmio_write_32(PI_REG(ch, 175), 0x00003f7c);
}
override_write_leveling_value(ch);
mmio_clrbits_32(PI_REG(ch, 60), 0x3 << 8);
}
/* read gate training(LPDDR4,LPDDR3,DDR3 support) */
if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
for (i = 0; i < rank; i++) {
select_per_cs_training_index(ch, i);
/* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 24,
0x2 << 24);
/*
* PI_74 PI_RDLVL_GATE_REQ:WR:16:1
* PI_RDLVL_CS:RW:24:2
*/
mmio_clrsetbits_32(PI_REG(ch, 74),
(0x1 << 16) | (0x3 << 24),
(0x1 << 16) | (i << 24));
while (1) {
/* PI_174 PI_INT_STATUS:RD:8:18 */
tmp = mmio_read_32(PI_REG(ch, 174)) >> 8;
/*
* check status obs
* PHY_43/171/299/427
* PHY_GTLVL_STATUS_OBS_x:16:8
*/
obs_0 = mmio_read_32(PHY_REG(ch, 43));
obs_1 = mmio_read_32(PHY_REG(ch, 171));
obs_2 = mmio_read_32(PHY_REG(ch, 299));
obs_3 = mmio_read_32(PHY_REG(ch, 427));
if (((obs_0 >> (16 + 6)) & 0x3) ||
((obs_1 >> (16 + 6)) & 0x3) ||
((obs_2 >> (16 + 6)) & 0x3) ||
((obs_3 >> (16 + 6)) & 0x3))
obs_err = 1;
if ((((tmp >> 9) & 0x1) == 0x1) &&
(((tmp >> 13) & 0x1) == 0x1) &&
(((tmp >> 3) & 0x1) == 0x0) &&
(obs_err == 0))
break;
else if ((((tmp >> 3) & 0x1) == 0x1) ||
(obs_err == 1))
return -1;
}
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
mmio_write_32(PI_REG(ch, 175), 0x00003f7c);
}
mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 24);
}
/* read leveling(LPDDR4,LPDDR3,DDR3 support) */
if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
for (i = 0; i < rank; i++) {
select_per_cs_training_index(ch, i);
/* PI_80 PI_RDLVL_EN:RW:16:2 */
mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 16,
0x2 << 16);
/* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
mmio_clrsetbits_32(PI_REG(ch, 74),
(0x1 << 8) | (0x3 << 24),
(0x1 << 8) | (i << 24));
while (1) {
/* PI_174 PI_INT_STATUS:RD:8:18 */
tmp = mmio_read_32(PI_REG(ch, 174)) >> 8;
/*
* make sure status obs not report error bit
* PHY_46/174/302/430
* phy_rdlvl_status_obs_X:16:8
*/
if ((((tmp >> 8) & 0x1) == 0x1) &&
(((tmp >> 13) & 0x1) == 0x1) &&
(((tmp >> 2) & 0x1) == 0x0))
break;
else if (((tmp >> 2) & 0x1) == 0x1)
return -1;
}
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
mmio_write_32(PI_REG(ch, 175), 0x00003f7c);
}
mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 16);
}
/* wdq leveling(LPDDR4 support) */
if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
for (i = 0; i < 4; i++) {
if (!(rank_mask & (1 << i)))
continue;
select_per_cs_training_index(ch, i);
/*
* disable PI_WDQLVL_VREF_EN before wdq leveling?
* PI_181 PI_WDQLVL_VREF_EN:RW:8:1
*/
mmio_clrbits_32(PI_REG(ch, 181), 0x1 << 8);
/* PI_124 PI_WDQLVL_EN:RW:16:2 */
mmio_clrsetbits_32(PI_REG(ch, 124), 0x3 << 16,
0x2 << 16);
/* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
mmio_clrsetbits_32(PI_REG(ch, 121),
(0x1 << 8) | (0x3 << 16),
(0x1 << 8) | (i << 16));
while (1) {
/* PI_174 PI_INT_STATUS:RD:8:18 */
tmp = mmio_read_32(PI_REG(ch, 174)) >> 8;
if ((((tmp >> 12) & 0x1) == 0x1) &&
(((tmp >> 13) & 0x1) == 0x1) &&
(((tmp >> 6) & 0x1) == 0x0))
break;
else if (((tmp >> 6) & 0x1) == 0x1)
return -1;
}
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
mmio_write_32(PI_REG(ch, 175), 0x00003f7c);
}
mmio_clrbits_32(PI_REG(ch, 124), 0x3 << 16);
}
/* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
mmio_clrbits_32(PHY_REG(ch, 927), (1 << 22));
return 0;
}
static __pmusramfunc void set_ddrconfig(
struct rk3399_sdram_params *sdram_params,
unsigned char channel, uint32_t ddrconfig)
{
/* only need to set ddrconfig */
struct rk3399_sdram_channel *ch = &sdram_params->ch[channel];
unsigned int cs0_cap = 0;
unsigned int cs1_cap = 0;
cs0_cap = (1 << (ch->cs0_row + ch->col + ch->bk + ch->bw - 20));
if (ch->rank > 1)
cs1_cap = cs0_cap >> (ch->cs0_row - ch->cs1_row);
if (ch->row_3_4) {
cs0_cap = cs0_cap * 3 / 4;
cs1_cap = cs1_cap * 3 / 4;
}
mmio_write_32(MSCH_BASE(channel) + MSCH_DEVICECONF,
ddrconfig | (ddrconfig << 6));
mmio_write_32(MSCH_BASE(channel) + MSCH_DEVICESIZE,
((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8));
}
static __pmusramfunc void dram_all_config(
struct rk3399_sdram_params *sdram_params)
{
unsigned int i;
for (i = 0; i < 2; i++) {
struct rk3399_sdram_channel *info = &sdram_params->ch[i];
struct rk3399_msch_timings *noc = &info->noc_timings;
if (sdram_params->ch[i].col == 0)
continue;
mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGA0,
noc->ddrtiminga0.d32);
mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGB0,
noc->ddrtimingb0.d32);
mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGC0,
noc->ddrtimingc0.d32);
mmio_write_32(MSCH_BASE(i) + MSCH_DEVTODEV0,
noc->devtodev0.d32);
mmio_write_32(MSCH_BASE(i) + MSCH_DDRMODE, noc->ddrmode.d32);
/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
if (sdram_params->ch[i].rank == 1)
mmio_setbits_32(CTL_REG(i, 276), 1 << 17);
}
DDR_STRIDE(sdram_params->stride);
/* reboot hold register set */
mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1),
CRU_PMU_SGRF_RST_RLS |
PRESET_GPIO0_HOLD(1) |
PRESET_GPIO1_HOLD(1));
mmio_clrsetbits_32(CRU_BASE + CRU_GLB_RST_CON, 0x3, 0x3);
}
static __pmusramfunc void pctl_cfg(uint32_t ch,
struct rk3399_sdram_params *sdram_params)
{
const uint32_t *params_ctl = sdram_params->pctl_regs.denali_ctl;
const uint32_t *params_pi = sdram_params->pi_regs.denali_pi;
const struct rk3399_ddr_publ_regs *phy_regs = &sdram_params->phy_regs;
uint32_t tmp, tmp1, tmp2, i;
/*
* Workaround controller bug:
* Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
*/
sram_regcpy(CTL_REG(ch, 1), (uintptr_t)&params_ctl[1],
CTL_REG_NUM - 1);
mmio_write_32(CTL_REG(ch, 0), params_ctl[0]);
sram_regcpy(PI_REG(ch, 0), (uintptr_t)&params_pi[0],
PI_REG_NUM);
sram_regcpy(PHY_REG(ch, 910), (uintptr_t)&phy_regs->phy896[910 - 896],
3);
mmio_clrsetbits_32(CTL_REG(ch, 68), PWRUP_SREFRESH_EXIT,
PWRUP_SREFRESH_EXIT);
/* PHY_DLL_RST_EN */
mmio_clrsetbits_32(PHY_REG(ch, 957), 0x3 << 24, 1 << 24);
dmbst();
mmio_setbits_32(PI_REG(ch, 0), START);
mmio_setbits_32(CTL_REG(ch, 0), START);
/* wait lock */
while (1) {
tmp = mmio_read_32(PHY_REG(ch, 920));
tmp1 = mmio_read_32(PHY_REG(ch, 921));
tmp2 = mmio_read_32(PHY_REG(ch, 922));
if ((((tmp >> 16) & 0x1) == 0x1) &&
(((tmp1 >> 16) & 0x1) == 0x1) &&
(((tmp1 >> 0) & 0x1) == 0x1) &&
(((tmp2 >> 0) & 0x1) == 0x1))
break;
/* if PLL bypass,don't need wait lock */
if (mmio_read_32(PHY_REG(ch, 911)) & 0x1)
break;
}
sram_regcpy(PHY_REG(ch, 896), (uintptr_t)&phy_regs->phy896[0], 63);
for (i = 0; i < 4; i++)
sram_regcpy(PHY_REG(ch, 128 * i),
(uintptr_t)&phy_regs->phy0[0], 91);
for (i = 0; i < 3; i++)
sram_regcpy(PHY_REG(ch, 512 + 128 * i),
(uintptr_t)&phy_regs->phy512[i][0], 38);
}
static __pmusramfunc int dram_switch_to_next_index(
struct rk3399_sdram_params *sdram_params)
{
uint32_t ch, ch_count;
uint32_t fn = ((mmio_read_32(CTL_REG(0, 111)) >> 16) + 1) & 0x1;
mmio_write_32(CIC_BASE + CIC_CTRL0,
(((0x3 << 4) | (1 << 2) | 1) << 16) |
(fn << 4) | (1 << 2) | 1);
while (!(mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2)))
;
mmio_write_32(CIC_BASE + CIC_CTRL0, 0x20002);
while (!(mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0)))
;
ch_count = sdram_params->num_channels;
/* LPDDR4 f2 cann't do training, all training will fail */
for (ch = 0; ch < ch_count; ch++) {
/*
* Without this disabled for LPDDR4 we end up writing 0's
* in place of real data in an interesting pattern.
*/
if (sdram_params->dramtype != LPDDR4) {
mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1,
fn << 8);
}
/* data_training failed */
if (data_training(ch, sdram_params, PI_FULL_TRAINING))
return -1;
}
return 0;
}
/*
* Needs to be done for both channels at once in case of a shared reset signal
* between channels.
*/
static __pmusramfunc int pctl_start(uint32_t channel_mask,
struct rk3399_sdram_params *sdram_params)
{
uint32_t count;
uint32_t byte;
mmio_setbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT);
mmio_setbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT);
/* need de-access IO retention before controller START */
if (channel_mask & (1 << 0))
mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 19));
if (channel_mask & (1 << 1))
mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 23));
/* PHY_DLL_RST_EN */
if (channel_mask & (1 << 0))
mmio_clrsetbits_32(PHY_REG(0, 957), 0x3 << 24,
0x2 << 24);
if (channel_mask & (1 << 1))
mmio_clrsetbits_32(PHY_REG(1, 957), 0x3 << 24,
0x2 << 24);
/* check ERROR bit */
if (channel_mask & (1 << 0)) {
count = 0;
while (!(mmio_read_32(CTL_REG(0, 203)) & (1 << 3))) {
/* CKE is low, loop 10ms */
if (count > 100)
return -1;
sram_udelay(100);
count++;
}
mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT);
/* Restore the PHY_RX_CAL_DQS value */
for (byte = 0; byte < 4; byte++)
mmio_clrsetbits_32(PHY_REG(0, 57 + 128 * byte),
0xfff << 16,
sdram_params->rx_cal_dqs[0][byte]);
}
if (channel_mask & (1 << 1)) {
count = 0;
while (!(mmio_read_32(CTL_REG(1, 203)) & (1 << 3))) {
/* CKE is low, loop 10ms */
if (count > 100)
return -1;
sram_udelay(100);
count++;
}
mmio_clrbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT);
/* Restore the PHY_RX_CAL_DQS value */
for (byte = 0; byte < 4; byte++)
mmio_clrsetbits_32(PHY_REG(1, 57 + 128 * byte),
0xfff << 16,
sdram_params->rx_cal_dqs[1][byte]);
}
return 0;
}
__pmusramfunc static void pmusram_restore_pll(int pll_id, uint32_t *src)
{
mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE);
mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK);
mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK);
mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]);
mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK);
mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK);
mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK);
while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) &
(1U << 31)) == 0x0)
;
}
__pmusramfunc static void pmusram_enable_watchdog(void)
{
/* Make the watchdog use the first global reset. */
mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, 1 << 1);
/*
* This gives the system ~8 seconds before reset. The pclk for the
* watchdog is 4MHz on reset. The value of 0x9 in WDT_TORR means that
* the watchdog will wait for 0x1ffffff cycles before resetting.
*/
mmio_write_32(WDT0_BASE + 4, 0x9);
/* Enable the watchdog */
mmio_setbits_32(WDT0_BASE, 0x1);
/* Magic reset the watchdog timer value for WDT_CRR. */
mmio_write_32(WDT0_BASE + 0xc, 0x76);
secure_watchdog_ungate();
/* The watchdog is in PD_ALIVE, so deidle it. */
mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, PMU_CLR_ALIVE);
}
void dmc_suspend(void)
{
struct rk3399_sdram_params *sdram_params = &sdram_config;
struct rk3399_ddr_publ_regs *phy_regs;
uint32_t *params_ctl;
uint32_t *params_pi;
uint32_t refdiv, postdiv2, postdiv1, fbdiv;
uint32_t ch, byte, i;
phy_regs = &sdram_params->phy_regs;
params_ctl = sdram_params->pctl_regs.denali_ctl;
params_pi = sdram_params->pi_regs.denali_pi;
/* save dpll register and ddr clock register value to pmusram */
cru_clksel_con6 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON6);
for (i = 0; i < PLL_CON_COUNT; i++)
dpll_data[i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, i));
fbdiv = dpll_data[0] & 0xfff;
postdiv2 = POSTDIV2_DEC(dpll_data[1]);
postdiv1 = POSTDIV1_DEC(dpll_data[1]);
refdiv = REFDIV_DEC(dpll_data[1]);
sdram_params->ddr_freq = ((fbdiv * 24) /
(refdiv * postdiv1 * postdiv2)) * MHz;
INFO("sdram_params->ddr_freq = %d\n", sdram_params->ddr_freq);
sdram_params->odt = (((mmio_read_32(PHY_REG(0, 5)) >> 16) &
0x7) != 0) ? 1 : 0;
/* copy the registers CTL PI and PHY */
dram_regcpy((uintptr_t)&params_ctl[0], CTL_REG(0, 0), CTL_REG_NUM);
/* mask DENALI_CTL_00_DATA.START, only copy here, will trigger later */
params_ctl[0] &= ~(0x1 << 0);
dram_regcpy((uintptr_t)&params_pi[0], PI_REG(0, 0),
PI_REG_NUM);
/* mask DENALI_PI_00_DATA.START, only copy here, will trigger later*/
params_pi[0] &= ~(0x1 << 0);
dram_regcpy((uintptr_t)&phy_regs->phy0[0],
PHY_REG(0, 0), 91);
for (i = 0; i < 3; i++)
dram_regcpy((uintptr_t)&phy_regs->phy512[i][0],
PHY_REG(0, 512 + 128 * i), 38);
dram_regcpy((uintptr_t)&phy_regs->phy896[0], PHY_REG(0, 896), 63);
for (ch = 0; ch < sdram_params->num_channels; ch++) {
for (byte = 0; byte < 4; byte++)
sdram_params->rx_cal_dqs[ch][byte] = (0xfff << 16) &
mmio_read_32(PHY_REG(ch, 57 + byte * 128));
}
/* set DENALI_PHY_957_DATA.PHY_DLL_RST_EN = 0x1 */
phy_regs->phy896[957 - 896] &= ~(0x3 << 24);
phy_regs->phy896[957 - 896] |= 1 << 24;
phy_regs->phy896[0] |= 1;
phy_regs->phy896[0] &= ~(0x3 << 8);
}
__pmusramfunc void phy_dll_bypass_set(uint32_t ch, uint32_t freq)
{
if (freq <= (125 * 1000 * 1000)) {
/* Set master mode to SW for slices*/
mmio_setbits_32(PHY_REG(ch, 86), 3 << 10);
mmio_setbits_32(PHY_REG(ch, 214), 3 << 10);
mmio_setbits_32(PHY_REG(ch, 342), 3 << 10);
mmio_setbits_32(PHY_REG(ch, 470), 3 << 10);
/* Set master mode to SW for address slices*/
mmio_setbits_32(PHY_REG(ch, 547), 3 << 18);
mmio_setbits_32(PHY_REG(ch, 675), 3 << 18);
mmio_setbits_32(PHY_REG(ch, 803), 3 << 18);
} else {
/* Clear SW master mode for slices*/
mmio_clrbits_32(PHY_REG(ch, 86), 3 << 10);
mmio_clrbits_32(PHY_REG(ch, 214), 3 << 10);
mmio_clrbits_32(PHY_REG(ch, 342), 3 << 10);
mmio_clrbits_32(PHY_REG(ch, 470), 3 << 10);
/* Clear SW master mode for address slices*/
mmio_clrbits_32(PHY_REG(ch, 547), 3 << 18);
mmio_clrbits_32(PHY_REG(ch, 675), 3 << 18);
mmio_clrbits_32(PHY_REG(ch, 803), 3 << 18);
}
}
__pmusramfunc void dmc_resume(void)
{
struct rk3399_sdram_params *sdram_params = &sdram_config;
uint32_t channel_mask = 0;
uint32_t channel;
/*
* We can't turn off the watchdog, so if we have not turned it on before
* we should not turn it on here.
*/
if ((pmu_enable_watchdog0 & 0x1) == 0x1) {
pmusram_enable_watchdog();
}
pmu_sgrf_rst_hld_release();
restore_pmu_rsthold();
sram_secure_timer_init();
/*
* we switch ddr clock to abpll when suspend,
* we set back to dpll here
*/
mmio_write_32(CRU_BASE + CRU_CLKSEL_CON6,
cru_clksel_con6 | REG_SOC_WMSK);
pmusram_restore_pll(DPLL_ID, dpll_data);
configure_sgrf();
retry:
for (channel = 0; channel < sdram_params->num_channels; channel++) {
phy_pctrl_reset(channel);
/*
* Without this, LPDDR4 will write 0's in place of real data
* in a strange pattern.
*/
if (sdram_params->dramtype == LPDDR4) {
phy_dll_bypass_set(channel, sdram_params->ddr_freq);
}
pctl_cfg(channel, sdram_params);
}
for (channel = 0; channel < 2; channel++) {
if (sdram_params->ch[channel].col)
channel_mask |= 1 << channel;
}
if (pctl_start(channel_mask, sdram_params) < 0)
goto retry;
for (channel = 0; channel < sdram_params->num_channels; channel++) {
/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
if (sdram_params->dramtype == LPDDR3)
sram_udelay(10);
/*
* Training here will always fail for LPDDR4, so skip it
* If traning fail, retry to do it again.
*/
if (sdram_params->dramtype != LPDDR4 &&
data_training(channel, sdram_params, PI_FULL_TRAINING))
goto retry;
set_ddrconfig(sdram_params, channel,
sdram_params->ch[channel].ddrconfig);
}
dram_all_config(sdram_params);
/* Switch to index 1 and prepare for DDR frequency switch. */
dram_switch_to_next_index(sdram_params);
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/rockchip/rk3399/drivers/dram/suspend.h
+28
View File
@@ -0,0 +1,28 @@
/*
* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SUSPEND_H
#define SUSPEND_H
#include <stdint.h>
#include <dram.h>
#define KHz (1000)
#define MHz (1000 * KHz)
#define GHz (1000 * MHz)
#define PI_CA_TRAINING (1 << 0)
#define PI_WRITE_LEVELING (1 << 1)
#define PI_READ_GATE_TRAINING (1 << 2)
#define PI_READ_LEVELING (1 << 3)
#define PI_WDQ_LEVELING (1 << 4)
#define PI_FULL_TRAINING (0xff)
void dmc_suspend(void);
__pmusramfunc void dmc_resume(void);
extern __pmusramdata uint8_t pmu_enable_watchdog0;
#endif /* SUSPEND_H */