GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <m0_ctl.h>
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#include <plat_private.h>
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#include <rk3399_def.h>
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#include <secure.h>
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#include <soc.h>
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void m0_init(void)
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{
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/* secure config for M0 */
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mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7));
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), WMSK_BIT(12));
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/* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */
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mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02);
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/*
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* To switch the parent to xin24M and div == 1,
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*
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* We need to close most of the PLLs and clocks except the OSC 24MHz
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* durning suspend, and this should be enough to supplies the ddrfreq,
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* For the simple handle, we just keep the fixed 24MHz to supply the
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* suspend and ddrfreq directly.
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*/
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mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0,
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BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8));
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mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5));
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}
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void m0_configure_execute_addr(uintptr_t addr)
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{
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/* set the execute address for M0 */
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mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3),
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BITS_WITH_WMASK((addr >> 12) & 0xffff,
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0xffffu, 0));
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mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7),
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BITS_WITH_WMASK((addr >> 28) & 0xf,
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0xfu, 0));
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}
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void m0_start(void)
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{
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/* enable clocks for M0 */
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mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
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BITS_WITH_WMASK(0x0, 0xf, 0));
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/* clean the PARAM_M0_DONE flag, mean that M0 will start working */
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mmio_write_32(M0_PARAM_ADDR + PARAM_M0_DONE, 0);
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dmbst();
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mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
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BITS_WITH_WMASK(0x0, 0x4, 0));
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udelay(5);
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/* start M0 */
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mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
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BITS_WITH_WMASK(0x0, 0x20, 0));
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dmbst();
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}
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void m0_stop(void)
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{
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/* stop M0 */
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mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
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BITS_WITH_WMASK(0x24, 0x24, 0));
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/* disable clocks for M0 */
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mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
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BITS_WITH_WMASK(0xf, 0xf, 0));
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}
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void m0_wait_done(void)
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{
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do {
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/*
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* Don't starve the M0 for access to SRAM, so delay before
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* reading the PARAM_M0_DONE value again.
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*/
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udelay(5);
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dsb();
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} while (mmio_read_32(M0_PARAM_ADDR + PARAM_M0_DONE) != M0_DONE_FLAG);
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/*
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* Let the M0 settle into WFI before we leave. This is so we don't reset
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* the M0 in a bad spot which can cause problems with the M0.
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*/
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udelay(10);
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dsb();
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}
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+29
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef M0_CTL_H
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#define M0_CTL_H
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#include <m0_param.h>
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#define M0_BINCODE_BASE ((uintptr_t)rk3399m0_bin)
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#define M0_PARAM_ADDR (M0_BINCODE_BASE + PARAM_ADDR)
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#define M0PMU_BINCODE_BASE ((uintptr_t)rk3399m0pmu_bin)
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/* pmu_fw.c */
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extern char rk3399m0_bin[];
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extern char rk3399m0_bin_end[];
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extern char rk3399m0pmu_bin[];
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extern char rk3399m0pmu_bin_end[];
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extern void m0_init(void);
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extern void m0_start(void);
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extern void m0_stop(void);
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extern void m0_wait_done(void);
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extern void m0_configure_execute_addr(uintptr_t addr);
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#endif /* M0_CTL_H */
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+136
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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#include <pmu_regs.h>
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.globl clst_warmboot_data
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.macro sram_func _name
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.cfi_sections .debug_frame
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.section .sram.text, "ax"
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.type \_name, %function
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.cfi_startproc
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\_name:
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.endm
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#define CRU_CLKSEL_CON6 0x118
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#define DDRCTL0_C_SYSREQ_CFG 0x0100
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#define DDRCTL1_C_SYSREQ_CFG 0x1000
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#define DDRC0_SREF_DONE_EXT 0x01
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#define DDRC1_SREF_DONE_EXT 0x04
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#define PLL_MODE_SHIFT (0x8)
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#define PLL_NORMAL_MODE ((0x3 << (PLL_MODE_SHIFT + 16)) | \
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(0x1 << PLL_MODE_SHIFT))
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#define MPIDR_CLST_L_BITS 0x0
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/*
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* For different socs, if we want to speed up warmboot,
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* we need to config some regs here.
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* If scu was suspend, we must resume related clk
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* from slow (24M) mode to normal mode first.
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* X0: MPIDR_EL1 & MPIDR_CLUSTER_MASK
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*/
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.macro func_rockchip_clst_warmboot
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adr x4, clst_warmboot_data
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lsr x5, x0, #6
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ldr w3, [x4, x5]
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str wzr, [x4, x5]
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cmp w3, #PMU_CLST_RET
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b.ne clst_warmboot_end
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ldr w6, =(PLL_NORMAL_MODE)
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/*
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* core_l offset is CRU_BASE + 0xc,
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* core_b offset is CRU_BASE + 0x2c
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*/
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ldr x7, =(CRU_BASE + 0xc)
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lsr x2, x0, #3
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str w6, [x7, x2]
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clst_warmboot_end:
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.endm
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.macro rockchip_clst_warmboot_data
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clst_warmboot_data:
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.rept PLATFORM_CLUSTER_COUNT
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.word 0
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.endr
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.endm
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/* -----------------------------------------------
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* void sram_func_set_ddrctl_pll(uint32_t pll_src)
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* Function to switch the PLL source for ddrctrl
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* In: x0 - The PLL of the clk_ddrc clock source
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* out: None
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* Clobber list : x0 - x3, x5, x8 - x10
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* -----------------------------------------------
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*/
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.globl sram_func_set_ddrctl_pll
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sram_func sram_func_set_ddrctl_pll
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/* backup parameter */
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mov x8, x0
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/* disable the MMU at EL3 */
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mrs x9, sctlr_el3
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bic x10, x9, #(SCTLR_M_BIT)
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msr sctlr_el3, x10
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isb
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dsb sy
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/* enable ddrctl0_1 idle request */
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mov x5, PMU_BASE
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ldr w0, [x5, #PMU_SFT_CON]
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orr w0, w0, #DDRCTL0_C_SYSREQ_CFG
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orr w0, w0, #DDRCTL1_C_SYSREQ_CFG
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str w0, [x5, #PMU_SFT_CON]
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check_ddrc0_1_sref_enter:
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ldr w1, [x5, #PMU_DDR_SREF_ST]
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and w2, w1, #DDRC0_SREF_DONE_EXT
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and w3, w1, #DDRC1_SREF_DONE_EXT
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orr w2, w2, w3
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cmp w2, #(DDRC0_SREF_DONE_EXT | DDRC1_SREF_DONE_EXT)
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b.eq check_ddrc0_1_sref_enter
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/*
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* select a PLL for ddrctrl:
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* x0 = 0: ALPLL
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* x0 = 1: ABPLL
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* x0 = 2: DPLL
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* x0 = 3: GPLLL
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*/
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mov x5, CRU_BASE
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lsl w0, w8, #4
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orr w0, w0, #0x00300000
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str w0, [x5, #CRU_CLKSEL_CON6]
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/* disable ddrctl0_1 idle request */
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mov x5, PMU_BASE
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ldr w0, [x5, #PMU_SFT_CON]
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bic w0, w0, #DDRCTL0_C_SYSREQ_CFG
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bic w0, w0, #DDRCTL1_C_SYSREQ_CFG
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str w0, [x5, #PMU_SFT_CON]
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check_ddrc0_1_sref_exit:
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ldr w1, [x5, #PMU_DDR_SREF_ST]
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and w2, w1, #DDRC0_SREF_DONE_EXT
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and w3, w1, #DDRC1_SREF_DONE_EXT
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orr w2, w2, w3
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cmp w2, #0x0
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b.eq check_ddrc0_1_sref_exit
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/* reenable the MMU at EL3 */
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msr sctlr_el3, x9
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isb
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dsb sy
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ret
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endfunc sram_func_set_ddrctl_pll
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+1626
File diff suppressed because it is too large
Load Diff
+141
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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PMU_H
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#define PMU_H
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#include <pmu_bits.h>
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#include <pmu_regs.h>
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#include <soc.h>
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/* Allocate sp reginon in pmusram */
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#define PSRAM_SP_SIZE 0x80
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#define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE)
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/*****************************************************************************
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* Common define for per soc pmu.h
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*****************************************************************************/
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/* The ways of cores power domain contorlling */
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enum cores_pm_ctr_mode {
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core_pwr_pd = 0,
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core_pwr_wfi = 1,
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core_pwr_wfi_int = 2
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};
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/*****************************************************************************
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* pmu con,reg
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*****************************************************************************/
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#define PMU_WKUP_CFG(n) ((n) * 4)
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#define PMU_CORE_PM_CON(cpu) (0xc0 + (cpu * 4))
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/* the shift of bits for cores status */
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enum pmu_core_pwrst_shift {
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clstl_cpu_wfe = 2,
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clstl_cpu_wfi = 6,
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clstb_cpu_wfe = 12,
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clstb_cpu_wfi = 16
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};
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#define CKECK_WFE_MSK 0x1
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#define CKECK_WFI_MSK 0x10
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#define CKECK_WFEI_MSK 0x11
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/* Specific features required */
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#define AP_PWROFF 0x0a
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#define GPIO0A0_SMT_ENABLE BITS_WITH_WMASK(1, 3, 0)
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#define GPIO1A6_IOMUX BITS_WITH_WMASK(0, 3, 12)
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#define TSADC_INT_PIN 38
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#define CORES_PM_DISABLE 0x0
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#define PD_CTR_LOOP 10000
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#define CHK_CPU_LOOP 500
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#define MAX_WAIT_COUNT 1000
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#define GRF_SOC_CON4 0x0e210
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#define PMUGRF_GPIO0A_SMT 0x0120
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#define PMUGRF_SOC_CON0 0x0180
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#define CCI_FORCE_WAKEUP WMSK_BIT(8)
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#define EXTERNAL_32K WMSK_BIT(0)
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#define PLL_PD_HW 0xff
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#define IOMUX_CLK_32K 0x00030002
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#define NOC_AUTO_ENABLE 0x3fffffff
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#define SAVE_QOS(array, NAME) \
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RK3399_CPU_AXI_SAVE_QOS(array, CPU_AXI_##NAME##_QOS_BASE)
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#define RESTORE_QOS(array, NAME) \
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RK3399_CPU_AXI_RESTORE_QOS(array, CPU_AXI_##NAME##_QOS_BASE)
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#define RK3399_CPU_AXI_SAVE_QOS(array, base) do { \
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array[0] = mmio_read_32(base + CPU_AXI_QOS_ID_COREID); \
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array[1] = mmio_read_32(base + CPU_AXI_QOS_REVISIONID); \
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array[2] = mmio_read_32(base + CPU_AXI_QOS_PRIORITY); \
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array[3] = mmio_read_32(base + CPU_AXI_QOS_MODE); \
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array[4] = mmio_read_32(base + CPU_AXI_QOS_BANDWIDTH); \
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array[5] = mmio_read_32(base + CPU_AXI_QOS_SATURATION); \
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array[6] = mmio_read_32(base + CPU_AXI_QOS_EXTCONTROL); \
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} while (0)
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#define RK3399_CPU_AXI_RESTORE_QOS(array, base) do { \
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mmio_write_32(base + CPU_AXI_QOS_ID_COREID, array[0]); \
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mmio_write_32(base + CPU_AXI_QOS_REVISIONID, array[1]); \
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mmio_write_32(base + CPU_AXI_QOS_PRIORITY, array[2]); \
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mmio_write_32(base + CPU_AXI_QOS_MODE, array[3]); \
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mmio_write_32(base + CPU_AXI_QOS_BANDWIDTH, array[4]); \
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mmio_write_32(base + CPU_AXI_QOS_SATURATION, array[5]); \
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mmio_write_32(base + CPU_AXI_QOS_EXTCONTROL, array[6]); \
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} while (0)
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struct pmu_slpdata_s {
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uint32_t cci_m0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t cci_m1_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t dmac0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t dmac1_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t dcf_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t crypto0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t crypto1_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t pmu_cm0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t peri_cm1_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t gic_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t sdmmc_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t gmac_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t emmc_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t usb_otg0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t usb_otg1_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t usb_host0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t usb_host1_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t gpu_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t video_m0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t video_m1_r_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t video_m1_w_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t rga_r_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t rga_w_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t vop_big_r[CPU_AXI_QOS_NUM_REGS];
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uint32_t vop_big_w[CPU_AXI_QOS_NUM_REGS];
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uint32_t vop_little[CPU_AXI_QOS_NUM_REGS];
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uint32_t iep_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t isp1_m0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t isp1_m1_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t isp0_m0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t isp0_m1_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t hdcp_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t perihp_nsp_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t perilp_nsp_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t perilpslv_nsp_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t sdio_qos[CPU_AXI_QOS_NUM_REGS];
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};
|
||||
|
||||
extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT];
|
||||
|
||||
extern void sram_func_set_ddrctl_pll(uint32_t pll_src);
|
||||
void pmu_power_domains_on(void);
|
||||
|
||||
#endif /* PMU_H */
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/* convoluted way to make sure that the define is pasted just the right way */
|
||||
#define INCBIN(file, sym, sec) \
|
||||
__asm__( \
|
||||
".section " sec "\n" \
|
||||
".global " sym "\n" \
|
||||
".type " sym ", %object\n" \
|
||||
".align 4\n" \
|
||||
sym ":\n" \
|
||||
".incbin \"" file "\"\n" \
|
||||
".size " sym ", .-" sym "\n" \
|
||||
".global " sym "_end\n" \
|
||||
sym "_end:\n" \
|
||||
)
|
||||
|
||||
INCBIN(RK3399M0FW, "rk3399m0_bin", ".sram.incbin");
|
||||
INCBIN(RK3399M0PMUFW, "rk3399m0pmu_bin", ".pmusram.incbin");
|
||||
Reference in New Issue
Block a user