GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PMU_H
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#define PMU_H
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#include <pmu_bits.h>
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#include <pmu_regs.h>
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#include <soc.h>
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/* Allocate sp reginon in pmusram */
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#define PSRAM_SP_SIZE 0x80
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#define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE)
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/*****************************************************************************
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* Common define for per soc pmu.h
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*****************************************************************************/
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/* The ways of cores power domain contorlling */
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enum cores_pm_ctr_mode {
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core_pwr_pd = 0,
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core_pwr_wfi = 1,
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core_pwr_wfi_int = 2
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};
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/*****************************************************************************
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* pmu con,reg
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*****************************************************************************/
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#define PMU_WKUP_CFG(n) ((n) * 4)
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#define PMU_CORE_PM_CON(cpu) (0xc0 + (cpu * 4))
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/* the shift of bits for cores status */
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enum pmu_core_pwrst_shift {
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clstl_cpu_wfe = 2,
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clstl_cpu_wfi = 6,
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clstb_cpu_wfe = 12,
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clstb_cpu_wfi = 16
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};
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#define CKECK_WFE_MSK 0x1
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#define CKECK_WFI_MSK 0x10
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#define CKECK_WFEI_MSK 0x11
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/* Specific features required */
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#define AP_PWROFF 0x0a
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#define GPIO0A0_SMT_ENABLE BITS_WITH_WMASK(1, 3, 0)
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#define GPIO1A6_IOMUX BITS_WITH_WMASK(0, 3, 12)
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#define TSADC_INT_PIN 38
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#define CORES_PM_DISABLE 0x0
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#define PD_CTR_LOOP 10000
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#define CHK_CPU_LOOP 500
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#define MAX_WAIT_COUNT 1000
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#define GRF_SOC_CON4 0x0e210
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#define PMUGRF_GPIO0A_SMT 0x0120
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#define PMUGRF_SOC_CON0 0x0180
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#define CCI_FORCE_WAKEUP WMSK_BIT(8)
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#define EXTERNAL_32K WMSK_BIT(0)
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#define PLL_PD_HW 0xff
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#define IOMUX_CLK_32K 0x00030002
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#define NOC_AUTO_ENABLE 0x3fffffff
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#define SAVE_QOS(array, NAME) \
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RK3399_CPU_AXI_SAVE_QOS(array, CPU_AXI_##NAME##_QOS_BASE)
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#define RESTORE_QOS(array, NAME) \
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RK3399_CPU_AXI_RESTORE_QOS(array, CPU_AXI_##NAME##_QOS_BASE)
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#define RK3399_CPU_AXI_SAVE_QOS(array, base) do { \
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array[0] = mmio_read_32(base + CPU_AXI_QOS_ID_COREID); \
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array[1] = mmio_read_32(base + CPU_AXI_QOS_REVISIONID); \
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array[2] = mmio_read_32(base + CPU_AXI_QOS_PRIORITY); \
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array[3] = mmio_read_32(base + CPU_AXI_QOS_MODE); \
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array[4] = mmio_read_32(base + CPU_AXI_QOS_BANDWIDTH); \
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array[5] = mmio_read_32(base + CPU_AXI_QOS_SATURATION); \
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array[6] = mmio_read_32(base + CPU_AXI_QOS_EXTCONTROL); \
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} while (0)
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#define RK3399_CPU_AXI_RESTORE_QOS(array, base) do { \
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mmio_write_32(base + CPU_AXI_QOS_ID_COREID, array[0]); \
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mmio_write_32(base + CPU_AXI_QOS_REVISIONID, array[1]); \
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mmio_write_32(base + CPU_AXI_QOS_PRIORITY, array[2]); \
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mmio_write_32(base + CPU_AXI_QOS_MODE, array[3]); \
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mmio_write_32(base + CPU_AXI_QOS_BANDWIDTH, array[4]); \
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mmio_write_32(base + CPU_AXI_QOS_SATURATION, array[5]); \
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mmio_write_32(base + CPU_AXI_QOS_EXTCONTROL, array[6]); \
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} while (0)
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struct pmu_slpdata_s {
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uint32_t cci_m0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t cci_m1_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t dmac0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t dmac1_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t dcf_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t crypto0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t crypto1_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t pmu_cm0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t peri_cm1_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t gic_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t sdmmc_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t gmac_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t emmc_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t usb_otg0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t usb_otg1_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t usb_host0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t usb_host1_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t gpu_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t video_m0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t video_m1_r_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t video_m1_w_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t rga_r_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t rga_w_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t vop_big_r[CPU_AXI_QOS_NUM_REGS];
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uint32_t vop_big_w[CPU_AXI_QOS_NUM_REGS];
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uint32_t vop_little[CPU_AXI_QOS_NUM_REGS];
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uint32_t iep_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t isp1_m0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t isp1_m1_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t isp0_m0_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t isp0_m1_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t hdcp_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t perihp_nsp_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t perilp_nsp_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t perilpslv_nsp_qos[CPU_AXI_QOS_NUM_REGS];
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uint32_t sdio_qos[CPU_AXI_QOS_NUM_REGS];
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};
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extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT];
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extern void sram_func_set_ddrctl_pll(uint32_t pll_src);
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void pmu_power_domains_on(void);
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#endif /* PMU_H */
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