GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <dfs.h>
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#include <dram.h>
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#include <m0_ctl.h>
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#include <plat_private.h>
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#include <pmu.h>
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#include <rk3399_def.h>
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#include <secure.h>
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#include <soc.h>
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/* Table of regions to map using the MMU. */
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const mmap_region_t plat_rk_mmap[] = {
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MAP_REGION_FLAT(DEV_RNG0_BASE, DEV_RNG0_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE),
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{ 0 }
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};
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/* The RockChip power domain tree descriptor */
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const unsigned char rockchip_power_domain_tree_desc[] = {
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/* No of root nodes */
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PLATFORM_SYSTEM_COUNT,
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/* No of children for the root node */
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PLATFORM_CLUSTER_COUNT,
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/* No of children for the first cluster node */
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PLATFORM_CLUSTER0_CORE_COUNT,
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/* No of children for the second cluster node */
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PLATFORM_CLUSTER1_CORE_COUNT
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};
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/* sleep data for pll suspend */
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static struct deepsleep_data_s slp_data;
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/* sleep data that needs to be accessed from pmusram */
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__pmusramdata struct pmu_sleep_data pmu_slp_data;
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static void set_pll_slow_mode(uint32_t pll_id)
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{
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if (pll_id == PPLL_ID)
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mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE);
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else
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mmio_write_32((CRU_BASE +
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CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE);
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}
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static void set_pll_normal_mode(uint32_t pll_id)
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{
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if (pll_id == PPLL_ID)
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mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE);
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else
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mmio_write_32(CRU_BASE +
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CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE);
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}
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static void set_pll_bypass(uint32_t pll_id)
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{
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if (pll_id == PPLL_ID)
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mmio_write_32(PMUCRU_BASE +
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PMUCRU_PPLL_CON(3), PLL_BYPASS_MODE);
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else
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mmio_write_32(CRU_BASE +
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CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE);
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}
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static void _pll_suspend(uint32_t pll_id)
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{
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set_pll_slow_mode(pll_id);
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set_pll_bypass(pll_id);
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}
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/**
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* disable_dvfs_plls - To suspend the specific PLLs
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*
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* When we close the center logic, the DPLL will be closed,
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* so we need to keep the ABPLL and switch to it to supply
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* clock for DDR during suspend, then we should not close
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* the ABPLL and exclude ABPLL_ID.
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*/
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void disable_dvfs_plls(void)
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{
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_pll_suspend(CPLL_ID);
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_pll_suspend(NPLL_ID);
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_pll_suspend(VPLL_ID);
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_pll_suspend(GPLL_ID);
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_pll_suspend(ALPLL_ID);
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}
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/**
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* disable_nodvfs_plls - To suspend the PPLL
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*/
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void disable_nodvfs_plls(void)
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{
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_pll_suspend(PPLL_ID);
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}
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/**
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* restore_pll - Copy PLL settings from memory to a PLL.
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*
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* This will copy PLL settings from an array in memory to the memory mapped
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* registers for a PLL.
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*
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* Note that: above the PLL exclude PPLL.
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*
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* pll_id: One of the values from enum plls_id
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* src: Pointer to the array of values to restore from
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*/
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static void restore_pll(int pll_id, uint32_t *src)
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{
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/* Nice to have PLL off while configuring */
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mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE);
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mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK);
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mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK);
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mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]);
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mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK);
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mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK);
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/* Do PLL_CON3 since that will enable things */
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mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK);
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/* Wait for PLL lock done */
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while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) &
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0x80000000) == 0x0)
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;
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}
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/**
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* save_pll - Copy PLL settings a PLL to memory
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*
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* This will copy PLL settings from the memory mapped registers for a PLL to
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* an array in memory.
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*
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* Note that: above the PLL exclude PPLL.
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*
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* pll_id: One of the values from enum plls_id
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* src: Pointer to the array of values to save to.
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*/
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static void save_pll(uint32_t *dst, int pll_id)
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{
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int i;
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for (i = 0; i < PLL_CON_COUNT; i++)
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dst[i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i));
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}
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/**
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* prepare_abpll_for_ddrctrl - Copy DPLL settings to ABPLL
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*
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* This will copy DPLL settings from the memory mapped registers for a PLL to
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* an array in memory.
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*/
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void prepare_abpll_for_ddrctrl(void)
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{
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save_pll(slp_data.plls_con[ABPLL_ID], ABPLL_ID);
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save_pll(slp_data.plls_con[DPLL_ID], DPLL_ID);
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restore_pll(ABPLL_ID, slp_data.plls_con[DPLL_ID]);
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}
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void restore_abpll(void)
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{
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restore_pll(ABPLL_ID, slp_data.plls_con[ABPLL_ID]);
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}
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void clk_gate_con_save(void)
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{
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uint32_t i = 0;
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for (i = 0; i < PMUCRU_GATE_COUNT; i++)
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slp_data.pmucru_gate_con[i] =
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mmio_read_32(PMUCRU_BASE + PMUCRU_GATE_CON(i));
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for (i = 0; i < CRU_GATE_COUNT; i++)
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slp_data.cru_gate_con[i] =
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mmio_read_32(CRU_BASE + CRU_GATE_CON(i));
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}
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void clk_gate_con_disable(void)
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{
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uint32_t i;
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for (i = 0; i < PMUCRU_GATE_COUNT; i++)
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mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), REG_SOC_WMSK);
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for (i = 0; i < CRU_GATE_COUNT; i++)
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mmio_write_32(CRU_BASE + CRU_GATE_CON(i), REG_SOC_WMSK);
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}
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void clk_gate_con_restore(void)
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{
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uint32_t i;
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for (i = 0; i < PMUCRU_GATE_COUNT; i++)
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mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i),
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REG_SOC_WMSK | slp_data.pmucru_gate_con[i]);
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for (i = 0; i < CRU_GATE_COUNT; i++)
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mmio_write_32(CRU_BASE + CRU_GATE_CON(i),
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REG_SOC_WMSK | slp_data.cru_gate_con[i]);
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}
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static void set_plls_nobypass(uint32_t pll_id)
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{
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if (pll_id == PPLL_ID)
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mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3),
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PLL_NO_BYPASS_MODE);
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else
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mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3),
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PLL_NO_BYPASS_MODE);
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}
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static void _pll_resume(uint32_t pll_id)
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{
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set_plls_nobypass(pll_id);
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set_pll_normal_mode(pll_id);
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}
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void set_pmu_rsthold(void)
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{
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uint32_t rstnhold_cofig0;
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uint32_t rstnhold_cofig1;
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pmu_slp_data.pmucru_rstnhold_con0 = mmio_read_32(PMUCRU_BASE +
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PMUCRU_RSTNHOLD_CON0);
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pmu_slp_data.pmucru_rstnhold_con1 = mmio_read_32(PMUCRU_BASE +
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PMUCRU_RSTNHOLD_CON1);
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rstnhold_cofig0 = BIT_WITH_WMSK(PRESETN_NOC_PMU_HOLD) |
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BIT_WITH_WMSK(PRESETN_INTMEM_PMU_HOLD) |
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BIT_WITH_WMSK(HRESETN_CM0S_PMU_HOLD) |
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BIT_WITH_WMSK(HRESETN_CM0S_NOC_PMU_HOLD) |
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BIT_WITH_WMSK(DRESETN_CM0S_PMU_HOLD) |
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BIT_WITH_WMSK(POESETN_CM0S_PMU_HOLD) |
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BIT_WITH_WMSK(PRESETN_TIMER_PMU_0_1_HOLD) |
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BIT_WITH_WMSK(RESETN_TIMER_PMU_0_HOLD) |
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BIT_WITH_WMSK(RESETN_TIMER_PMU_1_HOLD) |
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BIT_WITH_WMSK(PRESETN_UART_M0_PMU_HOLD) |
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BIT_WITH_WMSK(RESETN_UART_M0_PMU_HOLD) |
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BIT_WITH_WMSK(PRESETN_WDT_PMU_HOLD);
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rstnhold_cofig1 = BIT_WITH_WMSK(PRESETN_RKPWM_PMU_HOLD) |
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BIT_WITH_WMSK(PRESETN_PMUGRF_HOLD) |
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BIT_WITH_WMSK(PRESETN_SGRF_HOLD) |
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BIT_WITH_WMSK(PRESETN_GPIO0_HOLD) |
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BIT_WITH_WMSK(PRESETN_GPIO1_HOLD) |
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BIT_WITH_WMSK(PRESETN_CRU_PMU_HOLD) |
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BIT_WITH_WMSK(PRESETN_PVTM_PMU_HOLD);
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mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON0, rstnhold_cofig0);
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mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON1, rstnhold_cofig1);
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}
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void pmu_sgrf_rst_hld(void)
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{
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mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1),
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CRU_PMU_SGRF_RST_HOLD);
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}
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/*
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* When system reset in running state, we want the cpus to be reboot
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* from maskrom (system reboot),
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* the pmusgrf reset-hold bits needs to be released.
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* When system wake up from system deep suspend, some soc will be reset
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* when waked up,
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* we want the bootcpu to be reboot from pmusram,
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* the pmusgrf reset-hold bits needs to be held.
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*/
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__pmusramfunc void pmu_sgrf_rst_hld_release(void)
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{
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mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1),
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CRU_PMU_SGRF_RST_RLS);
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}
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__pmusramfunc void restore_pmu_rsthold(void)
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{
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mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON0,
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pmu_slp_data.pmucru_rstnhold_con0 | REG_SOC_WMSK);
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mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON1,
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pmu_slp_data.pmucru_rstnhold_con1 | REG_SOC_WMSK);
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}
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/**
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* enable_dvfs_plls - To resume the specific PLLs
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*
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* Please see the comment at the disable_dvfs_plls()
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* we don't suspend the ABPLL, so don't need resume
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* it too.
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*/
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void enable_dvfs_plls(void)
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{
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_pll_resume(ALPLL_ID);
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_pll_resume(GPLL_ID);
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_pll_resume(VPLL_ID);
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_pll_resume(NPLL_ID);
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_pll_resume(CPLL_ID);
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}
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/**
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* enable_nodvfs_plls - To resume the PPLL
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*/
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void enable_nodvfs_plls(void)
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{
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_pll_resume(PPLL_ID);
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}
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void soc_global_soft_reset_init(void)
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{
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mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1),
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CRU_PMU_SGRF_RST_RLS);
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mmio_clrbits_32(CRU_BASE + CRU_GLB_RST_CON,
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CRU_PMU_WDTRST_MSK | CRU_PMU_FIRST_SFTRST_MSK);
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}
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void __dead2 soc_global_soft_reset(void)
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{
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pmu_power_domains_on();
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set_pll_slow_mode(VPLL_ID);
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set_pll_slow_mode(NPLL_ID);
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set_pll_slow_mode(GPLL_ID);
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set_pll_slow_mode(CPLL_ID);
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set_pll_slow_mode(PPLL_ID);
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set_pll_slow_mode(ABPLL_ID);
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set_pll_slow_mode(ALPLL_ID);
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dsb();
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mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL);
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/*
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* Maybe the HW needs some times to reset the system,
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* so we do not hope the core to excute valid codes.
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*/
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while (1)
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;
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}
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void plat_rockchip_soc_init(void)
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{
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secure_timer_init();
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secure_sgrf_init();
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secure_sgrf_ddr_rgn_init();
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soc_global_soft_reset_init();
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plat_rockchip_gpio_init();
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m0_init();
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dram_init();
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dram_dfs_init();
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}
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+289
@@ -0,0 +1,289 @@
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/*
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* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
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*
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||||
* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOC_H
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#define SOC_H
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#include <lib/utils.h>
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#define GLB_SRST_FST_CFG_VAL 0xfdb9
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#define GLB_SRST_SND_CFG_VAL 0xeca8
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#define PMUCRU_PPLL_CON(n) ((n) * 4)
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#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4)
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#define PLL_MODE_MSK 0x03
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#define PLL_MODE_SHIFT 0x08
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#define PLL_BYPASS_MSK 0x01
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#define PLL_BYPASS_SHIFT 0x01
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#define PLL_PWRDN_MSK 0x01
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#define PLL_PWRDN_SHIFT 0x0
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#define PLL_BYPASS BIT(1)
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#define PLL_PWRDN BIT(0)
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#define NO_PLL_BYPASS (0x00)
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#define NO_PLL_PWRDN (0x00)
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#define FBDIV(n) ((0xfff << 16) | n)
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#define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12))
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#define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << 8))
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#define REFDIV(n) ((0x3F << 16) | n)
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#define PLL_LOCK(n) ((n >> 31) & 0x1)
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#define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\
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PLL_MODE_MSK, PLL_MODE_SHIFT)
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#define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\
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PLL_MODE_MSK, PLL_MODE_SHIFT)
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#define PLL_BYPASS_MODE BIT_WITH_WMSK(PLL_BYPASS_SHIFT)
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#define PLL_NO_BYPASS_MODE WMSK_BIT(PLL_BYPASS_SHIFT)
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#define PLL_CON_COUNT 0x06
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#define CRU_CLKSEL_COUNT 108
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#define CRU_CLKSEL_CON(n) (0x100 + (n) * 4)
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#define PMUCRU_CLKSEL_CONUT 0x06
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#define PMUCRU_CLKSEL_OFFSET 0x080
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#define REG_SIZE 0x04
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#define REG_SOC_WMSK 0xffff0000
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#define CLK_GATE_MASK 0x01
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#define PMUCRU_GATE_COUNT 0x03
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#define CRU_GATE_COUNT 0x23
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#define PMUCRU_GATE_CON(n) (0x100 + (n) * 4)
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#define CRU_GATE_CON(n) (0x300 + (n) * 4)
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||||
#define PMUCRU_RSTNHOLD_CON0 0x120
|
||||
enum {
|
||||
PRESETN_NOC_PMU_HOLD = 1,
|
||||
PRESETN_INTMEM_PMU_HOLD,
|
||||
HRESETN_CM0S_PMU_HOLD,
|
||||
HRESETN_CM0S_NOC_PMU_HOLD,
|
||||
DRESETN_CM0S_PMU_HOLD,
|
||||
POESETN_CM0S_PMU_HOLD,
|
||||
PRESETN_SPI3_HOLD,
|
||||
RESETN_SPI3_HOLD,
|
||||
PRESETN_TIMER_PMU_0_1_HOLD,
|
||||
RESETN_TIMER_PMU_0_HOLD,
|
||||
RESETN_TIMER_PMU_1_HOLD,
|
||||
PRESETN_UART_M0_PMU_HOLD,
|
||||
RESETN_UART_M0_PMU_HOLD,
|
||||
PRESETN_WDT_PMU_HOLD
|
||||
};
|
||||
|
||||
#define PMUCRU_RSTNHOLD_CON1 0x124
|
||||
enum {
|
||||
PRESETN_I2C0_HOLD,
|
||||
PRESETN_I2C4_HOLD,
|
||||
PRESETN_I2C8_HOLD,
|
||||
PRESETN_MAILBOX_PMU_HOLD,
|
||||
PRESETN_RKPWM_PMU_HOLD,
|
||||
PRESETN_PMUGRF_HOLD,
|
||||
PRESETN_SGRF_HOLD,
|
||||
PRESETN_GPIO0_HOLD,
|
||||
PRESETN_GPIO1_HOLD,
|
||||
PRESETN_CRU_PMU_HOLD,
|
||||
PRESETN_INTR_ARB_HOLD,
|
||||
PRESETN_PVTM_PMU_HOLD,
|
||||
RESETN_I2C0_HOLD,
|
||||
RESETN_I2C4_HOLD,
|
||||
RESETN_I2C8_HOLD
|
||||
};
|
||||
|
||||
enum plls_id {
|
||||
ALPLL_ID = 0,
|
||||
ABPLL_ID,
|
||||
DPLL_ID,
|
||||
CPLL_ID,
|
||||
GPLL_ID,
|
||||
NPLL_ID,
|
||||
VPLL_ID,
|
||||
PPLL_ID,
|
||||
END_PLL_ID,
|
||||
};
|
||||
|
||||
#define CLST_L_CPUS_MSK (0xf)
|
||||
#define CLST_B_CPUS_MSK (0x3)
|
||||
|
||||
enum pll_work_mode {
|
||||
SLOW_MODE = 0x00,
|
||||
NORMAL_MODE = 0x01,
|
||||
DEEP_SLOW_MODE = 0x02,
|
||||
};
|
||||
|
||||
enum glb_sft_reset {
|
||||
PMU_RST_BY_FIRST_SFT,
|
||||
PMU_RST_BY_SECOND_SFT = BIT(2),
|
||||
PMU_RST_NOT_BY_SFT = BIT(3),
|
||||
};
|
||||
|
||||
struct pll_div {
|
||||
uint32_t mhz;
|
||||
uint32_t refdiv;
|
||||
uint32_t fbdiv;
|
||||
uint32_t postdiv1;
|
||||
uint32_t postdiv2;
|
||||
uint32_t frac;
|
||||
uint32_t freq;
|
||||
};
|
||||
|
||||
struct deepsleep_data_s {
|
||||
uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT];
|
||||
uint32_t cru_gate_con[CRU_GATE_COUNT];
|
||||
uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT];
|
||||
};
|
||||
|
||||
struct pmu_sleep_data {
|
||||
uint32_t pmucru_rstnhold_con0;
|
||||
uint32_t pmucru_rstnhold_con1;
|
||||
};
|
||||
|
||||
/**************************************************
|
||||
* pmugrf reg, offset
|
||||
**************************************************/
|
||||
#define PMUGRF_OSREG(n) (0x300 + (n) * 4)
|
||||
#define PMUGRF_GPIO0A_P 0x040
|
||||
#define PMUGRF_GPIO1A_P 0x050
|
||||
|
||||
/**************************************************
|
||||
* DCF reg, offset
|
||||
**************************************************/
|
||||
#define DCF_DCF_CTRL 0x0
|
||||
#define DCF_DCF_ADDR 0x8
|
||||
#define DCF_DCF_ISR 0xc
|
||||
#define DCF_DCF_TOSET 0x14
|
||||
#define DCF_DCF_TOCMD 0x18
|
||||
#define DCF_DCF_CMD_CFG 0x1c
|
||||
|
||||
/* DCF_DCF_ISR */
|
||||
#define DCF_TIMEOUT (1 << 2)
|
||||
#define DCF_ERR (1 << 1)
|
||||
#define DCF_DONE (1 << 0)
|
||||
|
||||
/* DCF_DCF_CTRL */
|
||||
#define DCF_VOP_HW_EN (1 << 2)
|
||||
#define DCF_STOP (1 << 1)
|
||||
#define DCF_START (1 << 0)
|
||||
|
||||
#define CYCL_24M_CNT_US(us) (24 * us)
|
||||
#define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000))
|
||||
#define CYCL_32K_CNT_MS(ms) (ms * 32)
|
||||
|
||||
/**************************************************
|
||||
* cru reg, offset
|
||||
**************************************************/
|
||||
#define CRU_SOFTRST_CON(n) (0x400 + (n) * 4)
|
||||
|
||||
#define CRU_DMAC0_RST BIT_WITH_WMSK(3)
|
||||
/* reset release*/
|
||||
#define CRU_DMAC0_RST_RLS WMSK_BIT(3)
|
||||
|
||||
#define CRU_DMAC1_RST BIT_WITH_WMSK(4)
|
||||
/* reset release*/
|
||||
#define CRU_DMAC1_RST_RLS WMSK_BIT(4)
|
||||
|
||||
#define CRU_GLB_RST_CON 0x0510
|
||||
#define CRU_GLB_SRST_FST 0x0500
|
||||
#define CRU_GLB_SRST_SND 0x0504
|
||||
|
||||
#define CRU_CLKGATE_CON(n) (0x300 + n * 4)
|
||||
#define PCLK_GPIO2_GATE_SHIFT 3
|
||||
#define PCLK_GPIO3_GATE_SHIFT 4
|
||||
#define PCLK_GPIO4_GATE_SHIFT 5
|
||||
|
||||
/**************************************************
|
||||
* pmu cru reg, offset
|
||||
**************************************************/
|
||||
#define CRU_PMU_RSTHOLD_CON(n) (0x120 + n * 4)
|
||||
/* reset hold*/
|
||||
#define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6)
|
||||
/* reset hold release*/
|
||||
#define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6)
|
||||
|
||||
#define CRU_PMU_WDTRST_MSK (0x1 << 4)
|
||||
#define CRU_PMU_WDTRST_EN 0x0
|
||||
|
||||
#define CRU_PMU_FIRST_SFTRST_MSK (0x3 << 2)
|
||||
#define CRU_PMU_FIRST_SFTRST_EN 0x0
|
||||
|
||||
#define CRU_PMU_CLKGATE_CON(n) (0x100 + n * 4)
|
||||
#define PCLK_GPIO0_GATE_SHIFT 3
|
||||
#define PCLK_GPIO1_GATE_SHIFT 4
|
||||
|
||||
#define CPU_BOOT_ADDR_WMASK 0xffff0000
|
||||
#define CPU_BOOT_ADDR_ALIGN 16
|
||||
|
||||
#define GRF_IOMUX_2BIT_MASK 0x3
|
||||
#define GRF_IOMUX_GPIO 0x0
|
||||
|
||||
#define GRF_GPIO4C2_IOMUX_SHIFT 4
|
||||
#define GRF_GPIO4C2_IOMUX_PWM 0x1
|
||||
#define GRF_GPIO4C6_IOMUX_SHIFT 12
|
||||
#define GRF_GPIO4C6_IOMUX_PWM 0x1
|
||||
|
||||
#define PWM_CNT(n) (0x0000 + 0x10 * (n))
|
||||
#define PWM_PERIOD_HPR(n) (0x0004 + 0x10 * (n))
|
||||
#define PWM_DUTY_LPR(n) (0x0008 + 0x10 * (n))
|
||||
#define PWM_CTRL(n) (0x000c + 0x10 * (n))
|
||||
|
||||
#define PWM_DISABLE (0 << 0)
|
||||
#define PWM_ENABLE (1 << 0)
|
||||
|
||||
/* grf reg offset */
|
||||
#define GRF_USBPHY0_CTRL0 0x4480
|
||||
#define GRF_USBPHY0_CTRL2 0x4488
|
||||
#define GRF_USBPHY0_CTRL3 0x448c
|
||||
#define GRF_USBPHY0_CTRL12 0x44b0
|
||||
#define GRF_USBPHY0_CTRL13 0x44b4
|
||||
#define GRF_USBPHY0_CTRL15 0x44bc
|
||||
#define GRF_USBPHY0_CTRL16 0x44c0
|
||||
|
||||
#define GRF_USBPHY1_CTRL0 0x4500
|
||||
#define GRF_USBPHY1_CTRL2 0x4508
|
||||
#define GRF_USBPHY1_CTRL3 0x450c
|
||||
#define GRF_USBPHY1_CTRL12 0x4530
|
||||
#define GRF_USBPHY1_CTRL13 0x4534
|
||||
#define GRF_USBPHY1_CTRL15 0x453c
|
||||
#define GRF_USBPHY1_CTRL16 0x4540
|
||||
|
||||
#define GRF_GPIO2A_IOMUX 0xe000
|
||||
#define GRF_GPIO2A_P 0xe040
|
||||
#define GRF_GPIO3A_P 0xe050
|
||||
#define GRF_GPIO4A_P 0xe060
|
||||
#define GRF_GPIO2D_HE 0xe18c
|
||||
#define GRF_DDRC0_CON0 0xe380
|
||||
#define GRF_DDRC0_CON1 0xe384
|
||||
#define GRF_DDRC1_CON0 0xe388
|
||||
#define GRF_DDRC1_CON1 0xe38c
|
||||
#define GRF_SOC_CON_BASE 0xe200
|
||||
#define GRF_SOC_CON(n) (GRF_SOC_CON_BASE + (n) * 4)
|
||||
#define GRF_IO_VSEL 0xe640
|
||||
|
||||
#define CRU_CLKSEL_CON0 0x0100
|
||||
#define CRU_CLKSEL_CON6 0x0118
|
||||
#define CRU_SDIO0_CON1 0x058c
|
||||
#define PMUCRU_CLKSEL_CON0 0x0080
|
||||
#define PMUCRU_CLKGATE_CON2 0x0108
|
||||
#define PMUCRU_SOFTRST_CON0 0x0110
|
||||
#define PMUCRU_GATEDIS_CON0 0x0130
|
||||
#define PMUCRU_SOFTRST_CON(n) (PMUCRU_SOFTRST_CON0 + (n) * 4)
|
||||
|
||||
/* export related and operating SoC APIs */
|
||||
void __dead2 soc_global_soft_reset(void);
|
||||
void disable_dvfs_plls(void);
|
||||
void disable_nodvfs_plls(void);
|
||||
void enable_dvfs_plls(void);
|
||||
void enable_nodvfs_plls(void);
|
||||
void prepare_abpll_for_ddrctrl(void);
|
||||
void restore_abpll(void);
|
||||
void clk_gate_con_save(void);
|
||||
void clk_gate_con_disable(void);
|
||||
void clk_gate_con_restore(void);
|
||||
void set_pmu_rsthold(void);
|
||||
void pmu_sgrf_rst_hld(void);
|
||||
__pmusramfunc void pmu_sgrf_rst_hld_release(void);
|
||||
__pmusramfunc void restore_pmu_rsthold(void);
|
||||
#endif /* SOC_H */
|
||||
Reference in New Issue
Block a user