GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/arm/pl011.h>
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#include <lib/mmio.h>
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#include <sq_common.h>
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static console_t console;
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_START__, SPM_SHIM_EXCEPTIONS_START);
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IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END);
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IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_LMA__, SPM_SHIM_EXCEPTIONS_LMA);
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unsigned int plat_get_syscnt_freq2(void)
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{
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unsigned int counter_base_frequency;
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/* Read the frequency from Frequency modes table */
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counter_base_frequency = mmio_read_32(SQ_SYS_CNTCTL_BASE + CNTFID_OFF);
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/* The first entry of the frequency modes table must not be 0 */
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if (counter_base_frequency == 0)
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panic();
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return counter_base_frequency;
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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assert(sec_state_is_valid(type));
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return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info;
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}
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#if !RESET_TO_BL31
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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void *from_bl2 = (void *) arg0;
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bl_params_node_t *bl_params = ((bl_params_t *) from_bl2)->head;
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/* Initialize the console to provide early debug support */
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(void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE,
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PLAT_SQ_BOOT_UART_CLK_IN_HZ,
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SQ_CONSOLE_BAUDRATE, &console);
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console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
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/* Initialize power controller before setting up topology */
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plat_sq_pwrc_setup();
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while (bl_params) {
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if (bl_params->image_id == BL32_IMAGE_ID)
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bl32_image_ep_info = *bl_params->ep_info;
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if (bl_params->image_id == BL33_IMAGE_ID)
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bl33_image_ep_info = *bl_params->ep_info;
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bl_params = bl_params->next_params_info;
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}
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}
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#else
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/*******************************************************************************
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* Gets SPSR for BL32 entry
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******************************************************************************/
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uint32_t sq_get_spsr_for_bl32_entry(void)
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{
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL32 image.
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*/
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return 0;
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}
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/*******************************************************************************
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* Gets SPSR for BL33 entry
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******************************************************************************/
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uint32_t sq_get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned int mode;
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uint32_t spsr;
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/* Figure out what mode we enter the non-secure world in */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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/* Initialize the console to provide early debug support */
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(void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE,
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PLAT_SQ_BOOT_UART_CLK_IN_HZ,
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SQ_CONSOLE_BAUDRATE, &console);
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console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
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/* There are no parameters from BL2 if BL31 is a reset vector */
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assert(arg0 == 0U);
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assert(arg1 == 0U);
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/* Initialize power controller before setting up topology */
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plat_sq_pwrc_setup();
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#ifdef SPD_opteed
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struct draminfo di = {0};
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sq_scp_get_draminfo(&di);
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/*
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* Check if OP-TEE has been loaded in Secure RAM allocated
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* from DRAM1 region
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*/
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if ((di.base1 + di.size1) <= BL32_BASE) {
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NOTICE("OP-TEE has been loaded by SCP firmware\n");
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/* Populate entry point information for BL32 */
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SET_PARAM_HEAD(&bl32_image_ep_info,
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PARAM_EP,
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VERSION_1,
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0);
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SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
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bl32_image_ep_info.pc = BL32_BASE;
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bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry();
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} else {
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NOTICE("OP-TEE has not been loaded by SCP firmware\n");
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}
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#endif /* SPD_opteed */
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/* Populate entry point information for BL33 */
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SET_PARAM_HEAD(&bl33_image_ep_info,
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PARAM_EP,
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VERSION_1,
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0);
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/*
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* Tell BL31 where the non-trusted software image
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* is located and the entry state information
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*/
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bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
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bl33_image_ep_info.spsr = sq_get_spsr_for_bl33_entry();
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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}
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#endif
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static void sq_configure_sys_timer(void)
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{
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unsigned int reg_val;
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unsigned int freq_val = plat_get_syscnt_freq2();
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reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
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reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
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reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
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mmio_write_32(SQ_SYS_TIMCTL_BASE +
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CNTACR_BASE(PLAT_SQ_NSTIMER_FRAME_ID), reg_val);
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reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_SQ_NSTIMER_FRAME_ID));
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mmio_write_32(SQ_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
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/* Initialize CNTFRQ register in CNTCTLBase frame */
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mmio_write_32(SQ_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val);
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/*
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* Initialize CNTFRQ register in Non-secure CNTBase frame.
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* This is required for SynQuacer, because it does not
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* follow ARM ARM in that the value updated in CNTFRQ is not
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* reflected in CNTBASEN_CNTFRQ. Hence update the value manually.
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*/
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mmio_write_32(SQ_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val);
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}
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void bl31_platform_setup(void)
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{
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/* Initialize the CCN interconnect */
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plat_sq_interconnect_init();
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plat_sq_interconnect_enter_coherency();
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/* Initialize the GIC driver, cpu and distributor interfaces */
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sq_gic_driver_init();
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sq_gic_init();
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/* Enable and initialize the System level generic timer */
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mmio_write_32(SQ_SYS_CNTCTL_BASE + CNTCR_OFF,
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CNTCR_FCREQ(0U) | CNTCR_EN);
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/* Allow access to the System counter timer module */
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sq_configure_sys_timer();
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}
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void bl31_plat_runtime_setup(void)
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{
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struct draminfo *di = (struct draminfo *)(unsigned long)DRAMINFO_BASE;
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sq_scp_get_draminfo(di);
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}
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void bl31_plat_arch_setup(void)
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{
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static const mmap_region_t secure_partition_mmap[] = {
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#if SPM_MM
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MAP_REGION_FLAT(PLAT_SPM_BUF_BASE,
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PLAT_SPM_BUF_SIZE,
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MT_RW_DATA | MT_SECURE),
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MAP_REGION_FLAT(PLAT_SQ_SP_PRIV_BASE,
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PLAT_SQ_SP_PRIV_SIZE,
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MT_RW_DATA | MT_SECURE),
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#endif
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#if !RESET_TO_BL31
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MAP_REGION_FLAT(BL2_MAILBOX_BASE,
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BL2_MAILBOX_SIZE,
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MT_RW | MT_SECURE),
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#endif
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{0},
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};
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sq_mmap_setup(BL31_BASE, BL31_SIZE, secure_partition_mmap);
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enable_mmu_el3(XLAT_TABLE_NC);
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#if SPM_MM
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memcpy((void *)SPM_SHIM_EXCEPTIONS_START,
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(void *)SPM_SHIM_EXCEPTIONS_LMA,
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(uintptr_t)SPM_SHIM_EXCEPTIONS_END -
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(uintptr_t)SPM_SHIM_EXCEPTIONS_START);
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#endif
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}
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void bl31_plat_enable_mmu(uint32_t flags)
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{
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enable_mmu_el3(flags | XLAT_TABLE_NC);
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}
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