GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/clk.h>
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#include <drivers/delay_timer.h>
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#include <drivers/st/stm32_console.h>
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#include <drivers/st/stm32mp_clkfunc.h>
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#include <drivers/st/stm32mp_reset.h>
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#include <lib/smccc.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <services/arm_arch_svc.h>
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#include <platform_def.h>
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#define HEADER_VERSION_MAJOR_MASK GENMASK(23, 16)
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#define RESET_TIMEOUT_US_1MS 1000U
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static console_t console;
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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return BL33_BASE;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return read_cntfrq_el0();
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}
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static uintptr_t boot_ctx_address;
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static uint16_t boot_itf_selected;
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void stm32mp_save_boot_ctx_address(uintptr_t address)
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{
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boot_api_context_t *boot_context = (boot_api_context_t *)address;
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boot_ctx_address = address;
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boot_itf_selected = boot_context->boot_interface_selected;
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}
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uintptr_t stm32mp_get_boot_ctx_address(void)
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{
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return boot_ctx_address;
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}
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uint16_t stm32mp_get_boot_itf_selected(void)
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{
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return boot_itf_selected;
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}
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uintptr_t stm32mp_ddrctrl_base(void)
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{
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return DDRCTRL_BASE;
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}
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uintptr_t stm32mp_ddrphyc_base(void)
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{
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return DDRPHYC_BASE;
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}
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uintptr_t stm32mp_pwr_base(void)
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{
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return PWR_BASE;
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}
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uintptr_t stm32mp_rcc_base(void)
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{
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return RCC_BASE;
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}
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bool stm32mp_lock_available(void)
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{
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const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT;
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/* The spinlocks are used only when MMU and data cache are enabled */
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return (read_sctlr() & c_m_bits) == c_m_bits;
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}
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int stm32mp_map_ddr_non_cacheable(void)
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{
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return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
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STM32MP_DDR_MAX_SIZE,
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MT_NON_CACHEABLE | MT_RW | MT_SECURE);
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}
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int stm32mp_unmap_ddr(void)
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{
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return mmap_remove_dynamic_region(STM32MP_DDR_BASE,
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STM32MP_DDR_MAX_SIZE);
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}
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int stm32_get_otp_index(const char *otp_name, uint32_t *otp_idx,
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uint32_t *otp_len)
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{
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assert(otp_name != NULL);
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assert(otp_idx != NULL);
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return dt_find_otp_name(otp_name, otp_idx, otp_len);
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}
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int stm32_get_otp_value(const char *otp_name, uint32_t *otp_val)
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{
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uint32_t otp_idx;
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assert(otp_name != NULL);
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assert(otp_val != NULL);
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if (stm32_get_otp_index(otp_name, &otp_idx, NULL) != 0) {
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return -1;
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}
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if (stm32_get_otp_value_from_idx(otp_idx, otp_val) != 0) {
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ERROR("BSEC: %s Read Error\n", otp_name);
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return -1;
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}
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return 0;
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}
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int stm32_get_otp_value_from_idx(const uint32_t otp_idx, uint32_t *otp_val)
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{
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uint32_t ret = BSEC_NOT_SUPPORTED;
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assert(otp_val != NULL);
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#if defined(IMAGE_BL2)
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ret = bsec_shadow_read_otp(otp_val, otp_idx);
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#elif defined(IMAGE_BL32)
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ret = bsec_read_otp(otp_val, otp_idx);
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#else
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#error "Not supported"
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#endif
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if (ret != BSEC_OK) {
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ERROR("BSEC: idx=%u Read Error\n", otp_idx);
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return -1;
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}
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return 0;
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}
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#if defined(IMAGE_BL2)
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static void reset_uart(uint32_t reset)
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{
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int ret;
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ret = stm32mp_reset_assert(reset, RESET_TIMEOUT_US_1MS);
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if (ret != 0) {
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panic();
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}
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udelay(2);
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ret = stm32mp_reset_deassert(reset, RESET_TIMEOUT_US_1MS);
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if (ret != 0) {
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panic();
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}
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mdelay(1);
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}
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#endif
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static void set_console(uintptr_t base, uint32_t clk_rate)
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{
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unsigned int console_flags;
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if (console_stm32_register(base, clk_rate,
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(uint32_t)STM32MP_UART_BAUDRATE, &console) == 0) {
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panic();
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}
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console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH |
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CONSOLE_FLAG_TRANSLATE_CRLF;
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#if !defined(IMAGE_BL2) && defined(DEBUG)
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console_flags |= CONSOLE_FLAG_RUNTIME;
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#endif
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console_set_scope(&console, console_flags);
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}
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int stm32mp_uart_console_setup(void)
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{
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struct dt_node_info dt_uart_info;
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uint32_t clk_rate = 0U;
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int result;
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uint32_t boot_itf __unused;
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uint32_t boot_instance __unused;
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result = dt_get_stdout_uart_info(&dt_uart_info);
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if ((result <= 0) ||
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(dt_uart_info.status == DT_DISABLED)) {
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return -ENODEV;
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}
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#if defined(IMAGE_BL2)
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if ((dt_uart_info.clock < 0) ||
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(dt_uart_info.reset < 0)) {
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return -ENODEV;
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}
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#endif
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#if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
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stm32_get_boot_interface(&boot_itf, &boot_instance);
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if ((boot_itf == BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) &&
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(get_uart_address(boot_instance) == dt_uart_info.base)) {
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return -EACCES;
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}
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#endif
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#if defined(IMAGE_BL2)
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if (dt_set_stdout_pinctrl() != 0) {
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return -ENODEV;
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}
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clk_enable((unsigned long)dt_uart_info.clock);
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reset_uart((uint32_t)dt_uart_info.reset);
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clk_rate = clk_get_rate((unsigned long)dt_uart_info.clock);
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#endif
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set_console(dt_uart_info.base, clk_rate);
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return 0;
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}
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#if STM32MP_EARLY_CONSOLE
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void stm32mp_setup_early_console(void)
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{
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#if defined(IMAGE_BL2) || STM32MP_RECONFIGURE_CONSOLE
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plat_crash_console_init();
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#endif
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set_console(STM32MP_DEBUG_USART_BASE, STM32MP_DEBUG_USART_CLK_FRQ);
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NOTICE("Early console setup\n");
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}
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#endif /* STM32MP_EARLY_CONSOLE */
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/*****************************************************************************
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* plat_is_smccc_feature_available() - This function checks whether SMCCC
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* feature is availabile for platform.
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* @fid: SMCCC function id
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*
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* Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
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* SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
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*****************************************************************************/
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int32_t plat_is_smccc_feature_available(u_register_t fid)
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{
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switch (fid) {
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case SMCCC_ARCH_SOC_ID:
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return SMC_ARCH_CALL_SUCCESS;
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default:
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return SMC_ARCH_CALL_NOT_SUPPORTED;
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}
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}
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/* Get SOC version */
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int32_t plat_get_soc_version(void)
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{
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uint32_t chip_id = stm32mp_get_chip_dev_id();
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uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID);
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return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK));
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}
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/* Get SOC revision */
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int32_t plat_get_soc_revision(void)
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{
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return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK);
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}
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