GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOOT_API_H
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#define BOOT_API_H
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#include <stdint.h>
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#include <stdio.h>
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/*
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* Possible value of boot context field 'auth_status'
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*/
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#if STM32MP13
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/* No authentication done */
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#define BOOT_API_CTX_AUTH_NO 0x7CFDD351U
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/* Authentication done and failed */
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#define BOOT_API_CTX_AUTH_FAILED 0x51330884U
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/* Authentication done and success */
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#define BOOT_API_CTX_AUTH_SUCCESS 0x67E8CAE1U
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#endif
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#if STM32MP15
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/* No authentication done */
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#define BOOT_API_CTX_AUTH_NO 0x0U
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/* Authentication done and failed */
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#define BOOT_API_CTX_AUTH_FAILED 0x1U
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/* Authentication done and succeeded */
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#define BOOT_API_CTX_AUTH_SUCCESS 0x2U
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#endif
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/*
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* Possible value of boot context field 'boot_interface_sel'
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*/
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/* Value of field 'boot_interface_sel' when no boot occurred */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_NO 0x0U
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/* Boot occurred on SD */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD 0x1U
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/* Boot occurred on EMMC */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC 0x2U
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/* Boot occurred on FMC */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC 0x3U
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/* Boot occurred on QSPI NOR */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI 0x4U
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/* Boot occurred on UART */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART 0x5U
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/* Boot occurred on USB */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB 0x6U
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/* Boot occurred on QSPI NAND */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI 0x7U
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/**
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* @brief Possible value of boot context field 'EmmcXferStatus'
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*/
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/*
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* Possible value of boot context field 'emmc_xfer_status'
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*/
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#define BOOT_API_CTX_EMMC_XFER_STATUS_NOT_STARTED 0x0U
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#define BOOT_API_CTX_EMMC_XFER_STATUS_DATAEND_DETECTED 0x1U
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#define BOOT_API_CTX_EMMC_XFER_STATUS_XFER_OVERALL_TIMEOUT_DETECTED 0x2U
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#define BOOT_API_CTX_EMMC_XFER_STATUS_XFER_DATA_TIMEOUT 0x3U
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/*
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* Possible value of boot context field 'emmc_error_status'
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*/
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_NONE 0x0U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_CMD_TIMEOUT 0x1U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_ACK_TIMEOUT 0x2U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_DATA_CRC_FAIL 0x3U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_NOT_ENOUGH_BOOT_DATA_RX 0x4U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_HEADER_NOT_FOUND 0x5U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_HEADER_SIZE_ZERO 0x6U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_IMAGE_NOT_COMPLETE 0x7U
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#define BOOT_API_CTX_EMMC_ERROR_STATUS_ACK_ERROR 0x8U
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/* Image Header related definitions */
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/* Definition of header version */
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#if STM32MP13
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#define BOOT_API_HEADER_VERSION 0x00020000U
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#endif
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#if STM32MP15
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#define BOOT_API_HEADER_VERSION 0x00010000U
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#endif
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/*
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* Magic number used to detect header in memory
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* Its value must be 'S' 'T' 'M' 0x32, i.e 0x324D5453 as field
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* 'bootapi_image_header_t.magic'
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* This identifies the start of a boot image.
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*/
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#define BOOT_API_IMAGE_HEADER_MAGIC_NB 0x324D5453U
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/* Definitions related to Authentication used in image header structure */
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#define BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES 64
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#define BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES 64
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#define BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES 32
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/* Possible values of the field 'boot_api_image_header_t.ecc_algo_type' */
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#define BOOT_API_ECDSA_ALGO_TYPE_P256NIST 1
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#define BOOT_API_ECDSA_ALGO_TYPE_BRAINPOOL256 2
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/*
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* Extension headers related definitions
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*/
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/* 'bootapi_image_header_t.extension_flag' used for authentication feature */
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#define BOOT_API_AUTHENTICATION_EXTENSION_BIT BIT(0)
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/* 'bootapi_image_header_t.extension_flag' used for FSBL decryption feature */
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#define BOOT_API_FSBL_DECRYPTION_EXTENSION_BIT BIT(1)
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/* 'bootapi_image_header_t.extension_flag' used for padding header feature */
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#define BOOT_API_PADDING_EXTENSION_BIT BIT(31)
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/*
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* mask of bits of field 'bootapi_image_header_t.extension_flag'
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* used for extension headers
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*/
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#define BOOT_API_ALL_EXTENSIONS_MASK \
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(BOOT_API_AUTHENTICATION_EXTENSION_BIT | \
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BOOT_API_FSBL_DECRYPTION_EXTENSION_BIT | \
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BOOT_API_PADDING_EXTENSION_BIT)
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/*
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* Magic number of FSBL decryption extension header
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* The value shall gives the four bytes 'S','T',0x00,0x01 in memory
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*/
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#define BOOT_API_FSBL_DECRYPTION_HEADER_MAGIC_NB 0x01005453U
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/*
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* Magic number of PKH revocation extension header
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* The value shall gives the four bytes 'S','T',0x00,0x02 in memory
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*/
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#define BOOT_API_AUTHENTICATION_HEADER_MAGIC_NB 0x02005453U
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/* Max number of ECDSA public key hash in table */
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#define BOOT_API_AUTHENTICATION_NB_PKH_MAX 8U
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/* ECDSA public key hash table size in bytes */
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#define BOOT_API_AUTHENTICATION_TABLE_SIZE_BYTES \
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(BOOT_API_AUTHENTICATION_NB_PKH_MAX * \
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BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES)
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/*
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* Magic number of padding extension header
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* The value shall gives the four bytes 'S','T',0xFF,0xFF in memory
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*/
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#define BOOT_API_PADDING_HEADER_MAGIC_NB 0xFFFF5453U
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/*
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* Cores secure magic numbers
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* Constant to be stored in bakcup register
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* BOOT_API_MAGIC_NUMBER_TAMP_BCK_REG_IDX
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*/
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#define BOOT_API_A7_CORE0_MAGIC_NUMBER 0xCA7FACE0U
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#define BOOT_API_A7_CORE1_MAGIC_NUMBER 0xCA7FACE1U
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/*
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* TAMP_BCK4R register index
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* This register is used to write a Magic Number in order to restart
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* Cortex A7 Core 1 and make it execute @ branch address from TAMP_BCK5R
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*/
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#define BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX 4U
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/*
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* TAMP_BCK5R register index
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* This register is used to contain the branch address of
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* Cortex A7 Core 1 when restarted by a TAMP_BCK4R magic number writing
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*/
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#define BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX 5U
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/*
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* Possible value of boot context field 'hse_clock_value_in_hz'
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*/
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_UNDEFINED 0U
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_24_MHZ 24000000U
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_25_MHZ 25000000U
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#define BOOT_API_CTX_HSE_CLOCK_VALUE_26_MHZ 26000000U
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/*
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* Possible value of boot context field 'boot_partition_used_toboot'
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*/
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#define BOOT_API_CTX_BOOT_PARTITION_UNDEFINED 0U
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/* Used FSBL1 to boot */
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#define BOOT_API_CTX_BOOT_PARTITION_FSBL1 1U
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/* Used FSBL2 to boot */
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#define BOOT_API_CTX_BOOT_PARTITION_FSBL2 2U
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/* OTP_CFG0 */
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#define BOOT_API_OTP_MODE_WORD_NB 0
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/* Closed = OTP_CFG0[6] */
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#define BOOT_API_OTP_MODE_CLOSED_BIT_POS 6
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#define BOOT_API_RETURN_OK 0x77U
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/*
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* Boot Context related definitions
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*/
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/*
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* Boot core boot configuration structure
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* Specifies all items of the cold boot configuration
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* Memory and peripheral part.
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*/
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typedef struct {
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/*
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* Boot interface used to boot : take values from defines
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* BOOT_API_CTX_BOOT_INTERFACE_SEL_XXX above
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*/
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uint16_t boot_interface_selected;
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uint16_t boot_interface_instance;
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#if STM32MP13
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uint32_t reserved1[12];
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#endif
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#if STM32MP15
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uint32_t reserved1[13];
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#endif
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uint32_t otp_afmux_values[3];
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uint32_t reserved[3];
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#if STM32MP15
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uint32_t reserved2[2];
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#endif
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uint32_t auth_status;
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#if STM32MP15
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/*
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* Pointers to bootROM External Secure Services
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* - ECDSA verify signature
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*/
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uint32_t reserved3;
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uint32_t (*bootrom_ecdsa_verify_signature)(uint8_t *hash_in,
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uint8_t *pubkey_in,
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uint8_t *signature,
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uint32_t ecc_algo);
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uint32_t reserved4;
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#endif
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/*
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* Information specific to an SD boot
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* Updated each time an SD boot is at least attempted,
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* even if not successful
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* Note : This is useful to understand why an SD boot failed
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* in particular
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*/
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uint32_t sd_err_internal_timeout_cnt;
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uint32_t sd_err_dcrc_fail_cnt;
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uint32_t sd_err_dtimeout_cnt;
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uint32_t sd_err_ctimeout_cnt;
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uint32_t sd_err_ccrc_fail_cnt;
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uint32_t sd_overall_retry_cnt;
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/*
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* Information specific to an eMMC boot
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* Updated each time an eMMC boot is at least attempted,
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* even if not successful
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* Note : This is useful to understand why an eMMC boot failed
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* in particular
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*/
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uint32_t emmc_xfer_status;
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uint32_t emmc_error_status;
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uint32_t emmc_nbbytes_rxcopied_tosysram_download_area;
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uint32_t hse_clock_value_in_hz;
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/*
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* Boot partition :
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* ie FSBL partition on which the boot was successful
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*/
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uint32_t boot_partition_used_toboot;
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} __packed boot_api_context_t;
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/*
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* Image Header related definitions
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*/
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/*
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* Structure used to define the common Header format used for FSBL, xloader,
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* ... and in particular used by bootROM for FSBL header readout.
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* FSBL header size is 256 Bytes = 0x100
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*/
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typedef struct {
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/* BOOT_API_IMAGE_HEADER_MAGIC_NB */
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uint32_t magic;
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uint8_t image_signature[BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES];
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/*
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* Checksum of payload
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* 32-bit sum all payload bytes considered as 8 bit unsigned
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* numbers, discarding any overflow bits.
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* Use to check UART/USB downloaded image integrity when signature
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* is not used
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*/
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uint32_t payload_checksum;
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/* Image header version : should have value BOOT_API_HEADER_VERSION */
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uint32_t header_version;
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/* Image length in bytes */
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uint32_t image_length;
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/*
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* Image Entry point address : should be in the SYSRAM area
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* and at least within the download area range
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*/
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uint32_t image_entry_point;
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/* Reserved */
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uint32_t reserved1;
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/*
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* Image load address : not used by bootROM but to be consistent
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* with header format for other packages (xloader, ...)
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*/
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uint32_t load_address;
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/* Reserved */
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uint32_t reserved2;
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/* Image version to be compared by bootROM with monotonic
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* counter value in OTP_CFG4 prior executing the downloaded image
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*/
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uint32_t image_version;
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#if STM32MP13
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/*
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* Extension flags :
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*
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* Bit 0 : Authentication extension header
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* value 0 : No signature check request
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* Bit 1 : Encryption extension header
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* Bit 2 : Padding extension header
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*/
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uint32_t extension_flags;
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/* Length in bytes of all extension headers */
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uint32_t extension_headers_length;
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/* Add binary type information */
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uint32_t binary_type;
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/* Pad up to 128 byte total size */
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uint8_t pad[16];
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/* Followed by extension header */
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uint8_t ext_header[];
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#endif
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#if STM32MP15
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/*
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* Option flags:
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* Bit 0 : No signature check request : 'No_sig_check'
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* value 1 : for No signature check request
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* value 0 : No request to bypass the signature check
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* Note : No signature check is never allowed on a Secured chip
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*/
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uint32_t option_flags;
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/*
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* Type of ECC algorithm to use :
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* value 1 : for P-256 NIST algorithm
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* value 2 : for Brainpool 256 algorithm
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* See definitions 'BOOT_API_ECDSA_ALGO_TYPE_XXX' above.
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*/
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uint32_t ecc_algo_type;
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/*
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* OEM ECC Public Key (aka Root pubk) provided in header on 512 bits.
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* The SHA-256 hash of the OEM ECC pubk must match the one stored
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* in OTP cells.
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*/
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uint8_t ecc_pubk[BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES];
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/* Pad up to 256 byte total size */
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uint8_t pad[83];
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/* Add binary type information */
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uint8_t binary_type;
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#endif
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} __packed boot_api_image_header_t;
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typedef uint8_t boot_api_sha256_t[BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES];
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typedef struct {
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/* Extension header type:
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* BOOT_API_FSBL_DECRYPTION_HEADER_MAGIC_NB or
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* BOOT_API_AUTHENTICATION_HEADER_MAGIC_NB
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* BOOT_API_PADDING_HEADER_MAGIC_NB
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*/
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uint32_t type;
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/* Extension header len in byte */
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uint32_t len;
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/* parameters of this extension */
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uint8_t params[];
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} __packed boot_extension_header_t;
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typedef struct {
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/* Idx of ECDSA public key to be used in table */
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uint32_t pk_idx;
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/* Number of ECDSA public key in table */
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uint32_t nb_pk;
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/*
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* Type of ECC algorithm to use :
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* value 1 : for P-256 NIST algorithm
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* value 2 : for Brainpool 256 algorithm
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* See definitions 'BOOT_API_ECDSA_ALGO_TYPE_XXX' above.
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*/
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uint32_t ecc_algo_type;
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/* ECDSA public key to be used to check signature. */
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uint8_t ecc_pubk[BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES];
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/* table of Hash of Algo+ECDSA public key */
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boot_api_sha256_t pk_hashes[];
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} __packed boot_ext_header_params_authentication_t;
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typedef struct {
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/* Size of encryption key (128 or 256) */
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uint32_t key_size;
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uint32_t derivation_cont;
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/* 128 msb bits of plain payload SHA256 */
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uint32_t hash[4];
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} __packed boot_ext_header_params_encrypted_fsbl_t;
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#endif /* BOOT_API_H */
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+14
@@ -0,0 +1,14 @@
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/*
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||||
* Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
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||||
*/
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||||
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#ifndef PLAT_DEF_FIP_UUID_H
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#define PLAT_DEF_FIP_UUID_H
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#define UUID_STM32MP_CONFIG_CERT \
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{{0x50, 0x1d, 0x8d, 0xd2}, {0x8b, 0xce}, {0x49, 0xa5}, 0x84, 0xeb, \
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{0x55, 0x9a, 0x9f, 0x2e, 0xae, 0xaf} }
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#endif /* PLAT_DEF_FIP_UUID_H */
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+40
@@ -0,0 +1,40 @@
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/*
|
||||
* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef STM32MP1_IMG_DEF_H
|
||||
#define STM32MP1_IMG_DEF_H
|
||||
|
||||
#include <export/common/tbbr/tbbr_img_def_exp.h>
|
||||
|
||||
/* Undef the existing values */
|
||||
#undef BL32_EXTRA1_IMAGE_ID
|
||||
#undef BL32_EXTRA2_IMAGE_ID
|
||||
#undef TOS_FW_CONFIG_ID
|
||||
#undef TRUSTED_BOOT_FW_CERT_ID
|
||||
#undef FWU_METADATA_IMAGE_ID
|
||||
#undef BKUP_FWU_METADATA_IMAGE_ID
|
||||
#undef FW_CONFIG_ID
|
||||
#undef HW_CONFIG_ID
|
||||
#undef GPT_IMAGE_ID
|
||||
#undef ENC_IMAGE_ID
|
||||
|
||||
/* Define the STM32MP1 used ID */
|
||||
#define FW_CONFIG_ID U(1)
|
||||
#define HW_CONFIG_ID U(2)
|
||||
#define GPT_IMAGE_ID U(3)
|
||||
#define ENC_IMAGE_ID U(6)
|
||||
#define BL32_EXTRA1_IMAGE_ID U(8)
|
||||
#define BL32_EXTRA2_IMAGE_ID U(9)
|
||||
#define FWU_METADATA_IMAGE_ID U(12)
|
||||
#define BKUP_FWU_METADATA_IMAGE_ID U(13)
|
||||
#define TOS_FW_CONFIG_ID U(16)
|
||||
#define STM32MP_CONFIG_CERT_ID U(17)
|
||||
|
||||
/* Increase the MAX_NUMBER_IDS to match the authentication pool required */
|
||||
#define MAX_NUMBER_IDS U(19)
|
||||
|
||||
#endif /* STM32MP1_IMG_DEF_H */
|
||||
+218
@@ -0,0 +1,218 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
#include <arch.h>
|
||||
#include <drivers/arm/gic_common.h>
|
||||
#include <lib/utils_def.h>
|
||||
#include <plat/common/common_def.h>
|
||||
|
||||
#include "../stm32mp1_def.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Generic platform constants
|
||||
******************************************************************************/
|
||||
|
||||
/* Size of cacheable stacks */
|
||||
#if defined(IMAGE_BL32)
|
||||
#define PLATFORM_STACK_SIZE 0x600
|
||||
#else
|
||||
#define PLATFORM_STACK_SIZE 0xC00
|
||||
#endif
|
||||
|
||||
#define FIP_IMAGE_NAME "fip"
|
||||
#define METADATA_PART_1 "metadata1"
|
||||
#define METADATA_PART_2 "metadata2"
|
||||
|
||||
#define STM32MP_PRIMARY_CPU U(0x0)
|
||||
#define STM32MP_SECONDARY_CPU U(0x1)
|
||||
|
||||
#define PLATFORM_CLUSTER_COUNT U(1)
|
||||
#define PLATFORM_CLUSTER0_CORE_COUNT U(2)
|
||||
#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
|
||||
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
|
||||
PLATFORM_CLUSTER0_CORE_COUNT)
|
||||
#define PLATFORM_MAX_CPUS_PER_CLUSTER 2
|
||||
|
||||
#define MAX_IO_DEVICES U(4)
|
||||
#define MAX_IO_HANDLES U(4)
|
||||
#define MAX_IO_BLOCK_DEVICES U(1)
|
||||
#define MAX_IO_MTD_DEVICES U(1)
|
||||
|
||||
/*******************************************************************************
|
||||
* BL2 specific defines.
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
|
||||
* size plus a little space for growth.
|
||||
*/
|
||||
#define BL2_BASE STM32MP_BL2_BASE
|
||||
#define BL2_LIMIT (STM32MP_BL2_BASE + \
|
||||
STM32MP_BL2_SIZE)
|
||||
|
||||
#define BL2_RO_BASE STM32MP_BL2_RO_BASE
|
||||
#define BL2_RO_LIMIT (STM32MP_BL2_RO_BASE + \
|
||||
STM32MP_BL2_RO_SIZE)
|
||||
|
||||
#define BL2_RW_BASE STM32MP_BL2_RW_BASE
|
||||
#define BL2_RW_LIMIT (STM32MP_BL2_RW_BASE + \
|
||||
STM32MP_BL2_RW_SIZE)
|
||||
/*******************************************************************************
|
||||
* BL32 specific defines.
|
||||
******************************************************************************/
|
||||
#if defined(IMAGE_BL32)
|
||||
#if ENABLE_PIE
|
||||
#define BL32_BASE 0
|
||||
#define BL32_LIMIT STM32MP_BL32_SIZE
|
||||
#else
|
||||
#define BL32_BASE STM32MP_BL32_BASE
|
||||
#define BL32_LIMIT (STM32MP_BL32_BASE + \
|
||||
STM32MP_BL32_SIZE)
|
||||
#endif
|
||||
#endif /* defined(IMAGE_BL32) */
|
||||
|
||||
/*******************************************************************************
|
||||
* BL33 specific defines.
|
||||
******************************************************************************/
|
||||
#define BL33_BASE STM32MP_BL33_BASE
|
||||
|
||||
/*
|
||||
* Load address of BL33 for this platform port
|
||||
*/
|
||||
#define PLAT_STM32MP_NS_IMAGE_OFFSET BL33_BASE
|
||||
|
||||
/* Needed by STM32CubeProgrammer support */
|
||||
#define DWL_BUFFER_SIZE U(0x01000000)
|
||||
|
||||
/*
|
||||
* SSBL offset in case it's stored in eMMC boot partition.
|
||||
* We can fix it to 256K because TF-A size can't be bigger than SRAM
|
||||
*/
|
||||
#define PLAT_EMMC_BOOT_SSBL_OFFSET U(0x40000)
|
||||
|
||||
/*******************************************************************************
|
||||
* DTB specific defines.
|
||||
******************************************************************************/
|
||||
#define DTB_BASE STM32MP_DTB_BASE
|
||||
#define DTB_LIMIT (STM32MP_DTB_BASE + \
|
||||
STM32MP_DTB_SIZE)
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform specific page table and MMU setup constants
|
||||
******************************************************************************/
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
|
||||
|
||||
/*******************************************************************************
|
||||
* Declarations and constants to access the mailboxes safely. Each mailbox is
|
||||
* aligned on the biggest cache line size in the platform. This is known only
|
||||
* to the platform as it might have a combination of integrated and external
|
||||
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
|
||||
* line at any cache level. They could belong to different cpus/clusters &
|
||||
* get written while being protected by different locks causing corruption of
|
||||
* a valid mailbox address.
|
||||
******************************************************************************/
|
||||
#define CACHE_WRITEBACK_SHIFT 6
|
||||
#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
|
||||
|
||||
/*
|
||||
* Secure Interrupt: based on the standard ARM mapping
|
||||
*/
|
||||
#define ARM_IRQ_SEC_PHY_TIMER U(29)
|
||||
|
||||
#define ARM_IRQ_SEC_SGI_0 U(8)
|
||||
#define ARM_IRQ_SEC_SGI_1 U(9)
|
||||
#define ARM_IRQ_SEC_SGI_2 U(10)
|
||||
#define ARM_IRQ_SEC_SGI_3 U(11)
|
||||
#define ARM_IRQ_SEC_SGI_4 U(12)
|
||||
#define ARM_IRQ_SEC_SGI_5 U(13)
|
||||
#define ARM_IRQ_SEC_SGI_6 U(14)
|
||||
#define ARM_IRQ_SEC_SGI_7 U(15)
|
||||
|
||||
#define STM32MP1_IRQ_TZC400 U(36)
|
||||
#define STM32MP1_IRQ_TAMPSERRS U(229)
|
||||
#define STM32MP1_IRQ_AXIERRIRQ U(244)
|
||||
|
||||
/*
|
||||
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
|
||||
* terminology. On a GICv2 system or mode, the lists will be merged and treated
|
||||
* as Group 0 interrupts.
|
||||
*/
|
||||
#define PLATFORM_G1S_PROPS(grp) \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \
|
||||
GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \
|
||||
GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(STM32MP1_IRQ_TZC400, \
|
||||
GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \
|
||||
GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \
|
||||
GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \
|
||||
GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \
|
||||
GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \
|
||||
GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \
|
||||
GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_EDGE)
|
||||
|
||||
#define PLATFORM_G0_PROPS(grp) \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \
|
||||
GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \
|
||||
GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_EDGE)
|
||||
|
||||
/*
|
||||
* Power
|
||||
*/
|
||||
#define PLAT_MAX_PWR_LVL U(1)
|
||||
|
||||
/* Local power state for power domains in Run state. */
|
||||
#define ARM_LOCAL_STATE_RUN U(0)
|
||||
/* Local power state for retention. Valid only for CPU power domains */
|
||||
#define ARM_LOCAL_STATE_RET U(1)
|
||||
/* Local power state for power-down. Valid for CPU and cluster power domains */
|
||||
#define ARM_LOCAL_STATE_OFF U(2)
|
||||
/*
|
||||
* This macro defines the deepest retention state possible.
|
||||
* A higher state id will represent an invalid or a power down state.
|
||||
*/
|
||||
#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
|
||||
/*
|
||||
* This macro defines the deepest power down states possible. Any state ID
|
||||
* higher than this is invalid.
|
||||
*/
|
||||
#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
|
||||
|
||||
/*******************************************************************************
|
||||
* Size of the per-cpu data in bytes that should be reserved in the generic
|
||||
* per-cpu data structure for the FVP port.
|
||||
******************************************************************************/
|
||||
#define PLAT_PCPU_DATA_SIZE 2
|
||||
|
||||
/*******************************************************************************
|
||||
* Number of parallel entry slots in SMT SCMI server entry context. For this
|
||||
* platform, SCMI server is reached through SMC only, hence the number of
|
||||
* entry slots.
|
||||
******************************************************************************/
|
||||
#define PLAT_SMT_ENTRY_COUNT PLATFORM_CORE_COUNT
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2021, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef STM32MP1_DBGMCU_H
|
||||
#define STM32MP1_DBGMCU_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* Get chip version and ID from DBGMCU registers */
|
||||
int stm32mp1_dbgmcu_get_chip_version(uint32_t *chip_version);
|
||||
int stm32mp1_dbgmcu_get_chip_dev_id(uint32_t *chip_dev_id);
|
||||
|
||||
#endif /* STM32MP1_DBGMCU_H */
|
||||
+119
@@ -0,0 +1,119 @@
|
||||
/*
|
||||
* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef MBEDTLS_CONFIG_H
|
||||
#define MBEDTLS_CONFIG_H
|
||||
|
||||
/*
|
||||
* Key algorithms currently supported on mbed TLS libraries
|
||||
*/
|
||||
#define TF_MBEDTLS_USE_RSA 0
|
||||
#define TF_MBEDTLS_USE_ECDSA 1
|
||||
|
||||
/*
|
||||
* Hash algorithms currently supported on mbed TLS libraries
|
||||
*/
|
||||
#define TF_MBEDTLS_SHA256 1
|
||||
#define TF_MBEDTLS_SHA384 2
|
||||
#define TF_MBEDTLS_SHA512 3
|
||||
|
||||
/*
|
||||
* Configuration file to build mbed TLS with the required features for
|
||||
* Trusted Boot
|
||||
*/
|
||||
|
||||
#define MBEDTLS_PLATFORM_MEMORY
|
||||
#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
|
||||
/* Prevent mbed TLS from using snprintf so that it can use tf_snprintf. */
|
||||
#define MBEDTLS_PLATFORM_SNPRINTF_ALT
|
||||
|
||||
#define MBEDTLS_PKCS1_V21
|
||||
|
||||
#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
|
||||
#define MBEDTLS_X509_CHECK_KEY_USAGE
|
||||
#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
|
||||
|
||||
#define MBEDTLS_ASN1_PARSE_C
|
||||
#define MBEDTLS_ASN1_WRITE_C
|
||||
|
||||
#define MBEDTLS_BASE64_C
|
||||
#define MBEDTLS_BIGNUM_C
|
||||
|
||||
#define MBEDTLS_ERROR_C
|
||||
#define MBEDTLS_MD_C
|
||||
|
||||
#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
|
||||
#define MBEDTLS_OID_C
|
||||
|
||||
#define MBEDTLS_PK_C
|
||||
#define MBEDTLS_PK_PARSE_C
|
||||
#define MBEDTLS_PK_WRITE_C
|
||||
|
||||
#define MBEDTLS_PLATFORM_C
|
||||
|
||||
#if TF_MBEDTLS_USE_ECDSA
|
||||
#define MBEDTLS_ECDSA_C
|
||||
#define MBEDTLS_ECP_C
|
||||
#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
|
||||
#define MBEDTLS_ECP_NO_INTERNAL_RNG
|
||||
#endif
|
||||
#if TF_MBEDTLS_USE_RSA
|
||||
#define MBEDTLS_RSA_C
|
||||
#define MBEDTLS_X509_RSASSA_PSS_SUPPORT
|
||||
#endif
|
||||
|
||||
#define MBEDTLS_SHA256_C
|
||||
#if (TF_MBEDTLS_HASH_ALG_ID != TF_MBEDTLS_SHA256)
|
||||
#define MBEDTLS_SHA512_C
|
||||
#endif
|
||||
|
||||
#define MBEDTLS_VERSION_C
|
||||
|
||||
#define MBEDTLS_X509_USE_C
|
||||
#define MBEDTLS_X509_CRT_PARSE_C
|
||||
|
||||
#if TF_MBEDTLS_USE_AES_GCM
|
||||
#define MBEDTLS_AES_C
|
||||
#define MBEDTLS_CIPHER_C
|
||||
#define MBEDTLS_GCM_C
|
||||
#endif
|
||||
|
||||
/* MPI / BIGNUM options */
|
||||
#define MBEDTLS_MPI_WINDOW_SIZE 2
|
||||
|
||||
#if TF_MBEDTLS_USE_RSA
|
||||
#if TF_MBEDTLS_KEY_SIZE <= 2048
|
||||
#define MBEDTLS_MPI_MAX_SIZE 256
|
||||
#else
|
||||
#define MBEDTLS_MPI_MAX_SIZE 512
|
||||
#endif
|
||||
#else
|
||||
#define MBEDTLS_MPI_MAX_SIZE 256
|
||||
#endif
|
||||
|
||||
/* Memory buffer allocator options */
|
||||
#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 8
|
||||
|
||||
/*
|
||||
* Prevent the use of 128-bit division which
|
||||
* creates dependency on external libraries.
|
||||
*/
|
||||
#define MBEDTLS_NO_UDBL_DIVISION
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
/* System headers required to build mbed TLS with the current configuration */
|
||||
#include <stdlib.h>
|
||||
#include <mbedtls/check_config.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Mbed TLS heap size is smal as we only use the asn1
|
||||
* parsing functions
|
||||
* digest, signature and crypto algorithm are done by
|
||||
* other library.
|
||||
*/
|
||||
|
||||
#define TF_MBEDTLS_HEAP_SIZE U(5120)
|
||||
#endif /* MBEDTLS_CONFIG_H */
|
||||
+38
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef STM32MP1_PRIVATE_H
|
||||
#define STM32MP1_PRIVATE_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void configure_mmu(void);
|
||||
|
||||
void stm32mp1_arch_security_setup(void);
|
||||
void stm32mp1_security_setup(void);
|
||||
|
||||
void stm32mp1_gic_pcpu_init(void);
|
||||
void stm32mp1_gic_init(void);
|
||||
|
||||
void stm32mp1_syscfg_init(void);
|
||||
void stm32mp1_syscfg_enable_io_compensation_start(void);
|
||||
void stm32mp1_syscfg_enable_io_compensation_finish(void);
|
||||
void stm32mp1_syscfg_disable_io_compensation(void);
|
||||
uint32_t stm32mp1_syscfg_get_chip_version(void);
|
||||
uint32_t stm32mp1_syscfg_get_chip_dev_id(void);
|
||||
#if STM32MP13
|
||||
void stm32mp1_syscfg_boot_mode_enable(void);
|
||||
void stm32mp1_syscfg_boot_mode_disable(void);
|
||||
#endif
|
||||
#if STM32MP15
|
||||
static inline void stm32mp1_syscfg_boot_mode_enable(void){}
|
||||
static inline void stm32mp1_syscfg_boot_mode_disable(void){}
|
||||
#endif
|
||||
|
||||
void stm32mp1_deconfigure_uart_pins(void);
|
||||
|
||||
void stm32mp1_init_scmi_server(void);
|
||||
#endif /* STM32MP1_PRIVATE_H */
|
||||
+38
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef STM32MP1_SHARED_RESOURCES_H
|
||||
#define STM32MP1_SHARED_RESOURCES_H
|
||||
|
||||
#include <stm32mp_shared_resources.h>
|
||||
|
||||
#define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + (i))
|
||||
|
||||
enum stm32mp_shres {
|
||||
STM32MP1_SHRES_CRYP1,
|
||||
STM32MP1_SHRES_GPIOZ_0,
|
||||
STM32MP1_SHRES_GPIOZ_1,
|
||||
STM32MP1_SHRES_GPIOZ_2,
|
||||
STM32MP1_SHRES_GPIOZ_3,
|
||||
STM32MP1_SHRES_GPIOZ_4,
|
||||
STM32MP1_SHRES_GPIOZ_5,
|
||||
STM32MP1_SHRES_GPIOZ_6,
|
||||
STM32MP1_SHRES_GPIOZ_7,
|
||||
STM32MP1_SHRES_HASH1,
|
||||
STM32MP1_SHRES_I2C4,
|
||||
STM32MP1_SHRES_I2C6,
|
||||
STM32MP1_SHRES_IWDG1,
|
||||
STM32MP1_SHRES_MCU,
|
||||
STM32MP1_SHRES_MDMA,
|
||||
STM32MP1_SHRES_PLL3,
|
||||
STM32MP1_SHRES_RNG1,
|
||||
STM32MP1_SHRES_RTC,
|
||||
STM32MP1_SHRES_SPI6,
|
||||
STM32MP1_SHRES_USART1,
|
||||
|
||||
STM32MP1_SHRES_COUNT
|
||||
};
|
||||
#endif /* STM32MP1_SHARED_RESOURCES_H */
|
||||
+67
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright (c) 2016-2021, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef STM32MP1_SMC_H
|
||||
#define STM32MP1_SMC_H
|
||||
|
||||
/*
|
||||
* SMC function IDs for STM32 Service queries
|
||||
* STM32 SMC services use the space between 0x82000000 and 0x8200FFFF
|
||||
* like this is defined in SMC calling Convention by ARM
|
||||
* for SiP (silicon Partner)
|
||||
* https://developer.arm.com/docs/den0028/latest
|
||||
*/
|
||||
|
||||
/* Secure Service access from Non-secure */
|
||||
|
||||
/*
|
||||
* STM32_SMC_BSEC call API
|
||||
*
|
||||
* Argument a0: (input) SMCC ID
|
||||
* (output) status return code
|
||||
* Argument a1: (input) Service ID (STM32_SMC_BSEC_xxx)
|
||||
* Argument a2: (input) OTP index
|
||||
* (output) OTP read value, if applicable
|
||||
* Argument a3: (input) OTP value if applicable
|
||||
*/
|
||||
#define STM32_SMC_BSEC 0x82001003
|
||||
|
||||
/*
|
||||
* STM32_SIP_SMC_SCMI_AGENT0
|
||||
* STM32_SIP_SMC_SCMI_AGENT1
|
||||
* Process SCMI message pending in SCMI shared memory buffer.
|
||||
*
|
||||
* Argument a0: (input) SMCC ID
|
||||
*/
|
||||
#define STM32_SIP_SMC_SCMI_AGENT0 0x82002000
|
||||
#define STM32_SIP_SMC_SCMI_AGENT1 0x82002001
|
||||
|
||||
/* SMC function IDs for SiP Service queries */
|
||||
#define STM32_SIP_SVC_CALL_COUNT 0x8200ff00
|
||||
#define STM32_SIP_SVC_UID 0x8200ff01
|
||||
/* 0x8200ff02 is reserved */
|
||||
#define STM32_SIP_SVC_VERSION 0x8200ff03
|
||||
|
||||
/* STM32 SiP Service Calls version numbers */
|
||||
#define STM32_SIP_SVC_VERSION_MAJOR 0x0
|
||||
#define STM32_SIP_SVC_VERSION_MINOR 0x1
|
||||
|
||||
/* Number of STM32 SiP Calls implemented */
|
||||
#define STM32_COMMON_SIP_NUM_CALLS 3
|
||||
|
||||
/* Service for BSEC */
|
||||
#define STM32_SMC_READ_SHADOW 0x01
|
||||
#define STM32_SMC_PROG_OTP 0x02
|
||||
#define STM32_SMC_WRITE_SHADOW 0x03
|
||||
#define STM32_SMC_READ_OTP 0x04
|
||||
|
||||
/* SMC error codes */
|
||||
#define STM32_SMC_OK 0x00000000U
|
||||
#define STM32_SMC_NOT_SUPPORTED 0xFFFFFFFFU
|
||||
#define STM32_SMC_FAILED 0xFFFFFFFEU
|
||||
#define STM32_SMC_INVALID_PARAMS 0xFFFFFFFDU
|
||||
|
||||
#endif /* STM32MP1_SMC_H */
|
||||
+19
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef STM32MP1_TBB_CERT_H
|
||||
#define STM32MP1_TBB_CERT_H
|
||||
|
||||
#include <tbbr/tbb_cert.h>
|
||||
|
||||
/*
|
||||
* Enumerate the certificates that are used to establish the chain of trust
|
||||
*/
|
||||
enum {
|
||||
STM32MP_CONFIG_CERT = FWU_CERT + 1
|
||||
};
|
||||
|
||||
#endif /* STM32MP1_TBB_CERT_H */
|
||||
Reference in New Issue
Block a user