GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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#
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# Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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ifeq ($(STM32MP13),1)
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$(error "SP_min is not supported on STM32MP13 platform")
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endif
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SP_MIN_WITH_SECURE_FIQ := 1
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override ENABLE_PIE := 1
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BL32_CFLAGS += -fpie -DENABLE_PIE
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BL32_LDFLAGS += $(PIE_LDFLAGS)
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BL32_CFLAGS += -DSTM32MP_SHARED_RESOURCES
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BL32_SOURCES += drivers/st/etzpc/etzpc.c \
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plat/common/aarch32/platform_mp_stack.S \
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plat/st/stm32mp1/sp_min/sp_min_setup.c \
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plat/st/stm32mp1/stm32mp1_pm.c \
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plat/st/stm32mp1/stm32mp1_shared_resources.c \
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plat/st/stm32mp1/stm32mp1_topology.c
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# FDT wrappers
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include common/fdt_wrappers.mk
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BL32_SOURCES += ${FDT_WRAPPERS_SOURCES}
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# Generic GIC v2
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include drivers/arm/gic/v2/gicv2.mk
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BL32_SOURCES += ${GICV2_SOURCES} \
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plat/common/plat_gicv2.c \
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plat/st/stm32mp1/stm32mp1_gic.c
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# Generic PSCI
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BL32_SOURCES += plat/common/plat_psci_common.c
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# SCMI server drivers
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BL32_SOURCES += drivers/scmi-msg/base.c \
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drivers/scmi-msg/clock.c \
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drivers/scmi-msg/entry.c \
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drivers/scmi-msg/reset_domain.c \
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drivers/scmi-msg/smt.c
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# stm32mp1 specific services
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BL32_SOURCES += plat/st/stm32mp1/services/bsec_svc.c \
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plat/st/stm32mp1/services/stm32mp1_svc_setup.c \
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plat/st/stm32mp1/stm32mp1_scmi.c
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# Arm Archtecture services
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BL32_SOURCES += services/arm_arch_svc/arm_arch_svc_setup.c
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+197
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/*
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* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <context.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/arm/tzc400.h>
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#include <drivers/generic_delay_timer.h>
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#include <drivers/st/bsec.h>
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#include <drivers/st/etzpc.h>
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#include <drivers/st/stm32_gpio.h>
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#include <drivers/st/stm32_iwdg.h>
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#include <drivers/st/stm32mp1_clk.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <platform_sp_min.h>
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/******************************************************************************
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* Placeholder variables for copying the arguments that have been passed to
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* BL32 from BL2.
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******************************************************************************/
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static entry_point_info_t bl33_image_ep_info;
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/*******************************************************************************
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* Interrupt handler for FIQ (secure IRQ)
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******************************************************************************/
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void sp_min_plat_fiq_handler(uint32_t id)
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{
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(void)plat_crash_console_init();
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switch (id & INT_ID_MASK) {
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case STM32MP1_IRQ_TZC400:
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tzc400_init(STM32MP1_TZC_BASE);
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(void)tzc400_it_handler();
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panic();
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break;
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case STM32MP1_IRQ_AXIERRIRQ:
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ERROR("STM32MP1_IRQ_AXIERRIRQ generated\n");
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panic();
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break;
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default:
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ERROR("SECURE IT handler not define for it : %u\n", id);
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break;
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}
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}
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for
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* the security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type. A NULL pointer is returned
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* if the image does not exist.
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******************************************************************************/
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entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
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{
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entry_point_info_t *next_image_info;
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next_image_info = &bl33_image_ep_info;
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if (next_image_info->pc == 0U) {
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return NULL;
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}
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return next_image_info;
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}
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CASSERT((STM32MP_SEC_SYSRAM_BASE == STM32MP_SYSRAM_BASE) &&
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((STM32MP_SEC_SYSRAM_BASE + STM32MP_SEC_SYSRAM_SIZE) <=
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(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE)),
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assert_secure_sysram_fits_at_begining_of_sysram);
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#ifdef STM32MP_NS_SYSRAM_BASE
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CASSERT((STM32MP_NS_SYSRAM_BASE >= STM32MP_SEC_SYSRAM_BASE) &&
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((STM32MP_NS_SYSRAM_BASE + STM32MP_NS_SYSRAM_SIZE) ==
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(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE)),
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assert_non_secure_sysram_fits_at_end_of_sysram);
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CASSERT((STM32MP_NS_SYSRAM_BASE & (PAGE_SIZE_4KB - U(1))) == 0U,
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assert_non_secure_sysram_base_is_4kbyte_aligned);
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#define TZMA1_SECURE_RANGE \
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(((STM32MP_NS_SYSRAM_BASE - STM32MP_SYSRAM_BASE) >> FOUR_KB_SHIFT) - 1U)
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#else
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#define TZMA1_SECURE_RANGE STM32MP1_ETZPC_TZMA_ALL_SECURE
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#endif /* STM32MP_NS_SYSRAM_BASE */
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#define TZMA0_SECURE_RANGE STM32MP1_ETZPC_TZMA_ALL_SECURE
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static void stm32mp1_etzpc_early_setup(void)
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{
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if (etzpc_init() != 0) {
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panic();
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}
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etzpc_configure_tzma(STM32MP1_ETZPC_TZMA_ROM, TZMA0_SECURE_RANGE);
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etzpc_configure_tzma(STM32MP1_ETZPC_TZMA_SYSRAM, TZMA1_SECURE_RANGE);
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}
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/*******************************************************************************
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* Perform any BL32 specific platform actions.
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******************************************************************************/
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void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
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uintptr_t dt_addr = arg1;
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stm32mp_setup_early_console();
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/* Imprecise aborts can be masked in NonSecure */
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write_scr(read_scr() | SCR_AW_BIT);
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mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
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BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE);
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configure_mmu();
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assert(params_from_bl2 != NULL);
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assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
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assert(params_from_bl2->h.version >= VERSION_2);
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bl_params_node_t *bl_params = params_from_bl2->head;
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/*
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* Copy BL33 entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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while (bl_params != NULL) {
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if (bl_params->image_id == BL33_IMAGE_ID) {
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bl33_image_ep_info = *bl_params->ep_info;
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/*
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* Check if hw_configuration is given to BL32 and
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* share it to BL33.
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*/
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if (arg2 != 0U) {
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bl33_image_ep_info.args.arg0 = 0U;
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bl33_image_ep_info.args.arg1 = 0U;
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bl33_image_ep_info.args.arg2 = arg2;
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}
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break;
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}
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bl_params = bl_params->next_params_info;
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}
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if (dt_open_and_check(dt_addr) < 0) {
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panic();
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}
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if (bsec_probe() != 0) {
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panic();
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}
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if (stm32mp1_clk_probe() < 0) {
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panic();
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}
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(void)stm32mp_uart_console_setup();
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stm32mp1_etzpc_early_setup();
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}
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/*******************************************************************************
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* Initialize the MMU, security and the GIC.
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******************************************************************************/
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void sp_min_platform_setup(void)
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{
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generic_delay_timer_init();
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stm32mp1_gic_init();
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if (stm32_iwdg_init() < 0) {
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panic();
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}
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stm32mp_lock_periph_registering();
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stm32mp1_init_scmi_server();
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}
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void sp_min_plat_arch_setup(void)
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{
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}
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