GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Texas Instruments K3 Secure Proxy Driver
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* Based on Linux and U-Boot implementation
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*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <stdlib.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/utils.h>
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#include <lib/utils_def.h>
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#include "sec_proxy.h"
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/* SEC PROXY RT THREAD STATUS */
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#define RT_THREAD_STATUS (0x0)
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#define RT_THREAD_STATUS_ERROR_SHIFT (31)
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#define RT_THREAD_STATUS_ERROR_MASK BIT(31)
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#define RT_THREAD_STATUS_CUR_CNT_SHIFT (0)
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#define RT_THREAD_STATUS_CUR_CNT_MASK GENMASK(7, 0)
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/* SEC PROXY SCFG THREAD CTRL */
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#define SCFG_THREAD_CTRL (0x1000)
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#define SCFG_THREAD_CTRL_DIR_SHIFT (31)
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#define SCFG_THREAD_CTRL_DIR_MASK BIT(31)
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#define SEC_PROXY_THREAD(base, x) ((base) + (0x1000 * (x)))
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#define THREAD_IS_RX (1)
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#define THREAD_IS_TX (0)
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/**
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* struct k3_sec_proxy_desc - Description of secure proxy integration
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* @timeout_us: Timeout for communication (in Microseconds)
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* @max_msg_size: Message size in bytes
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* @data_start_offset: Offset of the First data register of the thread
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* @data_end_offset: Offset of the Last data register of the thread
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*/
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struct k3_sec_proxy_desc {
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uint32_t timeout_us;
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uint16_t max_msg_size;
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uint16_t data_start_offset;
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uint16_t data_end_offset;
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};
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/**
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* struct k3_sec_proxy_thread - Description of a Secure Proxy Thread
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* @name: Thread Name
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* @data: Thread Data path region for target
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* @scfg: Secure Config Region for Thread
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* @rt: RealTime Region for Thread
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*/
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struct k3_sec_proxy_thread {
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const char *name;
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uintptr_t data;
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uintptr_t scfg;
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uintptr_t rt;
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};
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/**
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* struct k3_sec_proxy_mbox - Description of a Secure Proxy Instance
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* @desc: Description of the SoC integration
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* @chans: Array for valid thread instances
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*/
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struct k3_sec_proxy_mbox {
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const struct k3_sec_proxy_desc desc;
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struct k3_sec_proxy_thread threads[];
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};
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/*
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* Thread ID #0: DMSC notify
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* Thread ID #1: DMSC request response
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* Thread ID #2: DMSC request high priority
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* Thread ID #3: DMSC request low priority
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* Thread ID #4: DMSC notify response
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*/
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#define SP_THREAD(_x) \
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[_x] = { \
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.name = #_x, \
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.data = SEC_PROXY_THREAD(SEC_PROXY_DATA_BASE, _x), \
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.scfg = SEC_PROXY_THREAD(SEC_PROXY_SCFG_BASE, _x), \
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.rt = SEC_PROXY_THREAD(SEC_PROXY_RT_BASE, _x), \
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}
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static struct k3_sec_proxy_mbox spm = {
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.desc = {
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.timeout_us = SEC_PROXY_TIMEOUT_US,
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.max_msg_size = SEC_PROXY_MAX_MESSAGE_SIZE,
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.data_start_offset = 0x4,
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.data_end_offset = 0x3C,
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},
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.threads = {
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#if !K3_SEC_PROXY_LITE
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SP_THREAD(SP_NOTIFY),
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SP_THREAD(SP_RESPONSE),
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SP_THREAD(SP_HIGH_PRIORITY),
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SP_THREAD(SP_LOW_PRIORITY),
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SP_THREAD(SP_NOTIFY_RESP),
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#else
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SP_THREAD(SP_RESPONSE),
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SP_THREAD(SP_HIGH_PRIORITY),
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#endif /* K3_SEC_PROXY_LITE */
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},
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};
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/**
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* struct sec_msg_hdr - Message header for secure messages and responses
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* @checksum: CRC of message for integrity checking
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*/
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union sec_msg_hdr {
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struct {
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uint16_t checksum;
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uint16_t reserved;
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} __packed;
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uint32_t data;
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};
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/**
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* k3_sec_proxy_verify_thread() - Verify thread status before
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* sending/receiving data
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* @spt: Pointer to Secure Proxy thread description
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* @dir: Direction of the thread
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*
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* Return: 0 if all goes well, else appropriate error message
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*/
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static inline int k3_sec_proxy_verify_thread(struct k3_sec_proxy_thread *spt,
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uint32_t dir)
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{
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/* Check for any errors already available */
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if (mmio_read_32(spt->rt + RT_THREAD_STATUS) &
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RT_THREAD_STATUS_ERROR_MASK) {
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ERROR("Thread %s is corrupted, cannot send data\n", spt->name);
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return -EINVAL;
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}
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/* Make sure thread is configured for right direction */
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if ((mmio_read_32(spt->scfg + SCFG_THREAD_CTRL) & SCFG_THREAD_CTRL_DIR_MASK)
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!= (dir << SCFG_THREAD_CTRL_DIR_SHIFT)) {
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if (dir == THREAD_IS_TX)
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ERROR("Trying to send data on RX Thread %s\n",
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spt->name);
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else
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ERROR("Trying to receive data on TX Thread %s\n",
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spt->name);
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return -EINVAL;
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}
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/* Check the message queue before sending/receiving data */
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uint32_t tick_start = (uint32_t)read_cntpct_el0();
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uint32_t ticks_per_us = SYS_COUNTER_FREQ_IN_TICKS / 1000000;
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while (!(mmio_read_32(spt->rt + RT_THREAD_STATUS) & RT_THREAD_STATUS_CUR_CNT_MASK)) {
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VERBOSE("Waiting for thread %s to %s\n",
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spt->name, (dir == THREAD_IS_TX) ? "empty" : "fill");
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if (((uint32_t)read_cntpct_el0() - tick_start) >
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(spm.desc.timeout_us * ticks_per_us)) {
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ERROR("Timeout waiting for thread %s to %s\n",
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spt->name, (dir == THREAD_IS_TX) ? "empty" : "fill");
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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/**
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* k3_sec_proxy_clear_rx_thread() - Clear Secure Proxy thread
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*
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* @id: Channel Identifier
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*
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* Return: 0 if all goes well, else appropriate error message
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*/
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int k3_sec_proxy_clear_rx_thread(enum k3_sec_proxy_chan_id id)
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{
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struct k3_sec_proxy_thread *spt = &spm.threads[id];
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/* Check for any errors already available */
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if (mmio_read_32(spt->rt + RT_THREAD_STATUS) &
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RT_THREAD_STATUS_ERROR_MASK) {
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ERROR("Thread %s is corrupted, cannot send data\n", spt->name);
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return -EINVAL;
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}
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/* Make sure thread is configured for right direction */
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if (!(mmio_read_32(spt->scfg + SCFG_THREAD_CTRL) & SCFG_THREAD_CTRL_DIR_MASK)) {
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ERROR("Cannot clear a transmit thread %s\n", spt->name);
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return -EINVAL;
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}
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/* Read off messages from thread until empty */
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uint32_t try_count = 10;
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while (mmio_read_32(spt->rt + RT_THREAD_STATUS) & RT_THREAD_STATUS_CUR_CNT_MASK) {
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if (!(try_count--)) {
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ERROR("Could not clear all messages from thread %s\n", spt->name);
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return -ETIMEDOUT;
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}
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WARN("Clearing message from thread %s\n", spt->name);
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mmio_read_32(spt->data + spm.desc.data_end_offset);
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}
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return 0;
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}
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/**
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* k3_sec_proxy_send() - Send data over a Secure Proxy thread
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* @id: Channel Identifier
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* @msg: Pointer to k3_sec_proxy_msg
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*
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* Return: 0 if all goes well, else appropriate error message
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*/
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int k3_sec_proxy_send(enum k3_sec_proxy_chan_id id, const struct k3_sec_proxy_msg *msg)
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{
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struct k3_sec_proxy_thread *spt = &spm.threads[id];
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union sec_msg_hdr secure_header;
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int num_words, trail_bytes, i, ret;
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uintptr_t data_reg;
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ret = k3_sec_proxy_verify_thread(spt, THREAD_IS_TX);
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if (ret) {
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ERROR("Thread %s verification failed (%d)\n", spt->name, ret);
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return ret;
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}
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/* Check the message size */
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if (msg->len + sizeof(secure_header) > spm.desc.max_msg_size) {
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ERROR("Thread %s message length %lu > max msg size\n",
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spt->name, msg->len);
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return -EINVAL;
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}
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/* TODO: Calculate checksum */
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secure_header.checksum = 0;
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/* Send the secure header */
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data_reg = spm.desc.data_start_offset;
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mmio_write_32(spt->data + data_reg, secure_header.data);
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data_reg += sizeof(uint32_t);
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/* Send whole words */
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num_words = msg->len / sizeof(uint32_t);
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for (i = 0; i < num_words; i++) {
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mmio_write_32(spt->data + data_reg, ((uint32_t *)msg->buf)[i]);
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data_reg += sizeof(uint32_t);
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}
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/* Send remaining bytes */
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trail_bytes = msg->len % sizeof(uint32_t);
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if (trail_bytes) {
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uint32_t data_trail = 0;
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i = msg->len - trail_bytes;
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while (trail_bytes--) {
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data_trail <<= 8;
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data_trail |= msg->buf[i++];
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}
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mmio_write_32(spt->data + data_reg, data_trail);
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data_reg += sizeof(uint32_t);
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}
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/*
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* 'data_reg' indicates next register to write. If we did not already
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* write on tx complete reg(last reg), we must do so for transmit
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* In addition, we also need to make sure all intermediate data
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* registers(if any required), are reset to 0 for TISCI backward
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* compatibility to be maintained.
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*/
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while (data_reg <= spm.desc.data_end_offset) {
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mmio_write_32(spt->data + data_reg, 0);
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data_reg += sizeof(uint32_t);
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}
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VERBOSE("Message successfully sent on thread %s\n", spt->name);
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return 0;
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}
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/**
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* k3_sec_proxy_recv() - Receive data from a Secure Proxy thread
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* @id: Channel Identifier
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* @msg: Pointer to k3_sec_proxy_msg
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*
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* Return: 0 if all goes well, else appropriate error message
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*/
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int k3_sec_proxy_recv(enum k3_sec_proxy_chan_id id, struct k3_sec_proxy_msg *msg)
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{
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struct k3_sec_proxy_thread *spt = &spm.threads[id];
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union sec_msg_hdr secure_header;
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uintptr_t data_reg;
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int num_words, trail_bytes, i, ret;
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ret = k3_sec_proxy_verify_thread(spt, THREAD_IS_RX);
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if (ret) {
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ERROR("Thread %s verification failed (%d)\n", spt->name, ret);
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return ret;
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}
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/* Read secure header */
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data_reg = spm.desc.data_start_offset;
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secure_header.data = mmio_read_32(spt->data + data_reg);
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data_reg += sizeof(uint32_t);
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/* Read whole words */
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num_words = msg->len / sizeof(uint32_t);
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for (i = 0; i < num_words; i++) {
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((uint32_t *)msg->buf)[i] = mmio_read_32(spt->data + data_reg);
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data_reg += sizeof(uint32_t);
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}
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/* Read remaining bytes */
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trail_bytes = msg->len % sizeof(uint32_t);
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if (trail_bytes) {
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uint32_t data_trail = mmio_read_32(spt->data + data_reg);
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data_reg += sizeof(uint32_t);
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i = msg->len - trail_bytes;
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while (trail_bytes--) {
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msg->buf[i] = data_trail & 0xff;
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data_trail >>= 8;
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}
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}
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/*
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* 'data_reg' indicates next register to read. If we did not already
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* read on rx complete reg(last reg), we must do so for receive
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*/
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if (data_reg <= spm.desc.data_end_offset)
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mmio_read_32(spt->data + spm.desc.data_end_offset);
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/* TODO: Verify checksum */
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(void)secure_header.checksum;
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VERBOSE("Message successfully received from thread %s\n", spt->name);
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return 0;
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}
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+82
@@ -0,0 +1,82 @@
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/*
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* Texas Instruments K3 Secure Proxy Driver
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* Based on Linux and U-Boot implementation
|
||||
*
|
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
|
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SEC_PROXY_H
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#define SEC_PROXY_H
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#include <stdint.h>
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/**
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* enum k3_sec_proxy_chan_id - Secure Proxy thread IDs
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*
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* These the available IDs used in k3_sec_proxy_{send,recv}()
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* There are two schemes we use:
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* * if K3_SEC_PROXY_LITE = 1, we just have two threads to talk
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* * if K3_SEC_PROXY_LITE = 0, we have the full fledged
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* communication scheme available.
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*/
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enum k3_sec_proxy_chan_id {
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#if !K3_SEC_PROXY_LITE
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SP_NOTIFY = 0,
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SP_RESPONSE,
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SP_HIGH_PRIORITY,
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SP_LOW_PRIORITY,
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SP_NOTIFY_RESP,
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#else
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SP_RESPONSE = 8,
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/*
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* Note: TISCI documentation indicates "low priority", but in reality
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* with a single thread, there is no low or high priority.. This usage
|
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* is more appropriate for TF-A since we can reduce the churn as a
|
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* result.
|
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*/
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SP_HIGH_PRIORITY,
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#endif /* K3_SEC_PROXY_LITE */
|
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};
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/**
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* struct k3_sec_proxy_msg - Secure proxy message structure
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* @len: Length of data in the Buffer
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* @buf: Buffer pointer
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*
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* This is the structure for data used in k3_sec_proxy_{send,recv}()
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*/
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||||
struct k3_sec_proxy_msg {
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size_t len;
|
||||
uint8_t *buf;
|
||||
};
|
||||
|
||||
/**
|
||||
* k3_sec_proxy_send() - Send data over a Secure Proxy thread
|
||||
* @id: Channel Identifier
|
||||
* @msg: Pointer to k3_sec_proxy_msg
|
||||
*
|
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* Return: 0 if all goes well, else appropriate error message
|
||||
*/
|
||||
int k3_sec_proxy_clear_rx_thread(enum k3_sec_proxy_chan_id id);
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/**
|
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* k3_sec_proxy_send() - Send data over a Secure Proxy thread
|
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* @id: Channel Identifier
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||||
* @msg: Pointer to k3_sec_proxy_msg
|
||||
*
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* Return: 0 if all goes well, else appropriate error message
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||||
*/
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int k3_sec_proxy_send(enum k3_sec_proxy_chan_id id, const struct k3_sec_proxy_msg *msg);
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/**
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* k3_sec_proxy_recv() - Receive data from a Secure Proxy thread
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* @id: Channel Identifier
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||||
* @msg: Pointer to k3_sec_proxy_msg
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||||
*
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||||
* Return: 0 if all goes well, else appropriate error message
|
||||
*/
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int k3_sec_proxy_recv(enum k3_sec_proxy_chan_id id, struct k3_sec_proxy_msg *msg);
|
||||
|
||||
#endif /* SEC_PROXY_H */
|
||||
+1739
File diff suppressed because it is too large
Load Diff
+232
@@ -0,0 +1,232 @@
|
||||
/*
|
||||
* Texas Instruments System Control Interface API
|
||||
* Based on Linux and U-Boot implementation
|
||||
*
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef TI_SCI_H
|
||||
#define TI_SCI_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
/**
|
||||
* Device control operations
|
||||
*
|
||||
* - ti_sci_device_get - command to request for device managed by TISCI
|
||||
* - ti_sci_device_get_exclusive - exclusively request a device
|
||||
* - ti_sci_device_idle - Command to idle a device managed by TISCI
|
||||
* - ti_sci_device_idle_exclusive - exclusively idle a device
|
||||
* - ti_sci_device_put - command to release a device managed by TISCI
|
||||
* - ti_sci_device_put_no_wait - release a device without waiting for response
|
||||
* - ti_sci_device_is_valid - Is the device valid
|
||||
* - ti_sci_device_get_clcnt - Get context loss counter
|
||||
* @count: Pointer to Context Loss counter to populate
|
||||
* - ti_sci_device_is_idle - Check if the device is requested to be idle
|
||||
* @r_state: true if requested to be idle
|
||||
* - ti_sci_device_is_stop - Check if the device is requested to be stopped
|
||||
* @r_state: true if requested to be stopped
|
||||
* @curr_state: true if currently stopped.
|
||||
* - ti_sci_device_is_on - Check if the device is requested to be ON
|
||||
* @r_state: true if requested to be ON
|
||||
* @curr_state: true if currently ON and active
|
||||
* - ti_sci_device_is_trans - Check if the device is currently transitioning
|
||||
* @curr_state: true if currently transitioning.
|
||||
* - ti_sci_device_set_resets - Command to set resets for
|
||||
* device managed by TISCI
|
||||
* @reset_state: Device specific reset bit field
|
||||
* - ti_sci_device_get_resets - Get reset state for device managed by TISCI
|
||||
* @reset_state: Pointer to reset state to populate
|
||||
*
|
||||
* NOTE: for all these functions, the following are generic in nature:
|
||||
* @id: Device Identifier
|
||||
* Returns 0 for successful request, else returns corresponding error message.
|
||||
*
|
||||
* Request for the device - NOTE: the client MUST maintain integrity of
|
||||
* usage count by balancing get_device with put_device. No refcounting is
|
||||
* managed by driver for that purpose.
|
||||
*/
|
||||
int ti_sci_device_get(uint32_t id);
|
||||
int ti_sci_device_get_exclusive(uint32_t id);
|
||||
int ti_sci_device_idle(uint32_t id);
|
||||
int ti_sci_device_idle_exclusive(uint32_t id);
|
||||
int ti_sci_device_put(uint32_t id);
|
||||
int ti_sci_device_put_no_wait(uint32_t id);
|
||||
int ti_sci_device_is_valid(uint32_t id);
|
||||
int ti_sci_device_get_clcnt(uint32_t id, uint32_t *count);
|
||||
int ti_sci_device_is_idle(uint32_t id, bool *r_state);
|
||||
int ti_sci_device_is_stop(uint32_t id, bool *r_state, bool *curr_state);
|
||||
int ti_sci_device_is_on(uint32_t id, bool *r_state, bool *curr_state);
|
||||
int ti_sci_device_is_trans(uint32_t id, bool *curr_state);
|
||||
int ti_sci_device_set_resets(uint32_t id, uint32_t reset_state);
|
||||
int ti_sci_device_get_resets(uint32_t id, uint32_t *reset_state);
|
||||
|
||||
/**
|
||||
* Clock control operations
|
||||
*
|
||||
* - ti_sci_clock_get - Get control of a clock from TI SCI
|
||||
* @needs_ssc: 'true' iff Spread Spectrum clock is desired
|
||||
* @can_change_freq: 'true' iff frequency change is desired
|
||||
* @enable_input_term: 'true' iff input termination is desired
|
||||
* - ti_sci_clock_idle - Idle a clock which is in our control
|
||||
* - ti_sci_clock_put - Release a clock from our control
|
||||
* - ti_sci_clock_is_auto - Is the clock being auto managed
|
||||
* @req_state: state indicating if the clock is auto managed
|
||||
* - ti_sci_clock_is_on - Is the clock ON
|
||||
* @req_state: state indicating if the clock is managed by us and enabled
|
||||
* @curr_state: state indicating if the clock is ready for operation
|
||||
* - ti_sci_clock_is_off - Is the clock OFF
|
||||
* @req_state: state indicating if the clock is managed by us and disabled
|
||||
* @curr_state: state indicating if the clock is NOT ready for operation
|
||||
* - ti_sci_clock_set_parent - Set the clock source of a specific device clock
|
||||
* @parent_id: Parent clock identifier to set
|
||||
* - ti_sci_clock_get_parent - Get current parent clock source
|
||||
* @parent_id: Current clock parent
|
||||
* - ti_sci_clock_get_num_parents - Get num parents of the current clk source
|
||||
* @num_parents: Returns he number of parents to the current clock.
|
||||
* - ti_sci_clock_get_match_freq - Find a good match for frequency
|
||||
* @match_freq: Frequency match in Hz response.
|
||||
* - ti_sci_clock_set_freq - Set a frequency for clock
|
||||
* - ti_sci_clock_get_freq - Get current frequency
|
||||
* @freq: Currently frequency in Hz
|
||||
*
|
||||
* NOTE: for all these functions, the following are generic in nature:
|
||||
* @dev_id: Device identifier this request is for
|
||||
* @clk_id: Clock identifier for the device for this request.
|
||||
* Each device has its own set of clock inputs. This indexes
|
||||
* which clock input to modify.
|
||||
* @min_freq: The minimum allowable frequency in Hz. This is the minimum
|
||||
* allowable programmed frequency and does not account for clock
|
||||
* tolerances and jitter.
|
||||
* @target_freq: The target clock frequency in Hz. A frequency will be
|
||||
* processed as close to this target frequency as possible.
|
||||
* @max_freq: The maximum allowable frequency in Hz. This is the maximum
|
||||
* allowable programmed frequency and does not account for clock
|
||||
* tolerances and jitter.
|
||||
* Returns 0 for successful request, else returns corresponding error message.
|
||||
*
|
||||
* Request for the clock - NOTE: the client MUST maintain integrity of
|
||||
* usage count by balancing get_clock with put_clock. No refcounting is
|
||||
* managed by driver for that purpose.
|
||||
*/
|
||||
int ti_sci_clock_get(uint32_t dev_id, uint8_t clk_id,
|
||||
bool needs_ssc, bool can_change_freq,
|
||||
bool enable_input_term);
|
||||
int ti_sci_clock_idle(uint32_t dev_id, uint8_t clk_id);
|
||||
int ti_sci_clock_put(uint32_t dev_id, uint8_t clk_id);
|
||||
int ti_sci_clock_is_auto(uint32_t dev_id, uint8_t clk_id,
|
||||
bool *req_state);
|
||||
int ti_sci_clock_is_on(uint32_t dev_id, uint8_t clk_id,
|
||||
bool *req_state, bool *curr_state);
|
||||
int ti_sci_clock_is_off(uint32_t dev_id, uint8_t clk_id,
|
||||
bool *req_state, bool *curr_state);
|
||||
int ti_sci_clock_set_parent(uint32_t dev_id, uint8_t clk_id,
|
||||
uint8_t parent_id);
|
||||
int ti_sci_clock_get_parent(uint32_t dev_id, uint8_t clk_id,
|
||||
uint8_t *parent_id);
|
||||
int ti_sci_clock_get_num_parents(uint32_t dev_id, uint8_t clk_id,
|
||||
uint8_t *num_parents);
|
||||
int ti_sci_clock_get_match_freq(uint32_t dev_id, uint8_t clk_id,
|
||||
uint64_t min_freq, uint64_t target_freq,
|
||||
uint64_t max_freq, uint64_t *match_freq);
|
||||
int ti_sci_clock_set_freq(uint32_t dev_id, uint8_t clk_id,
|
||||
uint64_t min_freq, uint64_t target_freq,
|
||||
uint64_t max_freq);
|
||||
int ti_sci_clock_get_freq(uint32_t dev_id, uint8_t clk_id, uint64_t *freq);
|
||||
|
||||
/**
|
||||
* Core control operations
|
||||
*
|
||||
* - ti_sci_core_reboot() - Command to request system reset
|
||||
*
|
||||
* Return: 0 if all went well, else returns appropriate error value.
|
||||
*/
|
||||
int ti_sci_core_reboot(void);
|
||||
|
||||
/**
|
||||
* Processor control operations
|
||||
*
|
||||
* - ti_sci_proc_request - Command to request a physical processor control
|
||||
* - ti_sci_proc_release - Command to release a physical processor control
|
||||
* - ti_sci_proc_handover - Command to handover a physical processor control to
|
||||
* a host in the processor's access control list.
|
||||
* @host_id: Host ID to get the control of the processor
|
||||
* - ti_sci_proc_set_boot_cfg - Command to set the processor boot configuration flags
|
||||
* @config_flags_set: Configuration flags to be set
|
||||
* @config_flags_clear: Configuration flags to be cleared.
|
||||
* - ti_sci_proc_set_boot_ctrl - Command to set the processor boot control flags
|
||||
* @control_flags_set: Control flags to be set
|
||||
* @control_flags_clear: Control flags to be cleared
|
||||
* - ti_sci_proc_set_boot_ctrl_no_wait - Same as above without waiting for response
|
||||
* - ti_sci_proc_auth_boot_image - Command to authenticate and load the image
|
||||
* and then set the processor configuration flags.
|
||||
* @cert_addr: Memory address at which payload image certificate is located.
|
||||
* - ti_sci_proc_get_boot_status - Command to get the processor boot status
|
||||
* - ti_sci_proc_wait_boot_status - Command to wait for a processor boot status
|
||||
* - ti_sci_proc_wait_boot_status_no_wait - Same as above without waiting for response
|
||||
*
|
||||
* NOTE: for all these functions, the following are generic in nature:
|
||||
* @proc_id: Processor ID
|
||||
* Returns 0 for successful request, else returns corresponding error message.
|
||||
*/
|
||||
int ti_sci_proc_request(uint8_t proc_id);
|
||||
int ti_sci_proc_release(uint8_t proc_id);
|
||||
int ti_sci_proc_handover(uint8_t proc_id, uint8_t host_id);
|
||||
int ti_sci_proc_set_boot_cfg(uint8_t proc_id, uint64_t bootvector,
|
||||
uint32_t config_flags_set,
|
||||
uint32_t config_flags_clear);
|
||||
int ti_sci_proc_set_boot_ctrl(uint8_t proc_id, uint32_t control_flags_set,
|
||||
uint32_t control_flags_clear);
|
||||
int ti_sci_proc_set_boot_ctrl_no_wait(uint8_t proc_id,
|
||||
uint32_t control_flags_set,
|
||||
uint32_t control_flags_clear);
|
||||
int ti_sci_proc_auth_boot_image(uint8_t proc_id, uint64_t cert_addr);
|
||||
int ti_sci_proc_get_boot_status(uint8_t proc_id, uint64_t *bv,
|
||||
uint32_t *cfg_flags,
|
||||
uint32_t *ctrl_flags,
|
||||
uint32_t *sts_flags);
|
||||
int ti_sci_proc_wait_boot_status(uint8_t proc_id, uint8_t num_wait_iterations,
|
||||
uint8_t num_match_iterations,
|
||||
uint8_t delay_per_iteration_us,
|
||||
uint8_t delay_before_iterations_us,
|
||||
uint32_t status_flags_1_set_all_wait,
|
||||
uint32_t status_flags_1_set_any_wait,
|
||||
uint32_t status_flags_1_clr_all_wait,
|
||||
uint32_t status_flags_1_clr_any_wait);
|
||||
int ti_sci_proc_wait_boot_status_no_wait(uint8_t proc_id,
|
||||
uint8_t num_wait_iterations,
|
||||
uint8_t num_match_iterations,
|
||||
uint8_t delay_per_iteration_us,
|
||||
uint8_t delay_before_iterations_us,
|
||||
uint32_t status_flags_1_set_all_wait,
|
||||
uint32_t status_flags_1_set_any_wait,
|
||||
uint32_t status_flags_1_clr_all_wait,
|
||||
uint32_t status_flags_1_clr_any_wait);
|
||||
|
||||
/**
|
||||
* System Low Power Operations
|
||||
*
|
||||
* - ti_sci_enter_sleep - Command to initiate system transition into suspend.
|
||||
* @proc_id: Processor ID.
|
||||
* @mode: Low power mode to enter.
|
||||
* @core_resume_addr: Address that core should be resumed from
|
||||
* after low power transition.
|
||||
*
|
||||
* NOTE: for all these functions, the following are generic in nature:
|
||||
* Returns 0 for successful request, else returns corresponding error message.
|
||||
*/
|
||||
int ti_sci_enter_sleep(uint8_t proc_id,
|
||||
uint8_t mode,
|
||||
uint64_t core_resume_addr);
|
||||
|
||||
/**
|
||||
* ti_sci_init() - Basic initialization
|
||||
*
|
||||
* Return: 0 if all goes good, else appropriate error message.
|
||||
*/
|
||||
int ti_sci_init(void);
|
||||
|
||||
#endif /* TI_SCI_H */
|
||||
+734
@@ -0,0 +1,734 @@
|
||||
/*
|
||||
* Texas Instruments System Control Interface (TISCI) Protocol
|
||||
*
|
||||
* Communication protocol with TI SCI hardware
|
||||
* The system works in a message response protocol
|
||||
* See: http://processors.wiki.ti.com/index.php/TISCI for details
|
||||
*
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef TI_SCI_PROTOCOL_H
|
||||
#define TI_SCI_PROTOCOL_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* Generic Messages */
|
||||
#define TI_SCI_MSG_ENABLE_WDT 0x0000
|
||||
#define TI_SCI_MSG_WAKE_RESET 0x0001
|
||||
#define TI_SCI_MSG_VERSION 0x0002
|
||||
#define TI_SCI_MSG_WAKE_REASON 0x0003
|
||||
#define TI_SCI_MSG_GOODBYE 0x0004
|
||||
#define TI_SCI_MSG_SYS_RESET 0x0005
|
||||
|
||||
/* Device requests */
|
||||
#define TI_SCI_MSG_SET_DEVICE_STATE 0x0200
|
||||
#define TI_SCI_MSG_GET_DEVICE_STATE 0x0201
|
||||
#define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202
|
||||
|
||||
/* Low Power Mode Requests */
|
||||
#define TI_SCI_MSG_ENTER_SLEEP 0x0301
|
||||
|
||||
/* Clock requests */
|
||||
#define TI_SCI_MSG_SET_CLOCK_STATE 0x0100
|
||||
#define TI_SCI_MSG_GET_CLOCK_STATE 0x0101
|
||||
#define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102
|
||||
#define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103
|
||||
#define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104
|
||||
#define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c
|
||||
#define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d
|
||||
#define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e
|
||||
|
||||
/* Processor Control Messages */
|
||||
#define TISCI_MSG_PROC_REQUEST 0xc000
|
||||
#define TISCI_MSG_PROC_RELEASE 0xc001
|
||||
#define TISCI_MSG_PROC_HANDOVER 0xc005
|
||||
#define TISCI_MSG_SET_PROC_BOOT_CONFIG 0xc100
|
||||
#define TISCI_MSG_SET_PROC_BOOT_CTRL 0xc101
|
||||
#define TISCI_MSG_PROC_AUTH_BOOT_IMIAGE 0xc120
|
||||
#define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400
|
||||
#define TISCI_MSG_WAIT_PROC_BOOT_STATUS 0xc401
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
|
||||
* @type: Type of messages: One of TI_SCI_MSG* values
|
||||
* @host: Host of the message
|
||||
* @seq: Message identifier indicating a transfer sequence
|
||||
* @flags: Flag for the message
|
||||
*/
|
||||
struct ti_sci_msg_hdr {
|
||||
uint16_t type;
|
||||
uint8_t host;
|
||||
uint8_t seq;
|
||||
#define TI_SCI_MSG_FLAG(val) (1 << (val))
|
||||
#define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0
|
||||
#define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0)
|
||||
#define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1)
|
||||
#define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0
|
||||
#define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1)
|
||||
/* Additional Flags */
|
||||
uint32_t flags;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_resp_version - Response for a message
|
||||
* @hdr: Generic header
|
||||
* @firmware_description: String describing the firmware
|
||||
* @firmware_revision: Firmware revision
|
||||
* @abi_major: Major version of the ABI that firmware supports
|
||||
* @abi_minor: Minor version of the ABI that firmware supports
|
||||
*
|
||||
* In general, ABI version changes follow the rule that minor version increments
|
||||
* are backward compatible. Major revision changes in ABI may not be
|
||||
* backward compatible.
|
||||
*
|
||||
* Response to a generic message with message type TI_SCI_MSG_VERSION
|
||||
*/
|
||||
struct ti_sci_msg_resp_version {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
#define FIRMWARE_DESCRIPTION_LENGTH 32
|
||||
char firmware_description[FIRMWARE_DESCRIPTION_LENGTH];
|
||||
uint16_t firmware_revision;
|
||||
uint8_t abi_major;
|
||||
uint8_t abi_minor;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_reboot - Reboot the SoC
|
||||
* @hdr: Generic Header
|
||||
* @domain: Domain to be reset, 0 for full SoC reboot
|
||||
*
|
||||
* Request type is TI_SCI_MSG_SYS_RESET, responded with a generic
|
||||
* ACK/NACK message.
|
||||
*/
|
||||
struct ti_sci_msg_req_reboot {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
#define TI_SCI_DOMAIN_FULL_SOC_RESET 0x0
|
||||
uint8_t domain;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_set_device_state - Set the desired state of the device
|
||||
* @hdr: Generic header
|
||||
* @id: Indicates which device to modify
|
||||
* @reserved: Reserved space in message, must be 0 for backward compatibility
|
||||
* @state: The desired state of the device.
|
||||
*
|
||||
* Certain flags can also be set to alter the device state:
|
||||
* + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
|
||||
* The meaning of this flag will vary slightly from device to device and from
|
||||
* SoC to SoC but it generally allows the device to wake the SoC out of deep
|
||||
* suspend states.
|
||||
* + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device.
|
||||
* + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed
|
||||
* with STATE_RETENTION or STATE_ON, it will claim the device exclusively.
|
||||
* If another host already has this device set to STATE_RETENTION or STATE_ON,
|
||||
* the message will fail. Once successful, other hosts attempting to set
|
||||
* STATE_RETENTION or STATE_ON will fail.
|
||||
*
|
||||
* Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic
|
||||
* ACK/NACK message.
|
||||
*/
|
||||
struct ti_sci_msg_req_set_device_state {
|
||||
/* Additional hdr->flags options */
|
||||
#define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8)
|
||||
#define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9)
|
||||
#define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10)
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint32_t id;
|
||||
uint32_t reserved;
|
||||
|
||||
#define MSG_DEVICE_SW_STATE_AUTO_OFF 0
|
||||
#define MSG_DEVICE_SW_STATE_RETENTION 1
|
||||
#define MSG_DEVICE_SW_STATE_ON 2
|
||||
uint8_t state;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_get_device_state - Request to get device.
|
||||
* @hdr: Generic header
|
||||
* @id: Device Identifier
|
||||
*
|
||||
* Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state
|
||||
* information
|
||||
*/
|
||||
struct ti_sci_msg_req_get_device_state {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint32_t id;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_resp_get_device_state - Response to get device request.
|
||||
* @hdr: Generic header
|
||||
* @context_loss_count: Indicates how many times the device has lost context. A
|
||||
* driver can use this monotonic counter to determine if the device has
|
||||
* lost context since the last time this message was exchanged.
|
||||
* @resets: Programmed state of the reset lines.
|
||||
* @programmed_state: The state as programmed by set_device.
|
||||
* - Uses the MSG_DEVICE_SW_* macros
|
||||
* @current_state: The actual state of the hardware.
|
||||
*
|
||||
* Response to request TI_SCI_MSG_GET_DEVICE_STATE.
|
||||
*/
|
||||
struct ti_sci_msg_resp_get_device_state {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint32_t context_loss_count;
|
||||
uint32_t resets;
|
||||
uint8_t programmed_state;
|
||||
#define MSG_DEVICE_HW_STATE_OFF 0
|
||||
#define MSG_DEVICE_HW_STATE_ON 1
|
||||
#define MSG_DEVICE_HW_STATE_TRANS 2
|
||||
uint8_t current_state;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_set_device_resets - Set the desired resets
|
||||
* configuration of the device
|
||||
* @hdr: Generic header
|
||||
* @id: Indicates which device to modify
|
||||
* @resets: A bit field of resets for the device. The meaning, behavior,
|
||||
* and usage of the reset flags are device specific. 0 for a bit
|
||||
* indicates releasing the reset represented by that bit while 1
|
||||
* indicates keeping it held.
|
||||
*
|
||||
* Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic
|
||||
* ACK/NACK message.
|
||||
*/
|
||||
struct ti_sci_msg_req_set_device_resets {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint32_t id;
|
||||
uint32_t resets;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state
|
||||
* @hdr: Generic Header, Certain flags can be set specific to the clocks:
|
||||
* MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified
|
||||
* via spread spectrum clocking.
|
||||
* MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's
|
||||
* frequency to be changed while it is running so long as it
|
||||
* is within the min/max limits.
|
||||
* MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this
|
||||
* is only applicable to clock inputs on the SoC pseudo-device.
|
||||
* @dev_id: Device identifier this request is for
|
||||
* @clk_id: Clock identifier for the device for this request.
|
||||
* Each device has it's own set of clock inputs. This indexes
|
||||
* which clock input to modify.
|
||||
* @request_state: Request the state for the clock to be set to.
|
||||
* MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock,
|
||||
* it can be disabled, regardless of the state of the device
|
||||
* MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to
|
||||
* automatically manage the state of this clock. If the device
|
||||
* is enabled, then the clock is enabled. If the device is set
|
||||
* to off or retention, then the clock is internally set as not
|
||||
* being required by the device.(default)
|
||||
* MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled,
|
||||
* regardless of the state of the device.
|
||||
*
|
||||
* Normally, all required clocks are managed by TISCI entity, this is used
|
||||
* only for specific control *IF* required. Auto managed state is
|
||||
* MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote
|
||||
* will explicitly control.
|
||||
*
|
||||
* Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic
|
||||
* ACK or NACK message.
|
||||
*/
|
||||
struct ti_sci_msg_req_set_clock_state {
|
||||
/* Additional hdr->flags options */
|
||||
#define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8)
|
||||
#define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9)
|
||||
#define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10)
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint32_t dev_id;
|
||||
uint8_t clk_id;
|
||||
#define MSG_CLOCK_SW_STATE_UNREQ 0
|
||||
#define MSG_CLOCK_SW_STATE_AUTO 1
|
||||
#define MSG_CLOCK_SW_STATE_REQ 2
|
||||
uint8_t request_state;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_get_clock_state - Request for clock state
|
||||
* @hdr: Generic Header
|
||||
* @dev_id: Device identifier this request is for
|
||||
* @clk_id: Clock identifier for the device for this request.
|
||||
* Each device has it's own set of clock inputs. This indexes
|
||||
* which clock input to get state of.
|
||||
*
|
||||
* Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state
|
||||
* of the clock
|
||||
*/
|
||||
struct ti_sci_msg_req_get_clock_state {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint32_t dev_id;
|
||||
uint8_t clk_id;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_resp_get_clock_state - Response to get clock state
|
||||
* @hdr: Generic Header
|
||||
* @programmed_state: Any programmed state of the clock. This is one of
|
||||
* MSG_CLOCK_SW_STATE* values.
|
||||
* @current_state: Current state of the clock. This is one of:
|
||||
* MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready
|
||||
* MSG_CLOCK_HW_STATE_READY: Clock is ready
|
||||
*
|
||||
* Response to TI_SCI_MSG_GET_CLOCK_STATE.
|
||||
*/
|
||||
struct ti_sci_msg_resp_get_clock_state {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint8_t programmed_state;
|
||||
#define MSG_CLOCK_HW_STATE_NOT_READY 0
|
||||
#define MSG_CLOCK_HW_STATE_READY 1
|
||||
uint8_t current_state;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_set_clock_parent - Set the clock parent
|
||||
* @hdr: Generic Header
|
||||
* @dev_id: Device identifier this request is for
|
||||
* @clk_id: Clock identifier for the device for this request.
|
||||
* Each device has it's own set of clock inputs. This indexes
|
||||
* which clock input to modify.
|
||||
* @parent_id: The new clock parent is selectable by an index via this
|
||||
* parameter.
|
||||
*
|
||||
* Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic
|
||||
* ACK / NACK message.
|
||||
*/
|
||||
struct ti_sci_msg_req_set_clock_parent {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint32_t dev_id;
|
||||
uint8_t clk_id;
|
||||
uint8_t parent_id;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_get_clock_parent - Get the clock parent
|
||||
* @hdr: Generic Header
|
||||
* @dev_id: Device identifier this request is for
|
||||
* @clk_id: Clock identifier for the device for this request.
|
||||
* Each device has it's own set of clock inputs. This indexes
|
||||
* which clock input to get the parent for.
|
||||
*
|
||||
* Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information
|
||||
*/
|
||||
struct ti_sci_msg_req_get_clock_parent {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint32_t dev_id;
|
||||
uint8_t clk_id;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_resp_get_clock_parent - Response with clock parent
|
||||
* @hdr: Generic Header
|
||||
* @parent_id: The current clock parent
|
||||
*
|
||||
* Response to TI_SCI_MSG_GET_CLOCK_PARENT.
|
||||
*/
|
||||
struct ti_sci_msg_resp_get_clock_parent {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint8_t parent_id;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents
|
||||
* @hdr: Generic header
|
||||
* @dev_id: Device identifier this request is for
|
||||
* @clk_id: Clock identifier for the device for this request.
|
||||
*
|
||||
* This request provides information about how many clock parent options
|
||||
* are available for a given clock to a device. This is typically used
|
||||
* for input clocks.
|
||||
*
|
||||
* Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate
|
||||
* message, or NACK in case of inability to satisfy request.
|
||||
*/
|
||||
struct ti_sci_msg_req_get_clock_num_parents {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint32_t dev_id;
|
||||
uint8_t clk_id;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents
|
||||
* @hdr: Generic header
|
||||
* @num_parents: Number of clock parents
|
||||
*
|
||||
* Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS
|
||||
*/
|
||||
struct ti_sci_msg_resp_get_clock_num_parents {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint8_t num_parents;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_query_clock_freq - Request to query a frequency
|
||||
* @hdr: Generic Header
|
||||
* @dev_id: Device identifier this request is for
|
||||
* @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
|
||||
* allowable programmed frequency and does not account for clock
|
||||
* tolerances and jitter.
|
||||
* @target_freq_hz: The target clock frequency. A frequency will be found
|
||||
* as close to this target frequency as possible.
|
||||
* @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
|
||||
* allowable programmed frequency and does not account for clock
|
||||
* tolerances and jitter.
|
||||
* @clk_id: Clock identifier for the device for this request.
|
||||
*
|
||||
* NOTE: Normally clock frequency management is automatically done by TISCI
|
||||
* entity. In case of specific requests, TISCI evaluates capability to achieve
|
||||
* requested frequency within provided range and responds with
|
||||
* result message.
|
||||
*
|
||||
* Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message,
|
||||
* or NACK in case of inability to satisfy request.
|
||||
*/
|
||||
struct ti_sci_msg_req_query_clock_freq {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint32_t dev_id;
|
||||
uint64_t min_freq_hz;
|
||||
uint64_t target_freq_hz;
|
||||
uint64_t max_freq_hz;
|
||||
uint8_t clk_id;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query
|
||||
* @hdr: Generic Header
|
||||
* @freq_hz: Frequency that is the best match in Hz.
|
||||
*
|
||||
* Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request
|
||||
* cannot be satisfied, the message will be of type NACK.
|
||||
*/
|
||||
struct ti_sci_msg_resp_query_clock_freq {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint64_t freq_hz;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency
|
||||
* @hdr: Generic Header
|
||||
* @dev_id: Device identifier this request is for
|
||||
* @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
|
||||
* allowable programmed frequency and does not account for clock
|
||||
* tolerances and jitter.
|
||||
* @target_freq_hz: The target clock frequency. The clock will be programmed
|
||||
* at a rate as close to this target frequency as possible.
|
||||
* @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
|
||||
* allowable programmed frequency and does not account for clock
|
||||
* tolerances and jitter.
|
||||
* @clk_id: Clock identifier for the device for this request.
|
||||
*
|
||||
* NOTE: Normally clock frequency management is automatically done by TISCI
|
||||
* entity. In case of specific requests, TISCI evaluates capability to achieve
|
||||
* requested range and responds with success/failure message.
|
||||
*
|
||||
* This sets the desired frequency for a clock within an allowable
|
||||
* range. This message will fail on an enabled clock unless
|
||||
* MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally,
|
||||
* if other clocks have their frequency modified due to this message,
|
||||
* they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled.
|
||||
*
|
||||
* Calling set frequency on a clock input to the SoC pseudo-device will
|
||||
* inform the PMMC of that clock's frequency. Setting a frequency of
|
||||
* zero will indicate the clock is disabled.
|
||||
*
|
||||
* Calling set frequency on clock outputs from the SoC pseudo-device will
|
||||
* function similarly to setting the clock frequency on a device.
|
||||
*
|
||||
* Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK
|
||||
* message.
|
||||
*/
|
||||
struct ti_sci_msg_req_set_clock_freq {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint32_t dev_id;
|
||||
uint64_t min_freq_hz;
|
||||
uint64_t target_freq_hz;
|
||||
uint64_t max_freq_hz;
|
||||
uint8_t clk_id;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency
|
||||
* @hdr: Generic Header
|
||||
* @dev_id: Device identifier this request is for
|
||||
* @clk_id: Clock identifier for the device for this request.
|
||||
*
|
||||
* NOTE: Normally clock frequency management is automatically done by TISCI
|
||||
* entity. In some cases, clock frequencies are configured by host.
|
||||
*
|
||||
* Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency
|
||||
* that the clock is currently at.
|
||||
*/
|
||||
struct ti_sci_msg_req_get_clock_freq {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint32_t dev_id;
|
||||
uint8_t clk_id;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request
|
||||
* @hdr: Generic Header
|
||||
* @freq_hz: Frequency that the clock is currently on, in Hz.
|
||||
*
|
||||
* Response to request type TI_SCI_MSG_GET_CLOCK_FREQ.
|
||||
*/
|
||||
struct ti_sci_msg_resp_get_clock_freq {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint64_t freq_hz;
|
||||
} __packed;
|
||||
|
||||
#define TISCI_ADDR_LOW_MASK 0x00000000ffffffff
|
||||
#define TISCI_ADDR_HIGH_MASK 0xffffffff00000000
|
||||
#define TISCI_ADDR_HIGH_SHIFT 32
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_proc_request - Request a processor
|
||||
*
|
||||
* @hdr: Generic Header
|
||||
* @processor_id: ID of processor
|
||||
*
|
||||
* Request type is TISCI_MSG_PROC_REQUEST, response is a generic ACK/NACK
|
||||
* message.
|
||||
*/
|
||||
struct ti_sci_msg_req_proc_request {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint8_t processor_id;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_proc_release - Release a processor
|
||||
*
|
||||
* @hdr: Generic Header
|
||||
* @processor_id: ID of processor
|
||||
*
|
||||
* Request type is TISCI_MSG_PROC_RELEASE, response is a generic ACK/NACK
|
||||
* message.
|
||||
*/
|
||||
struct ti_sci_msg_req_proc_release {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint8_t processor_id;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_proc_handover - Handover a processor to a host
|
||||
*
|
||||
* @hdr: Generic Header
|
||||
* @processor_id: ID of processor
|
||||
* @host_id: New Host we want to give control to
|
||||
*
|
||||
* Request type is TISCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
|
||||
* message.
|
||||
*/
|
||||
struct ti_sci_msg_req_proc_handover {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint8_t processor_id;
|
||||
uint8_t host_id;
|
||||
} __packed;
|
||||
|
||||
/* A53 Config Flags */
|
||||
#define PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN 0x00000001
|
||||
#define PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN 0x00000002
|
||||
#define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN 0x00000004
|
||||
#define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN 0x00000008
|
||||
#define PROC_BOOT_CFG_FLAG_ARMV8_AARCH32 0x00000100
|
||||
|
||||
/* R5 Config Flags */
|
||||
#define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001
|
||||
#define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002
|
||||
#define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
|
||||
#define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200
|
||||
#define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400
|
||||
#define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800
|
||||
#define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
|
||||
#define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_set_proc_boot_config - Set Processor boot configuration
|
||||
* @hdr: Generic Header
|
||||
* @processor_id: ID of processor
|
||||
* @bootvector_low: Lower 32bit (Little Endian) of boot vector
|
||||
* @bootvector_high: Higher 32bit (Little Endian) of boot vector
|
||||
* @config_flags_set: Optional Processor specific Config Flags to set.
|
||||
* Setting a bit here implies required bit sets to 1.
|
||||
* @config_flags_clear: Optional Processor specific Config Flags to clear.
|
||||
* Setting a bit here implies required bit gets cleared.
|
||||
*
|
||||
* Request type is TISCI_MSG_SET_PROC_BOOT_CONFIG, response is a generic
|
||||
* ACK/NACK message.
|
||||
*/
|
||||
struct ti_sci_msg_req_set_proc_boot_config {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint8_t processor_id;
|
||||
uint32_t bootvector_low;
|
||||
uint32_t bootvector_high;
|
||||
uint32_t config_flags_set;
|
||||
uint32_t config_flags_clear;
|
||||
} __packed;
|
||||
|
||||
/* ARMV8 Control Flags */
|
||||
#define PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM 0x00000001
|
||||
#define PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS 0x00000002
|
||||
#define PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ 0x00000100
|
||||
|
||||
/* R5 Control Flags */
|
||||
#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_set_proc_boot_ctrl - Set Processor boot control flags
|
||||
* @hdr: Generic Header
|
||||
* @processor_id: ID of processor
|
||||
* @config_flags_set: Optional Processor specific Config Flags to set.
|
||||
* Setting a bit here implies required bit sets to 1.
|
||||
* @config_flags_clear: Optional Processor specific Config Flags to clear.
|
||||
* Setting a bit here implies required bit gets cleared.
|
||||
*
|
||||
* Request type is TISCI_MSG_SET_PROC_BOOT_CTRL, response is a generic ACK/NACK
|
||||
* message.
|
||||
*/
|
||||
struct ti_sci_msg_req_set_proc_boot_ctrl {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint8_t processor_id;
|
||||
uint32_t control_flags_set;
|
||||
uint32_t control_flags_clear;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_proc_auth_start_image - Authenticate and start image
|
||||
* @hdr: Generic Header
|
||||
* @processor_id: ID of processor
|
||||
* @cert_addr_low: Lower 32bit (Little Endian) of certificate
|
||||
* @cert_addr_high: Higher 32bit (Little Endian) of certificate
|
||||
*
|
||||
* Request type is TISCI_MSG_PROC_AUTH_BOOT_IMAGE, response is a generic
|
||||
* ACK/NACK message.
|
||||
*/
|
||||
struct ti_sci_msg_req_proc_auth_boot_image {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint8_t processor_id;
|
||||
uint32_t cert_addr_low;
|
||||
uint32_t cert_addr_high;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_get_proc_boot_status - Get processor boot status
|
||||
* @hdr: Generic Header
|
||||
* @processor_id: ID of processor
|
||||
*
|
||||
* Request type is TISCI_MSG_GET_PROC_BOOT_STATUS, response is appropriate
|
||||
* message, or NACK in case of inability to satisfy request.
|
||||
*/
|
||||
struct ti_sci_msg_req_get_proc_boot_status {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint8_t processor_id;
|
||||
} __packed;
|
||||
|
||||
/* ARMv8 Status Flags */
|
||||
#define PROC_BOOT_STATUS_FLAG_ARMV8_WFE 0x00000001
|
||||
#define PROC_BOOT_STATUS_FLAG_ARMV8_WFI 0x00000002
|
||||
#define PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE 0x00000010
|
||||
#define PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2 0x00000020
|
||||
|
||||
/* R5 Status Flags */
|
||||
#define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
|
||||
#define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
|
||||
#define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004
|
||||
#define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100
|
||||
|
||||
/**
|
||||
* \brief Processor Status Response
|
||||
* struct ti_sci_msg_resp_get_proc_boot_status - Processor boot status response
|
||||
* @hdr: Generic Header
|
||||
* @processor_id: ID of processor
|
||||
* @bootvector_low: Lower 32bit (Little Endian) of boot vector
|
||||
* @bootvector_high: Higher 32bit (Little Endian) of boot vector
|
||||
* @config_flags: Optional Processor specific Config Flags set.
|
||||
* @control_flags: Optional Processor specific Control Flags.
|
||||
* @status_flags: Optional Processor specific Status Flags set.
|
||||
*
|
||||
* Response to TISCI_MSG_GET_PROC_BOOT_STATUS.
|
||||
*/
|
||||
struct ti_sci_msg_resp_get_proc_boot_status {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint8_t processor_id;
|
||||
uint32_t bootvector_low;
|
||||
uint32_t bootvector_high;
|
||||
uint32_t config_flags;
|
||||
uint32_t control_flags;
|
||||
uint32_t status_flags;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_wait_proc_boot_status - Wait for a processor boot status
|
||||
* @hdr: Generic Header
|
||||
* @processor_id: ID of processor
|
||||
* @num_wait_iterations Total number of iterations we will check before
|
||||
* we will timeout and give up
|
||||
* @num_match_iterations How many iterations should we have continued
|
||||
* status to account for status bits glitching.
|
||||
* This is to make sure that match occurs for
|
||||
* consecutive checks. This implies that the
|
||||
* worst case should consider that the stable
|
||||
* time should at the worst be num_wait_iterations
|
||||
* num_match_iterations to prevent timeout.
|
||||
* @delay_per_iteration_us Specifies how long to wait (in micro seconds)
|
||||
* between each status checks. This is the minimum
|
||||
* duration, and overhead of register reads and
|
||||
* checks are on top of this and can vary based on
|
||||
* varied conditions.
|
||||
* @delay_before_iterations_us Specifies how long to wait (in micro seconds)
|
||||
* before the very first check in the first
|
||||
* iteration of status check loop. This is the
|
||||
* minimum duration, and overhead of register
|
||||
* reads and checks are.
|
||||
* @status_flags_1_set_all_wait If non-zero, Specifies that all bits of the
|
||||
* status matching this field requested MUST be 1.
|
||||
* @status_flags_1_set_any_wait If non-zero, Specifies that at least one of the
|
||||
* bits matching this field requested MUST be 1.
|
||||
* @status_flags_1_clr_all_wait If non-zero, Specifies that all bits of the
|
||||
* status matching this field requested MUST be 0.
|
||||
* @status_flags_1_clr_any_wait If non-zero, Specifies that at least one of the
|
||||
* bits matching this field requested MUST be 0.
|
||||
*
|
||||
* Request type is TISCI_MSG_WAIT_PROC_BOOT_STATUS, response is appropriate
|
||||
* message, or NACK in case of inability to satisfy request.
|
||||
*/
|
||||
struct ti_sci_msg_req_wait_proc_boot_status {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint8_t processor_id;
|
||||
uint8_t num_wait_iterations;
|
||||
uint8_t num_match_iterations;
|
||||
uint8_t delay_per_iteration_us;
|
||||
uint8_t delay_before_iterations_us;
|
||||
uint32_t status_flags_1_set_all_wait;
|
||||
uint32_t status_flags_1_set_any_wait;
|
||||
uint32_t status_flags_1_clr_all_wait;
|
||||
uint32_t status_flags_1_clr_any_wait;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct ti_sci_msg_req_enter_sleep - Request for TI_SCI_MSG_ENTER_SLEEP.
|
||||
*
|
||||
* @hdr Generic Header
|
||||
* @mode Low power mode to enter.
|
||||
* @proc_id Processor id to be restored.
|
||||
* @core_resume_lo Low 32-bits of physical pointer to address for core
|
||||
* to begin execution upon resume.
|
||||
* @core_resume_hi High 32-bits of physical pointer to address for core
|
||||
* to begin execution upon resume.
|
||||
*
|
||||
* This message is to be sent after TI_SCI_MSG_PREPARE_SLEEP is sent from OS
|
||||
* and is what actually triggers entry into the specified low power mode.
|
||||
*/
|
||||
struct ti_sci_msg_req_enter_sleep {
|
||||
struct ti_sci_msg_hdr hdr;
|
||||
uint8_t mode;
|
||||
uint8_t processor_id;
|
||||
uint32_t core_resume_lo;
|
||||
uint32_t core_resume_hi;
|
||||
} __packed;
|
||||
|
||||
#endif /* TI_SCI_PROTOCOL_H */
|
||||
@@ -0,0 +1,197 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <string.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <common/bl_common.h>
|
||||
#include <common/debug.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/xlat_tables/xlat_tables_v2.h>
|
||||
|
||||
#include <k3_console.h>
|
||||
#include <k3_gicv3.h>
|
||||
#include <ti_sci.h>
|
||||
|
||||
/* Table of regions to map using the MMU */
|
||||
const mmap_region_t plat_k3_mmap[] = {
|
||||
MAP_REGION_FLAT(K3_USART_BASE, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(K3_GTC_BASE, K3_GTC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(SEC_PROXY_SCFG_BASE, SEC_PROXY_SCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(SEC_PROXY_DATA_BASE, SEC_PROXY_DATA_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
/*
|
||||
* Placeholder variables for maintaining information about the next image(s)
|
||||
*/
|
||||
static entry_point_info_t bl32_image_ep_info;
|
||||
static entry_point_info_t bl33_image_ep_info;
|
||||
|
||||
/*******************************************************************************
|
||||
* Gets SPSR for BL33 entry
|
||||
******************************************************************************/
|
||||
static uint32_t k3_get_spsr_for_bl33_entry(void)
|
||||
{
|
||||
unsigned long el_status;
|
||||
unsigned int mode;
|
||||
uint32_t spsr;
|
||||
|
||||
/* Figure out what mode we enter the non-secure world in */
|
||||
el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
|
||||
el_status &= ID_AA64PFR0_ELX_MASK;
|
||||
|
||||
mode = (el_status) ? MODE_EL2 : MODE_EL1;
|
||||
|
||||
spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
|
||||
return spsr;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Perform any BL3-1 early platform setup, such as console init and deciding on
|
||||
* memory layout.
|
||||
******************************************************************************/
|
||||
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
|
||||
u_register_t arg2, u_register_t arg3)
|
||||
{
|
||||
/* There are no parameters from BL2 if BL31 is a reset vector */
|
||||
assert(arg0 == 0U);
|
||||
assert(arg1 == 0U);
|
||||
|
||||
bl31_console_setup();
|
||||
|
||||
#ifdef BL32_BASE
|
||||
/* Populate entry point information for BL32 */
|
||||
SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
|
||||
bl32_image_ep_info.pc = BL32_BASE;
|
||||
bl32_image_ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
|
||||
DISABLE_ALL_EXCEPTIONS);
|
||||
SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
|
||||
#endif
|
||||
|
||||
/* Populate entry point information for BL33 */
|
||||
SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
|
||||
bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
|
||||
bl33_image_ep_info.spsr = k3_get_spsr_for_bl33_entry();
|
||||
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
|
||||
|
||||
#ifdef K3_HW_CONFIG_BASE
|
||||
/*
|
||||
* According to the file ``Documentation/arm64/booting.txt`` of the
|
||||
* Linux kernel tree, Linux expects the physical address of the device
|
||||
* tree blob (DTB) in x0, while x1-x3 are reserved for future use and
|
||||
* must be 0.
|
||||
*/
|
||||
bl33_image_ep_info.args.arg0 = (u_register_t)K3_HW_CONFIG_BASE;
|
||||
bl33_image_ep_info.args.arg1 = 0U;
|
||||
bl33_image_ep_info.args.arg2 = 0U;
|
||||
bl33_image_ep_info.args.arg3 = 0U;
|
||||
#endif
|
||||
}
|
||||
|
||||
void bl31_plat_arch_setup(void)
|
||||
{
|
||||
const mmap_region_t bl_regions[] = {
|
||||
MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_RO | MT_SECURE),
|
||||
MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, MT_RO_DATA | MT_RO | MT_SECURE),
|
||||
#if USE_COHERENT_MEM
|
||||
MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, MT_DEVICE | MT_RW | MT_SECURE),
|
||||
#endif
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
setup_page_tables(bl_regions, plat_k3_mmap);
|
||||
enable_mmu_el3(0);
|
||||
}
|
||||
|
||||
void bl31_platform_setup(void)
|
||||
{
|
||||
k3_gic_driver_init(K3_GIC_BASE);
|
||||
k3_gic_init();
|
||||
|
||||
ti_sci_init();
|
||||
}
|
||||
|
||||
void platform_mem_init(void)
|
||||
{
|
||||
/* Do nothing for now... */
|
||||
}
|
||||
|
||||
unsigned int plat_get_syscnt_freq2(void)
|
||||
{
|
||||
uint32_t gtc_freq;
|
||||
uint32_t gtc_ctrl;
|
||||
|
||||
/* Lets try and provide basic diagnostics - cost is low */
|
||||
gtc_ctrl = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTCR_OFFSET);
|
||||
/* Did the bootloader fail to enable timer and OS guys are confused? */
|
||||
if ((gtc_ctrl & K3_GTC_CNTCR_EN_MASK) == 0U) {
|
||||
ERROR("GTC is disabled! Timekeeping broken. Fix Bootloader\n");
|
||||
}
|
||||
/*
|
||||
* If debug will not pause time, we will have issues like
|
||||
* drivers timing out while debugging, in cases of OS like Linux,
|
||||
* RCU stall errors, which can be hard to differentiate vs real issues.
|
||||
*/
|
||||
if ((gtc_ctrl & K3_GTC_CNTCR_HDBG_MASK) == 0U) {
|
||||
WARN("GTC: Debug access doesn't stop time. Fix Bootloader\n");
|
||||
}
|
||||
|
||||
gtc_freq = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTFID0_OFFSET);
|
||||
/* Many older bootloaders may have missed programming FID0 register */
|
||||
if (gtc_freq != 0U) {
|
||||
return gtc_freq;
|
||||
}
|
||||
|
||||
/*
|
||||
* We could have just warned about this, but this can have serious
|
||||
* hard to debug side effects if we are NOT sure what the actual
|
||||
* frequency is. Lets make sure people don't miss this.
|
||||
*/
|
||||
ERROR("GTC_CNTFID0 is 0! Assuming %d Hz. Fix Bootloader\n",
|
||||
SYS_COUNTER_FREQ_IN_TICKS);
|
||||
|
||||
return SYS_COUNTER_FREQ_IN_TICKS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Empty function to prevent the console from being uninitialized after BL33 is
|
||||
* started and allow us to see messages from BL31.
|
||||
*/
|
||||
void bl31_plat_runtime_setup(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Return a pointer to the 'entry_point_info' structure of the next image
|
||||
* for the security state specified. BL3-3 corresponds to the non-secure
|
||||
* image type while BL3-2 corresponds to the secure image type. A NULL
|
||||
* pointer is returned if the image does not exist.
|
||||
******************************************************************************/
|
||||
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
|
||||
{
|
||||
entry_point_info_t *next_image_info;
|
||||
|
||||
assert(sec_state_is_valid(type));
|
||||
next_image_info = (type == NON_SECURE) ? &bl33_image_ep_info :
|
||||
&bl32_image_ep_info;
|
||||
/*
|
||||
* None of the images on the ARM development platforms can have 0x0
|
||||
* as the entrypoint
|
||||
*/
|
||||
if (next_image_info->pc)
|
||||
return next_image_info;
|
||||
|
||||
NOTICE("Requested nonexistent image\n");
|
||||
return NULL;
|
||||
}
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <drivers/console.h>
|
||||
#include <drivers/ti/uart/uart_16550.h>
|
||||
|
||||
#include <k3_console.h>
|
||||
|
||||
void bl31_console_setup(void)
|
||||
{
|
||||
static console_t console;
|
||||
|
||||
/* Initialize the console to provide early debug support */
|
||||
console_16550_register(K3_USART_BASE, K3_USART_CLK_SPEED,
|
||||
K3_USART_BAUD, &console);
|
||||
}
|
||||
@@ -0,0 +1,113 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <assert.h>
|
||||
#include <common/bl_common.h>
|
||||
#include <common/interrupt_props.h>
|
||||
#include <drivers/arm/gicv3.h>
|
||||
#include <lib/utils.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#include <k3_gicv3.h>
|
||||
|
||||
/* The GICv3 driver only needs to be initialized in EL3 */
|
||||
uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
|
||||
|
||||
#if K3_PM_SYSTEM_SUSPEND
|
||||
static gicv3_redist_ctx_t rdist_ctx[PLATFORM_CORE_COUNT];
|
||||
static gicv3_dist_ctx_t dist_ctx;
|
||||
#endif
|
||||
|
||||
static const interrupt_prop_t k3_interrupt_props[] = {
|
||||
PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
|
||||
PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
|
||||
};
|
||||
|
||||
static unsigned int k3_mpidr_to_core_pos(unsigned long mpidr)
|
||||
{
|
||||
return (unsigned int)plat_core_pos_by_mpidr(mpidr);
|
||||
}
|
||||
|
||||
gicv3_driver_data_t k3_gic_data = {
|
||||
.rdistif_num = PLATFORM_CORE_COUNT,
|
||||
.rdistif_base_addrs = rdistif_base_addrs,
|
||||
.interrupt_props = k3_interrupt_props,
|
||||
.interrupt_props_num = ARRAY_SIZE(k3_interrupt_props),
|
||||
.mpidr_to_core_pos = k3_mpidr_to_core_pos,
|
||||
};
|
||||
|
||||
void k3_gic_driver_init(uintptr_t gic_base)
|
||||
{
|
||||
/* GIC Distributor is always at the base of the IP */
|
||||
uintptr_t gicd_base = gic_base;
|
||||
/* GIC Redistributor base is run-time detected */
|
||||
uintptr_t gicr_base = 0;
|
||||
|
||||
for (unsigned int gicr_shift = 18; gicr_shift < 21; gicr_shift++) {
|
||||
uintptr_t gicr_check = gic_base + BIT(gicr_shift);
|
||||
uint32_t iidr = mmio_read_32(gicr_check + GICR_IIDR);
|
||||
if (iidr != 0) {
|
||||
/* Found the GICR base */
|
||||
gicr_base = gicr_check;
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* Assert if we have not found the GICR base */
|
||||
assert(gicr_base != 0);
|
||||
|
||||
/*
|
||||
* The GICv3 driver is initialized in EL3 and does not need
|
||||
* to be initialized again in SEL1. This is because the S-EL1
|
||||
* can use GIC system registers to manage interrupts and does
|
||||
* not need GIC interface base addresses to be configured.
|
||||
*/
|
||||
k3_gic_data.gicd_base = gicd_base;
|
||||
k3_gic_data.gicr_base = gicr_base;
|
||||
gicv3_driver_init(&k3_gic_data);
|
||||
}
|
||||
|
||||
void k3_gic_init(void)
|
||||
{
|
||||
gicv3_distif_init();
|
||||
gicv3_rdistif_init(plat_my_core_pos());
|
||||
gicv3_cpuif_enable(plat_my_core_pos());
|
||||
}
|
||||
|
||||
void k3_gic_cpuif_enable(void)
|
||||
{
|
||||
gicv3_cpuif_enable(plat_my_core_pos());
|
||||
}
|
||||
|
||||
void k3_gic_cpuif_disable(void)
|
||||
{
|
||||
gicv3_cpuif_disable(plat_my_core_pos());
|
||||
}
|
||||
|
||||
void k3_gic_pcpu_init(void)
|
||||
{
|
||||
gicv3_rdistif_init(plat_my_core_pos());
|
||||
}
|
||||
|
||||
#if K3_PM_SYSTEM_SUSPEND
|
||||
void k3_gic_save_context(void)
|
||||
{
|
||||
for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) {
|
||||
gicv3_rdistif_save(i, &rdist_ctx[i]);
|
||||
}
|
||||
gicv3_distif_save(&dist_ctx);
|
||||
}
|
||||
|
||||
void k3_gic_restore_context(void)
|
||||
{
|
||||
gicv3_distif_init_restore(&dist_ctx);
|
||||
for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) {
|
||||
gicv3_rdistif_init_restore(i, &rdist_ctx[i]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,155 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <cortex_a72.h>
|
||||
#include <cpu_macros.S>
|
||||
#include <platform_def.h>
|
||||
|
||||
#define K3_BOOT_REASON_COLD_RESET 0x1
|
||||
|
||||
/* ------------------------------------------------------------------
|
||||
* uintptr_t plat_get_my_entrypoint(void)
|
||||
* ------------------------------------------------------------------
|
||||
*
|
||||
* This function is called with the called with the MMU and caches
|
||||
* disabled (SCTLR_EL3.M = 0 and SCTLR_EL3.C = 0). The function is
|
||||
* responsible for distinguishing between a warm and cold reset for the
|
||||
* current CPU using platform-specific means. If it's a warm reset,
|
||||
* then it returns the warm reset entrypoint point provided to
|
||||
* plat_setup_psci_ops() during BL31 initialization. If it's a cold
|
||||
* reset then this function must return zero.
|
||||
*
|
||||
* This function does not follow the Procedure Call Standard used by
|
||||
* the Application Binary Interface for the ARM 64-bit architecture.
|
||||
* The caller should not assume that callee saved registers are
|
||||
* preserved across a call to this function.
|
||||
*/
|
||||
.globl plat_get_my_entrypoint
|
||||
func plat_get_my_entrypoint
|
||||
ldr x0, k3_boot_reason_data_store
|
||||
cmp x0, #K3_BOOT_REASON_COLD_RESET
|
||||
|
||||
/* We ONLY support cold boot at this point */
|
||||
bne plat_unsupported_boot
|
||||
mov x0, #0
|
||||
ret
|
||||
|
||||
/*
|
||||
* We self manage our boot reason.
|
||||
* At load time, we have just a default reason - which is cold reset
|
||||
*/
|
||||
k3_boot_reason_data_store:
|
||||
.word K3_BOOT_REASON_COLD_RESET
|
||||
|
||||
plat_unsupported_boot:
|
||||
b plat_unsupported_boot
|
||||
|
||||
endfunc plat_get_my_entrypoint
|
||||
|
||||
/* ------------------------------------------------------------------
|
||||
* unsigned int plat_my_core_pos(void)
|
||||
* ------------------------------------------------------------------
|
||||
*
|
||||
* This function returns the index of the calling CPU which is used as a
|
||||
* CPU-specific linear index into blocks of memory (for example while
|
||||
* allocating per-CPU stacks). This function will be invoked very early
|
||||
* in the initialization sequence which mandates that this function
|
||||
* should be implemented in assembly and should not rely on the
|
||||
* avalability of a C runtime environment. This function can clobber x0
|
||||
* - x8 and must preserve x9 - x29.
|
||||
*
|
||||
* This function plays a crucial role in the power domain topology
|
||||
* framework in PSCI and details of this can be found in Power Domain
|
||||
* Topology Design.
|
||||
*/
|
||||
.globl plat_my_core_pos
|
||||
func plat_my_core_pos
|
||||
mrs x0, MPIDR_EL1
|
||||
|
||||
and x1, x0, #MPIDR_CLUSTER_MASK
|
||||
lsr x1, x1, #MPIDR_AFF1_SHIFT
|
||||
and x0, x0, #MPIDR_CPU_MASK
|
||||
|
||||
cmp x1, 0
|
||||
b.eq out
|
||||
add x0, x0, #K3_CLUSTER0_CORE_COUNT
|
||||
|
||||
cmp x1, 1
|
||||
b.eq out
|
||||
add x0, x0, #K3_CLUSTER1_CORE_COUNT
|
||||
|
||||
cmp x1, 2
|
||||
b.eq out
|
||||
add x0, x0, #K3_CLUSTER2_CORE_COUNT
|
||||
|
||||
out:
|
||||
ret
|
||||
endfunc plat_my_core_pos
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* This handler does the following:
|
||||
* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
.globl plat_reset_handler
|
||||
func plat_reset_handler
|
||||
/* Only on Cortex-A72 */
|
||||
jump_if_cpu_midr CORTEX_A72_MIDR, a72
|
||||
ret
|
||||
|
||||
/* Cortex-A72 specific settings */
|
||||
a72:
|
||||
mrs x0, CORTEX_A72_L2CTLR_EL1
|
||||
orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
|
||||
msr CORTEX_A72_L2CTLR_EL1, x0
|
||||
isb
|
||||
ret
|
||||
endfunc plat_reset_handler
|
||||
|
||||
/* ---------------------------------------------
|
||||
* int plat_crash_console_init(void)
|
||||
* Function to initialize the crash console
|
||||
* without a C Runtime to print crash report.
|
||||
* Clobber list : x0 - x4
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
.globl plat_crash_console_init
|
||||
func plat_crash_console_init
|
||||
mov_imm x0, CRASH_CONSOLE_BASE
|
||||
mov_imm x1, CRASH_CONSOLE_CLK
|
||||
mov_imm x2, CRASH_CONSOLE_BAUD_RATE
|
||||
mov w3, #0x0
|
||||
b console_16550_core_init
|
||||
endfunc plat_crash_console_init
|
||||
|
||||
/* ---------------------------------------------
|
||||
* int plat_crash_console_putc(void)
|
||||
* Function to print a character on the crash
|
||||
* console without a C Runtime.
|
||||
* Clobber list : x1, x2
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
.globl plat_crash_console_putc
|
||||
func plat_crash_console_putc
|
||||
mov_imm x1, CRASH_CONSOLE_BASE
|
||||
b console_16550_core_putc
|
||||
endfunc plat_crash_console_putc
|
||||
|
||||
/* ---------------------------------------------
|
||||
* void plat_crash_console_flush()
|
||||
* Function to force a write of all buffered
|
||||
* data that hasn't been output.
|
||||
* Out : void.
|
||||
* Clobber list : x0, x1
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
.globl plat_crash_console_flush
|
||||
func plat_crash_console_flush
|
||||
mov_imm x0, CRASH_CONSOLE_BASE
|
||||
b console_16550_core_flush
|
||||
endfunc plat_crash_console_flush
|
||||
@@ -0,0 +1,295 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <common/debug.h>
|
||||
#include <lib/el3_runtime/cpu_data.h>
|
||||
#include <lib/psci/psci.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#include <ti_sci_protocol.h>
|
||||
#include <k3_gicv3.h>
|
||||
#include <ti_sci.h>
|
||||
|
||||
#define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
|
||||
#define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
|
||||
#define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
|
||||
|
||||
uintptr_t k3_sec_entrypoint;
|
||||
|
||||
static void k3_cpu_standby(plat_local_state_t cpu_state)
|
||||
{
|
||||
u_register_t scr;
|
||||
|
||||
scr = read_scr_el3();
|
||||
/* Enable the Non secure interrupt to wake the CPU */
|
||||
write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
|
||||
isb();
|
||||
/* dsb is good practice before using wfi to enter low power states */
|
||||
dsb();
|
||||
/* Enter standby state */
|
||||
wfi();
|
||||
/* Restore SCR */
|
||||
write_scr_el3(scr);
|
||||
}
|
||||
|
||||
static int k3_pwr_domain_on(u_register_t mpidr)
|
||||
{
|
||||
int core, proc_id, device_id, ret;
|
||||
|
||||
core = plat_core_pos_by_mpidr(mpidr);
|
||||
if (core < 0) {
|
||||
ERROR("Could not get target core id: %d\n", core);
|
||||
return PSCI_E_INTERN_FAIL;
|
||||
}
|
||||
|
||||
proc_id = PLAT_PROC_START_ID + core;
|
||||
device_id = PLAT_PROC_DEVICE_START_ID + core;
|
||||
|
||||
ret = ti_sci_proc_request(proc_id);
|
||||
if (ret) {
|
||||
ERROR("Request for processor failed: %d\n", ret);
|
||||
return PSCI_E_INTERN_FAIL;
|
||||
}
|
||||
|
||||
ret = ti_sci_proc_set_boot_cfg(proc_id, k3_sec_entrypoint, 0, 0);
|
||||
if (ret) {
|
||||
ERROR("Request to set core boot address failed: %d\n", ret);
|
||||
return PSCI_E_INTERN_FAIL;
|
||||
}
|
||||
|
||||
/* sanity check these are off before starting a core */
|
||||
ret = ti_sci_proc_set_boot_ctrl(proc_id,
|
||||
0, PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ |
|
||||
PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS |
|
||||
PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM);
|
||||
if (ret) {
|
||||
ERROR("Request to clear boot configuration failed: %d\n", ret);
|
||||
return PSCI_E_INTERN_FAIL;
|
||||
}
|
||||
|
||||
ret = ti_sci_device_get(device_id);
|
||||
if (ret) {
|
||||
ERROR("Request to start core failed: %d\n", ret);
|
||||
return PSCI_E_INTERN_FAIL;
|
||||
}
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
void k3_pwr_domain_off(const psci_power_state_t *target_state)
|
||||
{
|
||||
int core, cluster, proc_id, device_id, cluster_id, ret;
|
||||
|
||||
/* At very least the local core should be powering down */
|
||||
assert(CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE);
|
||||
|
||||
/* Prevent interrupts from spuriously waking up this cpu */
|
||||
k3_gic_cpuif_disable();
|
||||
|
||||
core = plat_my_core_pos();
|
||||
cluster = MPIDR_AFFLVL1_VAL(read_mpidr_el1());
|
||||
proc_id = PLAT_PROC_START_ID + core;
|
||||
device_id = PLAT_PROC_DEVICE_START_ID + core;
|
||||
cluster_id = PLAT_CLUSTER_DEVICE_START_ID + (cluster * 2);
|
||||
|
||||
/*
|
||||
* If we are the last core in the cluster then we take a reference to
|
||||
* the cluster device so that it does not get shutdown before we
|
||||
* execute the entire cluster L2 cleaning sequence below.
|
||||
*/
|
||||
if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
|
||||
ret = ti_sci_device_get(cluster_id);
|
||||
if (ret) {
|
||||
ERROR("Request to get cluster failed: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/* Start by sending wait for WFI command */
|
||||
ret = ti_sci_proc_wait_boot_status_no_wait(proc_id,
|
||||
/*
|
||||
* Wait maximum time to give us the best chance to get
|
||||
* to WFI before this command timeouts
|
||||
*/
|
||||
UINT8_MAX, 100, UINT8_MAX, UINT8_MAX,
|
||||
/* Wait for WFI */
|
||||
PROC_BOOT_STATUS_FLAG_ARMV8_WFI, 0, 0, 0);
|
||||
if (ret) {
|
||||
ERROR("Sending wait for WFI failed (%d)\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Now queue up the core shutdown request */
|
||||
ret = ti_sci_device_put_no_wait(device_id);
|
||||
if (ret) {
|
||||
ERROR("Sending core shutdown message failed (%d)\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/* If our cluster is not going down we stop here */
|
||||
if (CLUSTER_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
|
||||
return;
|
||||
|
||||
/* set AINACTS */
|
||||
ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id,
|
||||
PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS, 0);
|
||||
if (ret) {
|
||||
ERROR("Sending set control message failed (%d)\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/* set L2FLUSHREQ */
|
||||
ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id,
|
||||
PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ, 0);
|
||||
if (ret) {
|
||||
ERROR("Sending set control message failed (%d)\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/* wait for L2FLUSHDONE*/
|
||||
ret = ti_sci_proc_wait_boot_status_no_wait(proc_id,
|
||||
UINT8_MAX, 2, UINT8_MAX, UINT8_MAX,
|
||||
PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE, 0, 0, 0);
|
||||
if (ret) {
|
||||
ERROR("Sending wait message failed (%d)\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/* clear L2FLUSHREQ */
|
||||
ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id,
|
||||
0, PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ);
|
||||
if (ret) {
|
||||
ERROR("Sending set control message failed (%d)\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/* set ACINACTM */
|
||||
ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id,
|
||||
PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM, 0);
|
||||
if (ret) {
|
||||
ERROR("Sending set control message failed (%d)\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/* wait for STANDBYWFIL2 */
|
||||
ret = ti_sci_proc_wait_boot_status_no_wait(proc_id,
|
||||
UINT8_MAX, 2, UINT8_MAX, UINT8_MAX,
|
||||
PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2, 0, 0, 0);
|
||||
if (ret) {
|
||||
ERROR("Sending wait message failed (%d)\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Now queue up the cluster shutdown request */
|
||||
ret = ti_sci_device_put_no_wait(cluster_id);
|
||||
if (ret) {
|
||||
ERROR("Sending cluster shutdown message failed (%d)\n", ret);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void k3_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
||||
{
|
||||
/* TODO: Indicate to System firmware about completion */
|
||||
|
||||
k3_gic_pcpu_init();
|
||||
k3_gic_cpuif_enable();
|
||||
}
|
||||
|
||||
static void __dead2 k3_system_off(void)
|
||||
{
|
||||
ERROR("System Off: operation not handled.\n");
|
||||
while (true)
|
||||
wfi();
|
||||
}
|
||||
|
||||
static void __dead2 k3_system_reset(void)
|
||||
{
|
||||
/* Send the system reset request to system firmware */
|
||||
ti_sci_core_reboot();
|
||||
|
||||
while (true)
|
||||
wfi();
|
||||
}
|
||||
|
||||
static int k3_validate_power_state(unsigned int power_state,
|
||||
psci_power_state_t *req_state)
|
||||
{
|
||||
/* TODO: perform the proper validation */
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
static int k3_validate_ns_entrypoint(uintptr_t entrypoint)
|
||||
{
|
||||
/* TODO: perform the proper validation */
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
#if K3_PM_SYSTEM_SUSPEND
|
||||
static void k3_pwr_domain_suspend(const psci_power_state_t *target_state)
|
||||
{
|
||||
unsigned int core, proc_id;
|
||||
|
||||
core = plat_my_core_pos();
|
||||
proc_id = PLAT_PROC_START_ID + core;
|
||||
|
||||
/* Prevent interrupts from spuriously waking up this cpu */
|
||||
k3_gic_cpuif_disable();
|
||||
k3_gic_save_context();
|
||||
|
||||
k3_pwr_domain_off(target_state);
|
||||
|
||||
ti_sci_enter_sleep(proc_id, 0, k3_sec_entrypoint);
|
||||
}
|
||||
|
||||
static void k3_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
|
||||
{
|
||||
k3_gic_restore_context();
|
||||
k3_gic_cpuif_enable();
|
||||
}
|
||||
|
||||
static void k3_get_sys_suspend_power_state(psci_power_state_t *req_state)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
/* CPU & cluster off, system in retention */
|
||||
for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) {
|
||||
req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static const plat_psci_ops_t k3_plat_psci_ops = {
|
||||
.cpu_standby = k3_cpu_standby,
|
||||
.pwr_domain_on = k3_pwr_domain_on,
|
||||
.pwr_domain_off = k3_pwr_domain_off,
|
||||
.pwr_domain_on_finish = k3_pwr_domain_on_finish,
|
||||
#if K3_PM_SYSTEM_SUSPEND
|
||||
.pwr_domain_suspend = k3_pwr_domain_suspend,
|
||||
.pwr_domain_suspend_finish = k3_pwr_domain_suspend_finish,
|
||||
.get_sys_suspend_power_state = k3_get_sys_suspend_power_state,
|
||||
#endif
|
||||
.system_off = k3_system_off,
|
||||
.system_reset = k3_system_reset,
|
||||
.validate_power_state = k3_validate_power_state,
|
||||
.validate_ns_entrypoint = k3_validate_ns_entrypoint
|
||||
};
|
||||
|
||||
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
||||
const plat_psci_ops_t **psci_ops)
|
||||
{
|
||||
k3_sec_entrypoint = sec_entrypoint;
|
||||
|
||||
*psci_ops = &k3_plat_psci_ops;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <lib/psci/psci.h>
|
||||
|
||||
/* The power domain tree descriptor */
|
||||
static unsigned char power_domain_tree_desc[] = {
|
||||
PLATFORM_SYSTEM_COUNT,
|
||||
PLATFORM_CLUSTER_COUNT,
|
||||
K3_CLUSTER0_CORE_COUNT,
|
||||
K3_CLUSTER1_CORE_COUNT,
|
||||
K3_CLUSTER2_CORE_COUNT,
|
||||
K3_CLUSTER3_CORE_COUNT,
|
||||
};
|
||||
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
return power_domain_tree_desc;
|
||||
}
|
||||
|
||||
int plat_core_pos_by_mpidr(u_register_t mpidr)
|
||||
{
|
||||
unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr);
|
||||
unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
|
||||
if (MPIDR_AFFLVL3_VAL(mpidr) > 0 ||
|
||||
MPIDR_AFFLVL2_VAL(mpidr) > 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (cluster > 0)
|
||||
core += K3_CLUSTER0_CORE_COUNT;
|
||||
if (cluster > 1)
|
||||
core += K3_CLUSTER1_CORE_COUNT;
|
||||
if (cluster > 2)
|
||||
core += K3_CLUSTER2_CORE_COUNT;
|
||||
if (cluster > 3)
|
||||
return -1;
|
||||
|
||||
return core;
|
||||
}
|
||||
@@ -0,0 +1,95 @@
|
||||
#
|
||||
# Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# We don't use BL1 or BL2, so BL31 is the first image to execute
|
||||
RESET_TO_BL31 := 1
|
||||
# Only one core starts up at first
|
||||
COLD_BOOT_SINGLE_CPU := 1
|
||||
# We can choose where a core starts executing
|
||||
PROGRAMMABLE_RESET_ADDRESS:= 1
|
||||
|
||||
# ARM coherency is managed in hardware
|
||||
WARMBOOT_ENABLE_DCACHE_EARLY := 1
|
||||
|
||||
# A53 erratum for SoC. (enable them all)
|
||||
ERRATA_A53_826319 := 1
|
||||
ERRATA_A53_835769 := 1
|
||||
ERRATA_A53_836870 := 1
|
||||
ERRATA_A53_843419 := 1
|
||||
ERRATA_A53_855873 := 1
|
||||
ERRATA_A53_1530924 := 1
|
||||
|
||||
# A72 Erratum for SoC
|
||||
ERRATA_A72_859971 := 1
|
||||
ERRATA_A72_1319367 := 1
|
||||
|
||||
CRASH_REPORTING := 1
|
||||
HANDLE_EA_EL3_FIRST_NS := 1
|
||||
|
||||
# Split out RO data into a non-executable section
|
||||
SEPARATE_CODE_AND_RODATA := 1
|
||||
|
||||
# Generate a Position Independent Executable
|
||||
ENABLE_PIE := 1
|
||||
|
||||
TI_16550_MDR_QUIRK := 1
|
||||
$(eval $(call add_define,TI_16550_MDR_QUIRK))
|
||||
|
||||
K3_USART := 0
|
||||
$(eval $(call add_define,K3_USART))
|
||||
|
||||
# Allow customizing the UART baud rate
|
||||
K3_USART_BAUD := 115200
|
||||
$(eval $(call add_define,K3_USART_BAUD))
|
||||
|
||||
# Enable system suspend modes
|
||||
K3_PM_SYSTEM_SUSPEND := 0
|
||||
$(eval $(call add_define,K3_PM_SYSTEM_SUSPEND))
|
||||
|
||||
# Libraries
|
||||
include lib/xlat_tables_v2/xlat_tables.mk
|
||||
|
||||
PLAT_INCLUDES += \
|
||||
-I${PLAT_PATH}/include \
|
||||
-I${PLAT_PATH}/common/drivers/sec_proxy \
|
||||
-I${PLAT_PATH}/common/drivers/ti_sci \
|
||||
|
||||
K3_CONSOLE_SOURCES += \
|
||||
drivers/ti/uart/aarch64/16550_console.S \
|
||||
${PLAT_PATH}/common/k3_console.c \
|
||||
|
||||
# Include GICv3 driver files
|
||||
include drivers/arm/gic/v3/gicv3.mk
|
||||
|
||||
K3_GIC_SOURCES += \
|
||||
${GICV3_SOURCES} \
|
||||
plat/common/plat_gicv3.c \
|
||||
${PLAT_PATH}/common/k3_gicv3.c \
|
||||
|
||||
K3_PSCI_SOURCES += \
|
||||
plat/common/plat_psci_common.c \
|
||||
${PLAT_PATH}/common/k3_psci.c \
|
||||
|
||||
K3_SEC_PROXY_SOURCES += \
|
||||
${PLAT_PATH}/common/drivers/sec_proxy/sec_proxy.c \
|
||||
|
||||
K3_TI_SCI_SOURCES += \
|
||||
${PLAT_PATH}/common/drivers/ti_sci/ti_sci.c \
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += \
|
||||
lib/cpus/aarch64/cortex_a53.S \
|
||||
lib/cpus/aarch64/cortex_a72.S \
|
||||
${XLAT_TABLES_LIB_SRCS} \
|
||||
${K3_CONSOLE_SOURCES} \
|
||||
|
||||
BL31_SOURCES += \
|
||||
${PLAT_PATH}/common/k3_bl31_setup.c \
|
||||
${PLAT_PATH}/common/k3_helpers.S \
|
||||
${PLAT_PATH}/common/k3_topology.c \
|
||||
${K3_GIC_SOURCES} \
|
||||
${K3_PSCI_SOURCES} \
|
||||
${K3_SEC_PROXY_SOURCES} \
|
||||
${K3_TI_SCI_SOURCES} \
|
||||
Reference in New Issue
Block a user