GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
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* Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <plat_ipi.h>
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#include <plat_private.h>
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#include <versal_net_def.h>
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uint32_t platform_id, platform_version;
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/*
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* Table of regions to map using the MMU.
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* This doesn't include TZRAM as the 'mem_layout' argument passed to
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* configure_mmu_elx() will give the available subset of that,
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*/
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const mmap_region_t plat_versal_net_mmap[] = {
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MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(IPI_BASE, IPI_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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{ 0 }
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};
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const mmap_region_t *plat_versal_net_get_mmap(void)
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{
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return plat_versal_net_mmap;
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}
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/* For saving cpu clock for certain platform */
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uint32_t cpu_clock;
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char *board_name_decode(void)
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{
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switch (platform_id) {
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case VERSAL_NET_SPP:
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return "IPP";
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case VERSAL_NET_EMU:
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return "EMU";
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case VERSAL_NET_SILICON:
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return "Silicon";
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case VERSAL_NET_QEMU:
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return "QEMU";
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default:
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return "Unknown";
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}
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}
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void board_detection(void)
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{
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uint32_t version;
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version = mmio_read_32(PMC_TAP_VERSION);
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platform_id = FIELD_GET(PLATFORM_MASK, version);
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platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
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if (platform_id == VERSAL_NET_QEMU_COSIM) {
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platform_id = VERSAL_NET_QEMU;
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}
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if ((platform_id == VERSAL_NET_SPP) ||
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(platform_id == VERSAL_NET_EMU) ||
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(platform_id == VERSAL_NET_QEMU)) {
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/*
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* 9 is diff for
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* 0 means 0.9 version
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* 1 means 1.0 version
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* 2 means 1.1 version
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* etc,
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*/
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platform_version += 9U;
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}
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/* Make sure that console is setup to see this message */
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VERBOSE("Platform id: %d version: %d.%d\n", platform_id,
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platform_version / 10U, platform_version % 10U);
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}
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void versal_net_config_setup(void)
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{
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uint32_t val;
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uintptr_t crl_base, iou_scntrs_base, psx_base;
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crl_base = VERSAL_NET_CRL;
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iou_scntrs_base = VERSAL_NET_IOU_SCNTRS;
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psx_base = PSX_CRF;
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/* Reset for system timestamp generator in FPX */
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mmio_write_32(psx_base + PSX_CRF_RST_TIMESTAMP_OFFSET, 0);
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/* Global timer init - Program time stamp reference clk */
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val = mmio_read_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET);
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val |= VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
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mmio_write_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET, val);
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/* Clear reset of timestamp reg */
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mmio_write_32(crl_base + VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET, 0);
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/* Program freq register in System counter and enable system counter. */
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mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET,
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cpu_clock);
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mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
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VERSAL_NET_IOU_SCNTRS_CONTROL_EN);
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generic_delay_timer_init();
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#if (TFA_NO_PM == 0)
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/* Configure IPI data for versal_net */
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versal_net_ipi_config_table_init();
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#endif
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}
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uint32_t plat_get_syscnt_freq2(void)
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{
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return cpu_clock;
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}
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+110
@@ -0,0 +1,110 @@
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/*
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* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
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* Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <drivers/arm/gicv3.h>
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#include <platform_def.h>
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.globl plat_secondary_cold_boot_setup
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.globl plat_is_my_cpu_primary
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.globl platform_mem_init
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.globl plat_my_core_pos
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* TODO: Should we read the PSYS register to make sure
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* that the request has gone through.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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mrs x0, mpidr_el1
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/*
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* There is no sane reason to come out of this wfi. This
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* cpu will be powered on and reset by the cpu_on pm api
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*/
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dsb sy
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bl plat_panic_handler
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endfunc plat_secondary_cold_boot_setup
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func plat_is_my_cpu_primary
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mov x9, x30
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bl plat_my_core_pos
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cmp x0, #VERSAL_NET_PRIMARY_CPU
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cset x0, eq
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ret x9
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This function uses the plat_core_pos_by_mpidr()
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* definition to get the index of the calling CPU.
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b plat_core_pos_by_mpidr
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endfunc plat_my_core_pos
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/* ---------------------------------------------------------------------
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* We don't need to carry out any memory initialization on Versal NET
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* platform. The Secure RAM is accessible straight away.
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* ---------------------------------------------------------------------
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*/
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func platform_mem_init
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ret
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endfunc platform_mem_init
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0, x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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/* mov_imm x0, PLAT_VERSAL_NET_CRASH_UART_BASE
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mov_imm x1, PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ
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mov_imm x2, VERSAL_NET_CONSOLE_BAUDRATE
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b console_pl011_core_init */
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(int c)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, PLAT_VERSAL_NET_CRASH_UART_BASE
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b console_pl011_core_putc
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endfunc plat_crash_console_putc
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/* ---------------------------------------------
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* void plat_crash_console_flush()
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* Function to force a write of all buffered
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* data that hasn't been output.
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* Out : void.
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func plat_crash_console_flush
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mov_imm x0, PLAT_VERSAL_NET_CRASH_UART_BASE
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b console_pl011_core_flush
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endfunc plat_crash_console_flush
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