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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
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source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
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/*
* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdbool.h>
#include <string.h>
#include <common/debug.h>
#include <drivers/generic_delay_timer.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables.h>
#include <plat_ipi.h>
#include <plat_private.h>
#include <plat/common/platform.h>
#include "pm_api_sys.h"
/*
* Table of regions to map using the MMU.
* This doesn't include TZRAM as the 'mem_layout' argument passed to
* configure_mmu_elx() will give the available subset of that,
*/
const mmap_region_t plat_arm_mmap[] = {
{ DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
{ DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
{ CRF_APB_BASE, CRF_APB_BASE, CRF_APB_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
{0}
};
static uint32_t zynqmp_get_silicon_ver(void)
{
static unsigned int ver;
if (!ver) {
ver = mmio_read_32(ZYNQMP_CSU_BASEADDR +
ZYNQMP_CSU_VERSION_OFFSET);
ver &= ZYNQMP_SILICON_VER_MASK;
ver >>= ZYNQMP_SILICON_VER_SHIFT;
}
return ver;
}
uint32_t zynqmp_get_uart_clk(void)
{
unsigned int ver = zynqmp_get_silicon_ver();
if (ver == ZYNQMP_CSU_VERSION_QEMU) {
return 133000000;
} else {
return 100000000;
}
}
#if LOG_LEVEL >= LOG_LEVEL_NOTICE
static const struct {
uint32_t id;
uint32_t ver;
char *name;
bool evexists;
} zynqmp_devices[] = {
{
.id = 0x10,
.name = "XCZU3EG",
},
{
.id = 0x10,
.ver = 0x2c,
.name = "XCZU3CG",
},
{
.id = 0x11,
.name = "XCZU2EG",
},
{
.id = 0x11,
.ver = 0x2c,
.name = "XCZU2CG",
},
{
.id = 0x20,
.name = "XCZU5EV",
.evexists = true,
},
{
.id = 0x20,
.ver = 0x100,
.name = "XCZU5EG",
.evexists = true,
},
{
.id = 0x20,
.ver = 0x12c,
.name = "XCZU5CG",
},
{
.id = 0x21,
.name = "XCZU4EV",
.evexists = true,
},
{
.id = 0x21,
.ver = 0x100,
.name = "XCZU4EG",
.evexists = true,
},
{
.id = 0x21,
.ver = 0x12c,
.name = "XCZU4CG",
},
{
.id = 0x30,
.name = "XCZU7EV",
.evexists = true,
},
{
.id = 0x30,
.ver = 0x100,
.name = "XCZU7EG",
.evexists = true,
},
{
.id = 0x30,
.ver = 0x12c,
.name = "XCZU7CG",
},
{
.id = 0x38,
.name = "XCZU9EG",
},
{
.id = 0x38,
.ver = 0x2c,
.name = "XCZU9CG",
},
{
.id = 0x39,
.name = "XCZU6EG",
},
{
.id = 0x39,
.ver = 0x2c,
.name = "XCZU6CG",
},
{
.id = 0x40,
.name = "XCZU11EG",
},
{
.id = 0x50,
.name = "XCZU15EG",
},
{
.id = 0x58,
.name = "XCZU19EG",
},
{
.id = 0x59,
.name = "XCZU17EG",
},
{
.id = 0x60,
.name = "XCZU28DR",
},
{
.id = 0x61,
.name = "XCZU21DR",
},
{
.id = 0x62,
.name = "XCZU29DR",
},
{
.id = 0x63,
.name = "XCZU23DR",
},
{
.id = 0x64,
.name = "XCZU27DR",
},
{
.id = 0x65,
.name = "XCZU25DR",
},
{
.id = 0x66,
.name = "XCZU39DR",
},
{
.id = 0x7d,
.name = "XCZU43DR",
},
{
.id = 0x78,
.name = "XCZU46DR",
},
{
.id = 0x7f,
.name = "XCZU47DR",
},
{
.id = 0x7b,
.name = "XCZU48DR",
},
{
.id = 0x7e,
.name = "XCZU49DR",
},
};
#define ZYNQMP_PL_STATUS_BIT 9
#define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
#define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
#define SILICON_ID_XCK24 0x4714093U
#define SILICON_ID_XCK26 0x4724093U
static char *zynqmp_get_silicon_idcode_name(void)
{
uint32_t id, ver, chipid[2];
size_t i, j, len;
const char *name = "EG/EV";
#ifdef IMAGE_BL32
/*
* For BL32, get the chip id info directly by reading corresponding
* registers instead of making pm call. This has limitation
* that these registers should be configured to have access
* from APU which is default case.
*/
chipid[0] = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET);
#else
if (pm_get_chipid(chipid) != PM_RET_SUCCESS) {
return "XCZUUNKN";
}
#endif
id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
ZYNQMP_CSU_IDCODE_SVD_MASK);
id >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
ver = chipid[1] >> ZYNQMP_EFUSE_IPDISABLE_SHIFT;
for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
if (zynqmp_devices[i].id == id &&
zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK)) {
break;
}
}
if (i >= ARRAY_SIZE(zynqmp_devices)) {
switch (chipid[0]) {
case SILICON_ID_XCK24:
return "XCK24";
case SILICON_ID_XCK26:
return "XCK26";
default:
return "XCZUUNKN";
}
}
if (!zynqmp_devices[i].evexists) {
return zynqmp_devices[i].name;
}
if ((ver & ZYNQMP_PL_STATUS_MASK) != 0U) {
return zynqmp_devices[i].name;
}
len = strlen(zynqmp_devices[i].name) - 2;
for (j = 0; j < strlen(name); j++) {
zynqmp_devices[i].name[len] = name[j];
len++;
}
zynqmp_devices[i].name[len] = '\0';
return zynqmp_devices[i].name;
}
static unsigned int zynqmp_get_rtl_ver(void)
{
uint32_t ver;
ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET);
ver &= ZYNQMP_RTL_VER_MASK;
ver >>= ZYNQMP_RTL_VER_SHIFT;
return ver;
}
static char *zynqmp_print_silicon_idcode(void)
{
uint32_t id, maskid, tmp;
id = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
tmp = id;
tmp &= ZYNQMP_CSU_IDCODE_XILINX_ID_MASK |
ZYNQMP_CSU_IDCODE_FAMILY_MASK;
maskid = ZYNQMP_CSU_IDCODE_XILINX_ID << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT |
ZYNQMP_CSU_IDCODE_FAMILY << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT;
if (tmp != maskid) {
ERROR("Incorrect XILINX IDCODE 0x%x, maskid 0x%x\n", id, maskid);
return "UNKN";
}
VERBOSE("Xilinx IDCODE 0x%x\n", id);
return zynqmp_get_silicon_idcode_name();
}
static uint32_t zynqmp_get_ps_ver(void)
{
uint32_t ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET);
ver &= ZYNQMP_PS_VER_MASK;
ver >>= ZYNQMP_PS_VER_SHIFT;
return ver + 1U;
}
static void zynqmp_print_platform_name(void)
{
uint32_t ver = zynqmp_get_silicon_ver();
uint32_t rtl = zynqmp_get_rtl_ver();
char *label = "Unknown";
switch (ver) {
case ZYNQMP_CSU_VERSION_QEMU:
label = "QEMU";
break;
case ZYNQMP_CSU_VERSION_SILICON:
label = "silicon";
break;
default:
/* Do nothing in default case */
break;
}
VERBOSE("TF-A running on %s/%s at 0x%x\n",
zynqmp_print_silicon_idcode(), label, BL31_BASE);
VERBOSE("TF-A running on v%d/RTL%d.%d\n",
zynqmp_get_ps_ver(), (rtl & 0xf0) >> 4, rtl & 0xf);
}
#else
static inline void zynqmp_print_platform_name(void) { }
#endif
uint32_t zynqmp_get_bootmode(void)
{
uint32_t r;
unsigned int ret;
ret = pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r);
if (ret != PM_RET_SUCCESS) {
r = mmio_read_32(CRL_APB_BOOT_MODE_USER);
}
return r & CRL_APB_BOOT_MODE_MASK;
}
void zynqmp_config_setup(void)
{
uint64_t counter_freq;
/* Configure IPI data for ZynqMP */
zynqmp_ipi_config_table_init();
zynqmp_print_platform_name();
/* Configure counter frequency */
counter_freq = read_cntfrq_el0();
if (counter_freq == ZYNQMP_DEFAULT_COUNTER_FREQ) {
write_cntfrq_el0(plat_get_syscnt_freq2());
}
generic_delay_timer_init();
}
uint32_t plat_get_syscnt_freq2(void)
{
uint32_t ver = zynqmp_get_silicon_ver();
if (ver == ZYNQMP_CSU_VERSION_QEMU) {
return 65000000;
} else {
return mmio_read_32(IOU_SCNTRS_BASEFREQ);
}
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S
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/*
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm_macros.S>
#include <drivers/arm/gicv2.h>
#include <platform_def.h>
.globl plat_secondary_cold_boot_setup
.globl plat_is_my_cpu_primary
.globl zynqmp_calc_core_pos
.globl plat_my_core_pos
.globl platform_mem_init
/* -----------------------------------------------------
* void plat_secondary_cold_boot_setup (void);
*
* This function performs any platform specific actions
* needed for a secondary cpu after a cold reset e.g
* mark the cpu's presence, mechanism to place it in a
* holding pen etc.
* TODO: Should we read the PSYS register to make sure
* that the request has gone through.
* -----------------------------------------------------
*/
func plat_secondary_cold_boot_setup
mrs x0, mpidr_el1
/* Deactivate the gic cpu interface */
ldr x1, =BASE_GICC_BASE
mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
str w0, [x1, #GICC_CTLR]
/*
* There is no sane reason to come out of this wfi. This
* cpu will be powered on and reset by the cpu_on pm api
*/
dsb sy
1:
no_ret plat_panic_handler
endfunc plat_secondary_cold_boot_setup
func plat_is_my_cpu_primary
mov x9, x30
bl plat_my_core_pos
cmp x0, #ZYNQMP_PRIMARY_CPU
cset x0, eq
ret x9
endfunc plat_is_my_cpu_primary
/* -----------------------------------------------------
* unsigned int plat_my_core_pos(void)
* This function uses the zynqmp_calc_core_pos()
* definition to get the index of the calling CPU.
* -----------------------------------------------------
*/
func plat_my_core_pos
mrs x0, mpidr_el1
b zynqmp_calc_core_pos
endfunc plat_my_core_pos
/* -----------------------------------------------------
* unsigned int zynqmp_calc_core_pos(u_register_t mpidr)
* Helper function to calculate the core position.
* With this function: CorePos = (ClusterId * 4) +
* CoreId
* -----------------------------------------------------
*/
func zynqmp_calc_core_pos
and x1, x0, #MPIDR_CPU_MASK
and x0, x0, #MPIDR_CLUSTER_MASK
add x0, x1, x0, LSR #6
ret
endfunc zynqmp_calc_core_pos
/* ---------------------------------------------------------------------
* We don't need to carry out any memory initialization on ARM
* platforms. The Secure RAM is accessible straight away.
* ---------------------------------------------------------------------
*/
func platform_mem_init
ret
endfunc platform_mem_init
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
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/*
* Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <errno.h>
#include <bl31/bl31.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/arm/dcc.h>
#include <drivers/console.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <lib/mmio.h>
#include <plat_startup.h>
#include <plat_private.h>
#include <zynqmp_def.h>
#include <common/fdt_fixup.h>
#include <common/fdt_wrappers.h>
#include <libfdt.h>
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
/*
* Return a pointer to the 'entry_point_info' structure of the next image for
* the security state specified. BL33 corresponds to the non-secure image type
* while BL32 corresponds to the secure image type. A NULL pointer is returned
* if the image does not exist.
*/
struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
{
entry_point_info_t *next_image_info;
assert(sec_state_is_valid(type));
if (type == NON_SECURE) {
next_image_info = &bl33_image_ep_info;
} else {
next_image_info = &bl32_image_ep_info;
}
return next_image_info;
}
/*
* Set the build time defaults. We want to do this when doing a JTAG boot
* or if we can't find any other config data.
*/
static inline void bl31_set_default_config(void)
{
bl32_image_ep_info.pc = BL32_BASE;
bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
}
/*
* Perform any BL31 specific platform actions. Here is an opportunity to copy
* parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
* are lost (potentially). This needs to be done before the MMU is initialized
* so that the memory layout can be used while creating page tables.
*/
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
uint64_t atf_handoff_addr;
if (ZYNQMP_CONSOLE_IS(cadence) || (ZYNQMP_CONSOLE_IS(cadence1))) {
/* Register the console to provide early debug support */
static console_t bl31_boot_console;
(void)console_cdns_register(ZYNQMP_UART_BASE,
zynqmp_get_uart_clk(),
ZYNQMP_UART_BAUDRATE,
&bl31_boot_console);
console_set_scope(&bl31_boot_console,
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT);
} else if (ZYNQMP_CONSOLE_IS(dcc)) {
/* Initialize the dcc console for debug */
int32_t rc = console_dcc_register();
if (rc == 0) {
panic();
}
} else {
ERROR("BL31: No console device found.\n");
}
/* Initialize the platform config for future decision making */
zynqmp_config_setup();
/* There are no parameters from BL2 if BL31 is a reset vector */
assert(arg0 == 0U);
assert(arg1 == 0U);
/*
* Do initial security configuration to allow DRAM/device access. On
* Base ZYNQMP only DRAM security is programmable (via TrustZone), but
* other platforms might have more programmable security devices
* present.
*/
/* Populate common information for BL32 and BL33 */
SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
atf_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6);
if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) {
bl31_set_default_config();
} else {
/* use parameters from FSBL */
enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info,
&bl33_image_ep_info,
atf_handoff_addr);
if (ret == FSBL_HANDOFF_NO_STRUCT) {
bl31_set_default_config();
} else if (ret != FSBL_HANDOFF_SUCCESS) {
panic();
}
}
if (bl32_image_ep_info.pc != 0) {
VERBOSE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
}
if (bl33_image_ep_info.pc != 0) {
VERBOSE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
}
}
#if ZYNQMP_WDT_RESTART
static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3];
int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
{
/* Validate 'handler' and 'id' parameters */
if (!handler || id >= MAX_INTR_EL3) {
return -EINVAL;
}
/* Check if a handler has already been registered */
if (type_el3_interrupt_table[id]) {
return -EALREADY;
}
type_el3_interrupt_table[id] = handler;
return 0;
}
static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
void *handle, void *cookie)
{
uint32_t intr_id;
interrupt_type_handler_t handler;
intr_id = plat_ic_get_pending_interrupt_id();
handler = type_el3_interrupt_table[intr_id];
if (handler != NULL) {
handler(intr_id, flags, handle, cookie);
}
return 0;
}
#endif
#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
static void prepare_dtb(void)
{
void *dtb = (void *)XILINX_OF_BOARD_DTB_ADDR;
int ret;
/* Return if no device tree is detected */
if (fdt_check_header(dtb) != 0) {
NOTICE("Can't read DT at %p\n", dtb);
return;
}
ret = fdt_open_into(dtb, dtb, XILINX_OF_BOARD_DTB_MAX_SIZE);
if (ret < 0) {
ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret);
return;
}
if (dt_add_psci_node(dtb)) {
ERROR("Failed to add PSCI Device Tree node\n");
return;
}
if (dt_add_psci_cpu_enable_methods(dtb)) {
ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
return;
}
/* Reserve memory used by Trusted Firmware. */
if (fdt_add_reserved_memory(dtb, "tf-a", BL31_BASE, BL31_LIMIT - BL31_BASE)) {
WARN("Failed to add reserved memory nodes to DT.\n");
}
ret = fdt_pack(dtb);
if (ret < 0) {
ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret);
}
clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb));
INFO("Changed device tree to advertise PSCI and reserved memories.\n");
}
#endif
void bl31_platform_setup(void)
{
#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
prepare_dtb();
#endif
/* Initialize the gic cpu and distributor interfaces */
plat_arm_gic_driver_init();
plat_arm_gic_init();
}
void bl31_plat_runtime_setup(void)
{
#if ZYNQMP_WDT_RESTART
uint64_t flags = 0;
uint64_t rc;
set_interrupt_rm_flag(flags, NON_SECURE);
rc = register_interrupt_type_handler(INTR_TYPE_EL3,
rdo_el3_interrupt_handler, flags);
if (rc) {
panic();
}
#endif
}
/*
* Perform the very early platform specific architectural setup here.
*/
void bl31_plat_arch_setup(void)
{
plat_arm_interconnect_init();
plat_arm_interconnect_enter_coherency();
const mmap_region_t bl_regions[] = {
#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE,
MT_MEMORY | MT_RW | MT_NS),
#endif
MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
MT_MEMORY | MT_RW | MT_SECURE),
MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE),
MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
MT_RO_DATA | MT_SECURE),
MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
MT_DEVICE | MT_RW | MT_SECURE),
{0}
};
setup_page_tables(bl_regions, plat_arm_get_mmap());
enable_mmu_el3(0);
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/include/plat_ipi.h
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/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* ZynqMP IPI management enums and defines */
#ifndef PLAT_IPI_H
#define PLAT_IPI_H
#include <stdint.h>
#include <ipi.h>
/*********************************************************************
* IPI agent IDs macros
********************************************************************/
#define IPI_ID_APU 0U
#define IPI_ID_RPU0 1U
#define IPI_ID_RPU1 2U
#define IPI_ID_PMU0 3U
#define IPI_ID_PMU1 4U
#define IPI_ID_PMU2 5U
#define IPI_ID_PMU3 6U
#define IPI_ID_PL0 7U
#define IPI_ID_PL1 8U
#define IPI_ID_PL2 9U
#define IPI_ID_PL3 10U
/*********************************************************************
* IPI message buffers
********************************************************************/
#define IPI_BUFFER_BASEADDR 0xFF990000U
#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U)
#define IPI_BUFFER_PMU_BASE (IPI_BUFFER_BASEADDR + 0xE00U)
#define IPI_BUFFER_LOCAL_BASE IPI_BUFFER_APU_BASE
#define IPI_BUFFER_REMOTE_BASE IPI_BUFFER_PMU_BASE
#define IPI_BUFFER_TARGET_LOCAL_OFFSET 0x80U
#define IPI_BUFFER_TARGET_REMOTE_OFFSET 0x1C0U
#define IPI_BUFFER_MAX_WORDS 8U
#define IPI_BUFFER_REQ_OFFSET 0x0U
#define IPI_BUFFER_RESP_OFFSET 0x20U
/*********************************************************************
* Platform specific IPI API declarations
********************************************************************/
/* Configure IPI table for zynqmp */
void zynqmp_ipi_config_table_init(void);
#endif /* PLAT_IPI_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/include/plat_macros.S
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/*
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLAT_MACROS_S
#define PLAT_MACROS_S
#include <arm_macros.S>
#include <cci_macros.S>
#include "zynqmp_def.h"
/* ---------------------------------------------
* The below required platform porting macro
* prints out relevant GIC and CCI registers
* whenever an unhandled exception is taken in
* BL31.
* Clobbers: x0 - x10, x16, x17, sp
* ---------------------------------------------
*/
.macro plat_crash_print_regs
mov_imm x17, BASE_GICC_BASE
mov_imm x16, BASE_GICD_BASE
arm_print_gic_regs
print_cci_regs
.endm
#endif /* PLAT_MACROS_S */
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/include/plat_pm_common.h
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/*
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* Contains platform specific definitions of commonly used macros data types
* for PU Power Management. This file should be common for all PU's.
*/
#ifndef PLAT_PM_COMMON_H
#define PLAT_PM_COMMON_H
#include <stdint.h>
#include <common/debug.h>
#include "pm_defs.h"
#define ZYNQMP_TZ_VERSION_MAJOR 1
#define ZYNQMP_TZ_VERSION_MINOR 0
#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
ZYNQMP_TZ_VERSION_MINOR)
#endif /* _PLAT_PM_COMMON_H_ */
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/include/plat_private.h
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/*
* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLAT_PRIVATE_H
#define PLAT_PRIVATE_H
#include <stdint.h>
#include <bl31/interrupt_mgmt.h>
#include <common/bl_common.h>
#include <drivers/cadence/cdns_uart.h>
void zynqmp_config_setup(void);
uint32_t zynqmp_calc_core_pos(u_register_t mpidr);
/* ZynqMP specific functions */
uint32_t zynqmp_get_uart_clk(void);
uint32_t zynqmp_get_bootmode(void);
#if ZYNQMP_WDT_RESTART
/*
* Register handler to specific GIC entrance
* for INTR_TYPE_EL3 type of interrupt
*/
int request_intr_type_el3(uint32_t, interrupt_type_handler_t);
#endif
#endif /* PLAT_PRIVATE_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/include/platform_def.h
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/*
* Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
#include <arch.h>
#include <common/interrupt_props.h>
#include <drivers/arm/gic_common.h>
#include <lib/utils_def.h>
#include "zynqmp_def.h"
/*******************************************************************************
* Generic platform constants
******************************************************************************/
/* Size of cacheable stacks */
#define PLATFORM_STACK_SIZE 0x440
#define PLATFORM_CORE_COUNT U(4)
#define PLAT_NUM_POWER_DOMAINS U(5)
#define PLAT_MAX_PWR_LVL U(1)
#define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE U(2)
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
/*
* Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
* present). BL31_BASE is calculated using the current BL31 debug size plus a
* little space for growth.
*/
#ifndef ZYNQMP_ATF_MEM_BASE
#if !DEBUG && defined(SPD_none) && !SDEI_SUPPORT
# define BL31_BASE U(0xfffea000)
# define BL31_LIMIT U(0x100000000)
#else
# define BL31_BASE U(0xfffe5000)
# define BL31_LIMIT U(0x100000000)
#endif
#else
# define BL31_BASE (ZYNQMP_ATF_MEM_BASE)
# define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1)
# ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE
# define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1)
# endif
#endif
/*******************************************************************************
* BL32 specific defines.
******************************************************************************/
#ifndef ZYNQMP_BL32_MEM_BASE
# define BL32_BASE U(0x60000000)
# define BL32_LIMIT U(0x7fffffff)
#else
# define BL32_BASE (ZYNQMP_BL32_MEM_BASE)
# define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1)
#endif
/*******************************************************************************
* BL33 specific defines.
******************************************************************************/
#ifndef PRELOADED_BL33_BASE
# define PLAT_ARM_NS_IMAGE_BASE U(0x8000000)
#else
# define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE
#endif
/*******************************************************************************
* TSP specific defines.
******************************************************************************/
#define TSP_SEC_MEM_BASE BL32_BASE
#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
/* ID of the secure physical generic timer interrupt used by the TSP */
#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define XILINX_OF_BOARD_DTB_ADDR U(0x100000)
#define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000)
#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
#define MAX_MMAP_REGIONS 8
#define MAX_XLAT_TABLES 6
#else
#define MAX_MMAP_REGIONS 7
#define MAX_XLAT_TABLES 5
#endif
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
#define ZYNQMP_SDEI_SGI_PRIVATE U(8)
/* Platform macros to support exception handling framework */
#define PLAT_PRI_BITS U(3)
#define PLAT_SDEI_CRITICAL_PRI 0x10
#define PLAT_SDEI_NORMAL_PRI 0x20
#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
/*
* Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
* terminology. On a GICv2 system or mode, the lists will be merged and treated
* as Group 0 interrupts.
*/
#if !ZYNQMP_WDT_RESTART
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE)
#else
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE)
#endif
#define PLAT_ARM_G0_IRQ_PROPS(grp) \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \
GIC_INTR_CFG_EDGE)
#endif /* PLATFORM_DEF_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/include/zynqmp_def.h
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/*
* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef ZYNQMP_DEF_H
#define ZYNQMP_DEF_H
#include <plat/arm/common/smccc_def.h>
#include <plat/common/common_def.h>
#define ZYNQMP_CONSOLE_ID_cadence 1
#define ZYNQMP_CONSOLE_ID_cadence0 1
#define ZYNQMP_CONSOLE_ID_cadence1 2
#define ZYNQMP_CONSOLE_ID_dcc 3
#define ZYNQMP_CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE)
/* Default counter frequency */
#define ZYNQMP_DEFAULT_COUNTER_FREQ 0U
/* Firmware Image Package */
#define ZYNQMP_PRIMARY_CPU 0
/* Memory location options for Shared data and TSP in ZYNQMP */
#define ZYNQMP_IN_TRUSTED_SRAM 0
#define ZYNQMP_IN_TRUSTED_DRAM 1
/*******************************************************************************
* ZYNQMP memory map related constants
******************************************************************************/
/* Aggregate of all devices in the first GB */
#define DEVICE0_BASE U(0xFF000000)
#define DEVICE0_SIZE U(0x00E00000)
#define DEVICE1_BASE U(0xF9000000)
#define DEVICE1_SIZE U(0x00800000)
/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
#define CRF_APB_BASE U(0xFD1A0000)
#define CRF_APB_SIZE U(0x00600000)
#define CRF_APB_CLK_BASE U(0xFD1A0020)
/* CRF registers and bitfields */
#define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104)
#define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0)
#define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10)
/* CRL registers and bitfields */
#define CRL_APB_BASE U(0xFF5E0000)
#define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200)
#define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218)
#define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C)
#define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250))
#define CRL_APB_CLK_BASE U(0xFF5E0020)
#define CRL_APB_RPU_AMBA_RESET (U(1) << 2)
#define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3)
#define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4)
#define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0)
#define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0)
#define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9)
#define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1)
#define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << \
CRL_APB_BOOT_ENABLE_PIN_1_SHIFT)
#define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << \
CRL_APB_BOOT_DRIVE_PIN_1_SHIFT)
#define ZYNQMP_BOOTMODE_JTAG U(0)
#define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | \
CRL_APB_BOOT_DRIVE_PIN_1)
#define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1
/* system counter registers and bitfields */
#define IOU_SCNTRS_BASE U(0xFF260000)
#define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20)
/* APU registers and bitfields */
#define APU_BASE U(0xFD5C0000)
#define APU_CONFIG_0 (APU_BASE + 0x20)
#define APU_RVBAR_L_0 (APU_BASE + 0x40)
#define APU_RVBAR_H_0 (APU_BASE + 0x44)
#define APU_PWRCTL (APU_BASE + 0x90)
#define APU_CONFIG_0_VINITHI_SHIFT 8
#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1
#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2
#define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4
#define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8
/* PMU registers and bitfields */
#define PMU_GLOBAL_BASE U(0xFFD80000)
#define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0)
#define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48)
#define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110)
#define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118)
#define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c)
#define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120)
#define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4)
/*******************************************************************************
* CCI-400 related constants
******************************************************************************/
#define PLAT_ARM_CCI_BASE U(0xFD6E0000)
#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3
#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4
/*******************************************************************************
* GIC-400 & interrupt handling related constants
******************************************************************************/
#define BASE_GICD_BASE U(0xF9010000)
#define BASE_GICC_BASE U(0xF9020000)
#define BASE_GICH_BASE U(0xF9040000)
#define BASE_GICV_BASE U(0xF9060000)
#if ZYNQMP_WDT_RESTART
#define IRQ_SEC_IPI_APU 67
#define IRQ_TTC3_1 77
#define TTC3_BASE_ADDR U(0xFF140000)
#define TTC3_INTR_REGISTER_1 (TTC3_BASE_ADDR + 0x54)
#define TTC3_INTR_ENABLE_1 (TTC3_BASE_ADDR + 0x60)
#endif
#define ARM_IRQ_SEC_PHY_TIMER 29
#define ARM_IRQ_SEC_SGI_0 8
#define ARM_IRQ_SEC_SGI_1 9
#define ARM_IRQ_SEC_SGI_2 10
#define ARM_IRQ_SEC_SGI_3 11
#define ARM_IRQ_SEC_SGI_4 12
#define ARM_IRQ_SEC_SGI_5 13
#define ARM_IRQ_SEC_SGI_6 14
#define ARM_IRQ_SEC_SGI_7 15
#define MAX_INTR_EL3 128
/*******************************************************************************
* UART related constants
******************************************************************************/
#define ZYNQMP_UART0_BASE U(0xFF000000)
#define ZYNQMP_UART1_BASE U(0xFF010000)
#if ZYNQMP_CONSOLE_IS(cadence) || ZYNQMP_CONSOLE_IS(dcc)
# define ZYNQMP_UART_BASE ZYNQMP_UART0_BASE
#elif ZYNQMP_CONSOLE_IS(cadence1)
# define ZYNQMP_UART_BASE ZYNQMP_UART1_BASE
#else
# error "invalid ZYNQMP_CONSOLE"
#endif
#define ZYNQMP_CRASH_UART_BASE ZYNQMP_UART_BASE
/* impossible to call C routine how it is done now - hardcode any value */
#define ZYNQMP_CRASH_UART_CLK_IN_HZ 100000000 /* FIXME */
/* Must be non zero */
#define ZYNQMP_UART_BAUDRATE 115200
/* Silicon version detection */
#define ZYNQMP_SILICON_VER_MASK 0xF000
#define ZYNQMP_SILICON_VER_SHIFT 12
#define ZYNQMP_CSU_VERSION_SILICON 0
#define ZYNQMP_CSU_VERSION_QEMU 3
#define ZYNQMP_RTL_VER_MASK 0xFF0U
#define ZYNQMP_RTL_VER_SHIFT 4
#define ZYNQMP_PS_VER_MASK 0xFU
#define ZYNQMP_PS_VER_SHIFT 0
#define ZYNQMP_CSU_BASEADDR U(0xFFCA0000)
#define ZYNQMP_CSU_IDCODE_OFFSET 0x40U
#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0U
#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFFU << \
ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT)
#define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093
#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12U
#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7U << \
ZYNQMP_CSU_IDCODE_SVD_SHIFT)
#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15U
#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xFU << \
ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19U
#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3U << \
ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT)
#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21U
#define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7FU << \
ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
#define ZYNQMP_CSU_IDCODE_FAMILY 0x23
#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28U
#define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xFU << \
ZYNQMP_CSU_IDCODE_REVISION_SHIFT)
#define ZYNQMP_CSU_IDCODE_REVISION 0U
#define ZYNQMP_CSU_VERSION_OFFSET 0x44U
/* Efuse */
#define EFUSE_BASEADDR U(0xFFCC0000)
#define EFUSE_IPDISABLE_OFFSET 0x1018
#define EFUSE_IPDISABLE_VERSION 0x1FFU
#define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20
/* Access control register defines */
#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
#define FPD_SLCR_BASEADDR U(0xFD610000)
#define IOU_SLCR_BASEADDR U(0xFF180000)
#define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000)
#define ZYNQMP_RPU0_CFG U(0xFF9A0100)
#define ZYNQMP_RPU1_CFG U(0xFF9A0200)
#define ZYNQMP_SLSPLIT_MASK U(0x08)
#define ZYNQMP_TCM_COMB_MASK U(0x40)
#define ZYNQMP_SLCLAMP_MASK U(0x10)
#define ZYNQMP_VINITHI_MASK U(0x04)
/* Tap delay bypass */
#define IOU_TAPDLY_BYPASS U(0XFF180390)
#define TAP_DELAY_MASK U(0x7)
/* SGMII mode */
#define IOU_GEM_CTRL U(0xFF180360)
#define IOU_GEM_CLK_CTRL U(0xFF180308)
#define SGMII_SD_MASK U(0x3)
#define SGMII_SD_OFFSET U(2)
#define SGMII_PCS_SD_0 U(0x0)
#define SGMII_PCS_SD_1 U(0x1)
#define SGMII_PCS_SD_PHY U(0x2)
#define GEM_SGMII_MASK U(0x4)
#define GEM_CLK_CTRL_MASK U(0xF)
#define GEM_CLK_CTRL_OFFSET U(5)
#define GEM_RX_SRC_SEL_GTR U(0x1)
#define GEM_SGMII_MODE U(0x4)
/* SD DLL reset */
#define ZYNQMP_SD_DLL_CTRL U(0xFF180358)
#define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004)
#define ZYNQMP_SD0_DLL_RST U(0x00000004)
#define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000)
#define ZYNQMP_SD1_DLL_RST U(0x00040000)
/* SD tap delay */
#define ZYNQMP_SD_DLL_CTRL U(0xFF180358)
#define ZYNQMP_SD_ITAP_DLY U(0xFF180314)
#define ZYNQMP_SD_OTAP_DLY U(0xFF180318)
#define ZYNQMP_SD_TAP_OFFSET U(16)
#define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200)
#define ZYNQMP_SD_ITAPCHGWIN U(0x200)
#define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100)
#define ZYNQMP_SD_ITAPDLYENA U(0x100)
#define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF)
#define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F)
#define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40)
#define ZYNQMP_SD_OTAPDLYENA U(0x40)
/* Clock control registers */
/* Full power domain clocks */
#define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00)
#define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c)
#define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18)
#define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24)
#define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28)
#define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c)
#define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30)
/* Peripheral clocks */
#define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40)
#define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44)
#define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48)
#define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50)
#define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54)
#define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c)
#define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60)
#define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64)
#define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80)
#define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94)
#define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98)
#define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c)
#define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0)
#define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4)
#define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8)
#define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8)
/* Low power domain clocks */
#define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00)
#define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10)
#define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20)
#define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24)
#define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28)
/* Peripheral clocks */
#define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c)
#define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30)
#define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34)
#define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38)
#define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c)
#define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40)
#define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44)
#define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48)
#define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c)
#define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50)
#define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54)
#define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58)
#define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c)
#define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60)
#define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64)
#define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68)
#define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70)
#define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c)
#define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80)
#define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84)
#define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88)
#define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c)
#define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90)
#define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94)
#define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98)
#define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0)
#define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4)
#define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8)
#define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac)
#define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4)
#define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc)
#define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4)
#define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc)
#define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0)
#define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4)
#define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8)
#define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100)
#define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104)
#define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108)
#define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308)
#define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304)
#define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100)
#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300)
/* Global general storage register base address */
#define GGS_BASEADDR (0xFFD80030U)
#define GGS_NUM_REGS U(4)
/* Persistent global general storage register base address */
#define PGGS_BASEADDR (0xFFD80050U)
#define PGGS_NUM_REGS U(4)
/* PMU GGS4 register 4 is used for warm restart boot health status */
#define PMU_GLOBAL_GEN_STORAGE4 (GGS_BASEADDR + 0x10)
/* Warm restart boot health status mask */
#define PM_BOOT_HEALTH_STATUS_MASK U(0x01)
/* WDT restart scope shift and mask */
#define RESTART_SCOPE_SHIFT (3)
#define RESTART_SCOPE_MASK (0x3U << RESTART_SCOPE_SHIFT)
/* AFI registers */
#define AFIFM6_WRCTRL U(13)
#define FABRIC_WIDTH U(3)
/* CSUDMA Module Base Address*/
#define CSUDMA_BASE U(0xFFC80000)
/* RSA-CORE Module Base Address*/
#define RSA_CORE_BASE U(0xFFCE0000)
#endif /* ZYNQMP_DEF_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/plat_psci.c
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/*
* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <errno.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/arm/gicv2.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <plat_private.h>
#include "pm_api_sys.h"
#include "pm_client.h"
static uintptr_t zynqmp_sec_entry;
static void zynqmp_cpu_standby(plat_local_state_t cpu_state)
{
VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state);
dsb();
wfi();
}
static int32_t zynqmp_pwr_domain_on(u_register_t mpidr)
{
uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
const struct pm_proc *proc;
uint32_t buff[3];
enum pm_ret_status ret;
VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
if (cpu_id == -1) {
return PSCI_E_INTERN_FAIL;
}
proc = pm_get_proc(cpu_id);
/* Check the APU proc status before wakeup */
ret = pm_get_node_status(proc->node_id, buff);
if ((ret != PM_RET_SUCCESS) || (buff[0] == PM_PROC_STATE_SUSPENDING)) {
return PSCI_E_INTERN_FAIL;
}
/* Clear power down request */
pm_client_wakeup(proc);
/* Send request to PMU to wake up selected APU CPU core */
pm_req_wakeup(proc->node_id, 1, zynqmp_sec_entry, REQ_ACK_BLOCKING);
return PSCI_E_SUCCESS;
}
static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state)
{
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
}
/* Prevent interrupts from spuriously waking up this cpu */
gicv2_cpuif_disable();
/*
* Send request to PMU to power down the appropriate APU CPU
* core.
* According to PSCI specification, CPU_off function does not
* have resume address and CPU core can only be woken up
* invoking CPU_on function, during which resume address will
* be set.
*/
pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0);
}
static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state)
{
uint32_t state;
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ?
PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
/* Send request to PMU to suspend this core */
pm_self_suspend(proc->node_id, MAX_LATENCY, state, zynqmp_sec_entry);
/* APU is to be turned off */
if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
/* disable coherency */
plat_arm_interconnect_exit_coherency();
}
}
static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
}
plat_arm_gic_pcpu_init();
gicv2_cpuif_enable();
}
static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
{
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
}
/* Clear the APU power control register for this cpu */
pm_client_wakeup(proc);
/* enable coherency */
plat_arm_interconnect_enter_coherency();
/* APU was turned off */
if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
plat_arm_gic_init();
} else {
gicv2_cpuif_enable();
gicv2_pcpu_distif_init();
}
}
/*******************************************************************************
* ZynqMP handlers to shutdown/reboot the system
******************************************************************************/
static void __dead2 zynqmp_system_off(void)
{
/* disable coherency */
plat_arm_interconnect_exit_coherency();
/* Send the power down request to the PMU */
pm_system_shutdown(PMF_SHUTDOWN_TYPE_SHUTDOWN,
pm_get_shutdown_scope());
while (1) {
wfi();
}
}
static void __dead2 zynqmp_system_reset(void)
{
/* disable coherency */
plat_arm_interconnect_exit_coherency();
/* Send the system reset request to the PMU */
pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET,
pm_get_shutdown_scope());
while (1) {
wfi();
}
}
static int32_t zynqmp_validate_power_state(uint32_t power_state,
psci_power_state_t *req_state)
{
VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
uint32_t pstate = psci_get_pstate_type(power_state);
assert(req_state);
/* Sanity check the requested state */
if (pstate == PSTATE_TYPE_STANDBY) {
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
} else {
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
}
/* We expect the 'state id' to be zero */
if (psci_get_pstate_id(power_state)) {
return PSCI_E_INVALID_PARAMS;
}
return PSCI_E_SUCCESS;
}
static void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state)
{
req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE;
}
/*******************************************************************************
* Export the platform handlers to enable psci to invoke them
******************************************************************************/
static const struct plat_psci_ops zynqmp_psci_ops = {
.cpu_standby = zynqmp_cpu_standby,
.pwr_domain_on = zynqmp_pwr_domain_on,
.pwr_domain_off = zynqmp_pwr_domain_off,
.pwr_domain_suspend = zynqmp_pwr_domain_suspend,
.pwr_domain_on_finish = zynqmp_pwr_domain_on_finish,
.pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish,
.system_off = zynqmp_system_off,
.system_reset = zynqmp_system_reset,
.validate_power_state = zynqmp_validate_power_state,
.get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state,
};
/*******************************************************************************
* Export the platform specific power ops.
******************************************************************************/
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
const struct plat_psci_ops **psci_ops)
{
zynqmp_sec_entry = sec_entrypoint;
*psci_ops = &zynqmp_psci_ops;
return 0;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/plat_topology.c
+13
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/*
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
static const uint8_t plat_power_domain_tree_desc[] = {1, 4};
const uint8_t *plat_get_power_domain_tree_desc(void)
{
return plat_power_domain_tree_desc;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/plat_zynqmp.c
+21
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/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat_private.h>
#include <plat/common/platform.h>
int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
{
if (mpidr & MPIDR_CLUSTER_MASK) {
return -1;
}
if ((mpidr & MPIDR_CPU_MASK) >= PLATFORM_CORE_COUNT) {
return -1;
}
return zynqmp_calc_core_pos(mpidr);
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/platform.mk
+144
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#
# Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
# Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
override ERRATA_A53_855873 := 1
ERRATA_A53_1530924 := 1
override PROGRAMMABLE_RESET_ADDRESS := 1
PSCI_EXTENDED_STATE_ID := 1
A53_DISABLE_NON_TEMPORAL_HINT := 0
SEPARATE_CODE_AND_RODATA := 1
ZYNQMP_WDT_RESTART := 0
IPI_CRC_CHECK := 0
override RESET_TO_BL31 := 1
override WARMBOOT_ENABLE_DCACHE_EARLY := 1
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
# pncd SPD requires secure SGI to be handled at EL1
ifeq (${SPD},pncd)
ifeq (${ZYNQMP_WDT_RESTART},1)
$(error "Error: ZYNQMP_WDT_RESTART and SPD=pncd are incompatible")
endif
override GICV2_G0_FOR_EL3 := 0
else
override GICV2_G0_FOR_EL3 := 1
endif
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
WORKAROUND_CVE_2017_5715 := 0
ARM_XLAT_TABLES_LIB_V1 := 1
$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1))
$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1))
ifdef ZYNQMP_ATF_MEM_BASE
$(eval $(call add_define,ZYNQMP_ATF_MEM_BASE))
ifndef ZYNQMP_ATF_MEM_SIZE
$(error "ZYNQMP_ATF_BASE defined without ZYNQMP_ATF_SIZE")
endif
$(eval $(call add_define,ZYNQMP_ATF_MEM_SIZE))
ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE
$(eval $(call add_define,ZYNQMP_ATF_MEM_PROGBITS_SIZE))
endif
endif
ifdef ZYNQMP_BL32_MEM_BASE
$(eval $(call add_define,ZYNQMP_BL32_MEM_BASE))
ifndef ZYNQMP_BL32_MEM_SIZE
$(error "ZYNQMP_BL32_BASE defined without ZYNQMP_BL32_SIZE")
endif
$(eval $(call add_define,ZYNQMP_BL32_MEM_SIZE))
endif
ifdef ZYNQMP_WDT_RESTART
$(eval $(call add_define,ZYNQMP_WDT_RESTART))
endif
ifdef ZYNQMP_IPI_CRC_CHECK
$(warning "ZYNQMP_IPI_CRC_CHECK macro is deprecated...instead please use IPI_CRC_CHECK.")
endif
ifdef IPI_CRC_CHECK
$(eval $(call add_define,IPI_CRC_CHECK))
endif
ifdef ZYNQMP_SECURE_EFUSES
$(eval $(call add_define,ZYNQMP_SECURE_EFUSES))
endif
PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
-Iinclude/plat/arm/common/aarch64/ \
-Iplat/xilinx/common/include/ \
-Iplat/xilinx/common/ipi_mailbox_service/ \
-Iplat/xilinx/zynqmp/include/ \
-Iplat/xilinx/zynqmp/pm_service/ \
include lib/libfdt/libfdt.mk
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
lib/xlat_tables/aarch64/xlat_tables.c \
drivers/arm/dcc/dcc_console.c \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
${GICV2_SOURCES} \
drivers/cadence/uart/aarch64/cdns_console.S \
plat/arm/common/arm_cci.c \
plat/arm/common/arm_common.c \
plat/arm/common/arm_gicv2.c \
plat/common/plat_gicv2.c \
plat/xilinx/common/ipi.c \
plat/xilinx/zynqmp/zynqmp_ipi.c \
plat/common/aarch64/crash_console_helpers.S \
plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S \
plat/xilinx/zynqmp/aarch64/zynqmp_common.c
ZYNQMP_CONSOLE ?= cadence
ifeq (${ZYNQMP_CONSOLE}, $(filter ${ZYNQMP_CONSOLE},cadence cadence0 cadence1 dcc))
else
$(error "Please define ZYNQMP_CONSOLE")
endif
$(eval $(call add_define_val,ZYNQMP_CONSOLE,ZYNQMP_CONSOLE_ID_${ZYNQMP_CONSOLE}))
BL31_SOURCES += drivers/arm/cci/cci.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
plat/common/plat_psci_common.c \
common/fdt_fixup.c \
${LIBFDT_SRCS} \
plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
plat/xilinx/common/pm_service/pm_ipi.c \
plat/xilinx/common/plat_startup.c \
plat/xilinx/zynqmp/bl31_zynqmp_setup.c \
plat/xilinx/zynqmp/plat_psci.c \
plat/xilinx/zynqmp/plat_zynqmp.c \
plat/xilinx/zynqmp/plat_topology.c \
plat/xilinx/zynqmp/sip_svc_setup.c \
plat/xilinx/zynqmp/pm_service/pm_svc_main.c \
plat/xilinx/zynqmp/pm_service/pm_api_sys.c \
plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c \
plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c \
plat/xilinx/zynqmp/pm_service/pm_api_clock.c \
plat/xilinx/zynqmp/pm_service/pm_client.c
ifeq (${SDEI_SUPPORT},1)
BL31_SOURCES += plat/xilinx/zynqmp/zynqmp_ehf.c \
plat/xilinx/zynqmp/zynqmp_sdei.c
endif
BL31_CPPFLAGS += -fno-jump-tables
TF_CFLAGS_aarch64 += -mbranch-protection=none
ifneq (${RESET_TO_BL31},1)
$(error "Using BL31 as the reset vector is only one option supported on ZynqMP. Please set RESET_TO_BL31 to 1.")
endif
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+3048
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source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
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/*
* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* ZynqMP system level PM-API functions for clock control.
*/
#ifndef PM_API_CLOCK_H
#define PM_API_CLOCK_H
#include <lib/utils_def.h>
#include "pm_common.h"
#define CLK_NAME_LEN (15U)
#define MAX_PARENTS (100U)
#define CLK_NA_PARENT -1
#define CLK_DUMMY_PARENT -2
/* Flags for parent id */
#define PARENT_CLK_SELF (0U)
#define PARENT_CLK_NODE1 (1U)
#define PARENT_CLK_NODE2 (2U)
#define PARENT_CLK_NODE3 (3U)
#define PARENT_CLK_NODE4 (4U)
#define PARENT_CLK_EXTERNAL (5U)
#define PARENT_CLK_MIO0_MIO77 (6U)
#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
/* unused */
#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
/* parents need enable during gate/ungate, set rate and re-parent */
#define CLK_OPS_PARENT_ENABLE BIT(12)
#define CLK_DIVIDER_ONE_BASED BIT(0)
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
#define CLK_DIVIDER_HIWORD_MASK BIT(3)
#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
#define CLK_DIVIDER_READ_ONLY BIT(5)
#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
#define CLK_FRAC BIT(8)
#define END_OF_CLK "END_OF_CLK"
//CLock Ids
enum clock_id {
CLK_IOPLL = (0U),
CLK_RPLL = (1U),
CLK_APLL = (2U),
CLK_DPLL = (3U),
CLK_VPLL = (4U),
CLK_IOPLL_TO_FPD = (5U),
CLK_RPLL_TO_FPD = (6U),
CLK_APLL_TO_LPD = (7U),
CLK_DPLL_TO_LPD = (8U),
CLK_VPLL_TO_LPD = (9U),
CLK_ACPU = (10U),
CLK_ACPU_HALF = (11U),
CLK_DBG_FPD = (12U),
CLK_DBG_LPD = (13U),
CLK_DBG_TRACE = (14U),
CLK_DBG_TSTMP = (15U),
CLK_DP_VIDEO_REF = (16U),
CLK_DP_AUDIO_REF = (17U),
CLK_DP_STC_REF = (18U),
CLK_GDMA_REF = (19U),
CLK_DPDMA_REF = (20U),
CLK_DDR_REF = (21U),
CLK_SATA_REF = (22U),
CLK_PCIE_REF = (23U),
CLK_GPU_REF = (24U),
CLK_GPU_PP0_REF = (25U),
CLK_GPU_PP1_REF = (26U),
CLK_TOPSW_MAIN = (27U),
CLK_TOPSW_LSBUS = (28U),
CLK_GTGREF0_REF = (29U),
CLK_LPD_SWITCH = (30U),
CLK_LPD_LSBUS = (31U),
CLK_USB0_BUS_REF = (32U),
CLK_USB1_BUS_REF = (33U),
CLK_USB3_DUAL_REF = (34U),
CLK_USB0 = (35U),
CLK_USB1 = (36U),
CLK_CPU_R5 = (37U),
CLK_CPU_R5_CORE = (38U),
CLK_CSU_SPB = (39U),
CLK_CSU_PLL = (40U),
CLK_PCAP = (41U),
CLK_IOU_SWITCH = (42U),
CLK_GEM_TSU_REF = (43U),
CLK_GEM_TSU = (44U),
CLK_GEM0_TX = (45U),
CLK_GEM1_TX = (46U),
CLK_GEM2_TX = (47U),
CLK_GEM3_TX = (48U),
CLK_GEM0_RX = (49U),
CLK_GEM1_RX = (50U),
CLK_GEM2_RX = (51U),
CLK_GEM3_RX = (52U),
CLK_QSPI_REF = (53U),
CLK_SDIO0_REF = (54U),
CLK_SDIO1_REF = (55U),
CLK_UART0_REF = (56U),
CLK_UART1_REF = (57U),
CLK_SPI0_REF = (58U),
CLK_SPI1_REF = (59U),
CLK_NAND_REF = (60U),
CLK_I2C0_REF = (61U),
CLK_I2C1_REF = (62U),
CLK_CAN0_REF = (63U),
CLK_CAN1_REF = (64U),
CLK_CAN0 = (65U),
CLK_CAN1 = (66U),
CLK_DLL_REF = (67U),
CLK_ADMA_REF = (68U),
CLK_TIMESTAMP_REF = (69U),
CLK_AMS_REF = (70U),
CLK_PL0_REF = (71U),
CLK_PL1_REF = (72U),
CLK_PL2_REF = (73U),
CLK_PL3_REF = (74U),
CLK_FPD_WDT = (75U),
CLK_IOPLL_INT = (76U),
CLK_IOPLL_PRE_SRC = (77U),
CLK_IOPLL_HALF = (78U),
CLK_IOPLL_INT_MUX = (79U),
CLK_IOPLL_POST_SRC = (80U),
CLK_RPLL_INT = (81U),
CLK_RPLL_PRE_SRC = (82U),
CLK_RPLL_HALF = (83U),
CLK_RPLL_INT_MUX = (84U),
CLK_RPLL_POST_SRC = (85U),
CLK_APLL_INT = (86U),
CLK_APLL_PRE_SRC = (87U),
CLK_APLL_HALF = (88U),
CLK_APLL_INT_MUX = (89U),
CLK_APLL_POST_SRC = (90U),
CLK_DPLL_INT = (91U),
CLK_DPLL_PRE_SRC = (92U),
CLK_DPLL_HALF = (93U),
CLK_DPLL_INT_MUX = (94U),
CLK_DPLL_POST_SRC = (95U),
CLK_VPLL_INT = (96U),
CLK_VPLL_PRE_SRC = (97U),
CLK_VPLL_HALF = (98U),
CLK_VPLL_INT_MUX = (99U),
CLK_VPLL_POST_SRC = (100U),
CLK_CAN0_MIO = (101U),
CLK_CAN1_MIO = (102U),
CLK_ACPU_FULL = (103U),
CLK_GEM0_REF = (104U),
CLK_GEM1_REF = (105U),
CLK_GEM2_REF = (106U),
CLK_GEM3_REF = (107U),
CLK_GEM0_REF_UNGATED = (108U),
CLK_GEM1_REF_UNGATED = (109U),
CLK_GEM2_REF_UNGATED = (110U),
CLK_GEM3_REF_UNGATED = (111U),
CLK_LPD_WDT = (112U),
END_OF_OUTPUT_CLKS = (113U),
};
#define CLK_MAX_OUTPUT_CLK END_OF_OUTPUT_CLKS
//External clock ids
enum {
EXT_CLK_PSS_REF = END_OF_OUTPUT_CLKS,
EXT_CLK_VIDEO = (114U),
EXT_CLK_PSS_ALT_REF = (115U),
EXT_CLK_AUX_REF = (116U),
EXT_CLK_GT_CRX_REF = (117U),
EXT_CLK_SWDT0 = (118U),
EXT_CLK_SWDT1 = (119U),
EXT_CLK_GEM0_TX_EMIO = (120U),
EXT_CLK_GEM1_TX_EMIO = (121U),
EXT_CLK_GEM2_TX_EMIO = (122U),
EXT_CLK_GEM3_TX_EMIO = (123U),
EXT_CLK_GEM0_RX_EMIO = (124U),
EXT_CLK_GEM1_RX_EMIO = (125U),
EXT_CLK_GEM2_RX_EMIO = (126U),
EXT_CLK_GEM3_RX_EMIO = (127U),
EXT_CLK_MIO50_OR_MIO51 = (128U),
EXT_CLK_MIO0 = (129U),
EXT_CLK_MIO1 = (130U),
EXT_CLK_MIO2 = (131U),
EXT_CLK_MIO3 = (132U),
EXT_CLK_MIO4 = (133U),
EXT_CLK_MIO5 = (134U),
EXT_CLK_MIO6 = (135U),
EXT_CLK_MIO7 = (136U),
EXT_CLK_MIO8 = (137U),
EXT_CLK_MIO9 = (138U),
EXT_CLK_MIO10 = (139U),
EXT_CLK_MIO11 = (140U),
EXT_CLK_MIO12 = (141U),
EXT_CLK_MIO13 = (142U),
EXT_CLK_MIO14 = (143U),
EXT_CLK_MIO15 = (144U),
EXT_CLK_MIO16 = (145U),
EXT_CLK_MIO17 = (146U),
EXT_CLK_MIO18 = (147U),
EXT_CLK_MIO19 = (148U),
EXT_CLK_MIO20 = (149U),
EXT_CLK_MIO21 = (150U),
EXT_CLK_MIO22 = (151U),
EXT_CLK_MIO23 = (152U),
EXT_CLK_MIO24 = (153U),
EXT_CLK_MIO25 = (154U),
EXT_CLK_MIO26 = (155U),
EXT_CLK_MIO27 = (156U),
EXT_CLK_MIO28 = (157U),
EXT_CLK_MIO29 = (158U),
EXT_CLK_MIO30 = (159U),
EXT_CLK_MIO31 = (160U),
EXT_CLK_MIO32 = (161U),
EXT_CLK_MIO33 = (162U),
EXT_CLK_MIO34 = (163U),
EXT_CLK_MIO35 = (164U),
EXT_CLK_MIO36 = (165U),
EXT_CLK_MIO37 = (166U),
EXT_CLK_MIO38 = (167U),
EXT_CLK_MIO39 = (168U),
EXT_CLK_MIO40 = (169U),
EXT_CLK_MIO41 = (170U),
EXT_CLK_MIO42 = (171U),
EXT_CLK_MIO43 = (172U),
EXT_CLK_MIO44 = (173U),
EXT_CLK_MIO45 = (174U),
EXT_CLK_MIO46 = (175U),
EXT_CLK_MIO47 = (176U),
EXT_CLK_MIO48 = (177U),
EXT_CLK_MIO49 = (178U),
EXT_CLK_MIO50 = (179U),
EXT_CLK_MIO51 = (180U),
EXT_CLK_MIO52 = (181U),
EXT_CLK_MIO53 = (182U),
EXT_CLK_MIO54 = (183U),
EXT_CLK_MIO55 = (184U),
EXT_CLK_MIO56 = (185U),
EXT_CLK_MIO57 = (186U),
EXT_CLK_MIO58 = (187U),
EXT_CLK_MIO59 = (188U),
EXT_CLK_MIO60 = (189U),
EXT_CLK_MIO61 = (190U),
EXT_CLK_MIO62 = (191U),
EXT_CLK_MIO63 = (192U),
EXT_CLK_MIO64 = (193U),
EXT_CLK_MIO65 = (194U),
EXT_CLK_MIO66 = (195U),
EXT_CLK_MIO67 = (196U),
EXT_CLK_MIO68 = (197U),
EXT_CLK_MIO69 = (198U),
EXT_CLK_MIO70 = (199U),
EXT_CLK_MIO71 = (200U),
EXT_CLK_MIO72 = (201U),
EXT_CLK_MIO73 = (202U),
EXT_CLK_MIO74 = (203U),
EXT_CLK_MIO75 = (204U),
EXT_CLK_MIO76 = (205U),
EXT_CLK_MIO77 = (206U),
END_OF_CLKS = (207U),
};
#define CLK_MAX END_OF_CLKS
//CLock types
#define CLK_TYPE_OUTPUT 0U
#define CLK_TYPE_EXTERNAL 1U
//Topology types
#define TYPE_INVALID 0U
#define TYPE_MUX 1U
#define TYPE_PLL 2U
#define TYPE_FIXEDFACTOR 3U
#define TYPE_DIV1 4U
#define TYPE_DIV2 5U
#define TYPE_GATE 6U
struct pm_pll;
struct pm_pll *pm_clock_get_pll(enum clock_id clock_id);
struct pm_pll *pm_clock_get_pll_by_related_clk(enum clock_id clock_id);
uint8_t pm_clock_has_div(uint32_t clock_id, enum pm_clock_div_id div_id);
void pm_api_clock_get_name(uint32_t clock_id, char *name);
enum pm_ret_status pm_api_clock_get_num_clocks(uint32_t *nclocks);
enum pm_ret_status pm_api_clock_get_topology(uint32_t clock_id,
uint32_t index,
uint32_t *topology);
enum pm_ret_status pm_api_clock_get_fixedfactor_params(uint32_t clock_id,
uint32_t *mul,
uint32_t *div);
enum pm_ret_status pm_api_clock_get_parents(uint32_t clock_id,
uint32_t index,
uint32_t *parents);
enum pm_ret_status pm_api_clock_get_attributes(uint32_t clock_id,
uint32_t *attr);
enum pm_ret_status pm_api_clock_get_max_divisor(enum clock_id clock_id,
uint8_t div_type,
uint32_t *max_div);
enum pm_ret_status pm_clock_get_pll_node_id(enum clock_id clock_id,
enum pm_node_id *node_id);
enum pm_ret_status pm_clock_id_is_valid(uint32_t clock_id);
enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll);
enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll);
enum pm_ret_status pm_clock_pll_get_state(struct pm_pll *pll,
uint32_t *state);
enum pm_ret_status pm_clock_pll_set_parent(struct pm_pll *pll,
enum clock_id clock_id,
uint32_t parent_index);
enum pm_ret_status pm_clock_pll_get_parent(struct pm_pll *pll,
enum clock_id clock_id,
uint32_t *parent_index);
enum pm_ret_status pm_clock_set_pll_mode(enum clock_id clock_id,
uint32_t mode);
enum pm_ret_status pm_clock_get_pll_mode(enum clock_id clock_id,
uint32_t *mode);
#endif /* PM_API_CLOCK_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
+767
View File
@@ -0,0 +1,767 @@
/*
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* ZynqMP system level PM-API functions for ioctl.
*/
#include <arch_helpers.h>
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <plat/common/platform.h>
#include <zynqmp_def.h>
#include "pm_api_clock.h"
#include "pm_api_ioctl.h"
#include "pm_api_sys.h"
#include "pm_client.h"
#include "pm_common.h"
#include "pm_ipi.h"
/**
* pm_ioctl_get_rpu_oper_mode () - Get current RPU operation mode
* @mode Buffer to store value of oper mode(Split/Lock-step)
*
* This function provides current configured RPU operational mode.
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_get_rpu_oper_mode(uint32_t *mode)
{
uint32_t val;
val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL);
val &= ZYNQMP_SLSPLIT_MASK;
if (val == 0U) {
*mode = PM_RPU_MODE_LOCKSTEP;
} else {
*mode = PM_RPU_MODE_SPLIT;
}
return PM_RET_SUCCESS;
}
/**
* pm_ioctl_set_rpu_oper_mode () - Configure RPU operation mode
* @mode Value to set for oper mode(Split/Lock-step)
*
* This function configures RPU operational mode(Split/Lock-step).
* It also sets TCM combined mode in RPU lock-step and TCM non-combined
* mode for RPU split mode. In case of Lock step mode, RPU1's output is
* clamped.
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_set_rpu_oper_mode(uint32_t mode)
{
uint32_t val;
if (mmio_read_32(CRL_APB_RST_LPD_TOP) & CRL_APB_RPU_AMBA_RESET) {
return PM_RET_ERROR_ACCESS;
}
val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL);
if (mode == PM_RPU_MODE_SPLIT) {
val |= ZYNQMP_SLSPLIT_MASK;
val &= ~ZYNQMP_TCM_COMB_MASK;
val &= ~ZYNQMP_SLCLAMP_MASK;
} else if (mode == PM_RPU_MODE_LOCKSTEP) {
val &= ~ZYNQMP_SLSPLIT_MASK;
val |= ZYNQMP_TCM_COMB_MASK;
val |= ZYNQMP_SLCLAMP_MASK;
} else {
return PM_RET_ERROR_ARGS;
}
mmio_write_32(ZYNQMP_RPU_GLBL_CNTL, val);
return PM_RET_SUCCESS;
}
/**
* pm_ioctl_config_boot_addr() - Configure RPU boot address
* @nid Node ID of RPU
* @value Value to set for boot address (TCM/OCM)
*
* This function configures RPU boot address(memory).
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_config_boot_addr(enum pm_node_id nid,
uint32_t value)
{
uint32_t rpu_cfg_addr, val;
if (nid == NODE_RPU_0) {
rpu_cfg_addr = ZYNQMP_RPU0_CFG;
} else if (nid == NODE_RPU_1) {
rpu_cfg_addr = ZYNQMP_RPU1_CFG;
} else {
return PM_RET_ERROR_ARGS;
}
val = mmio_read_32(rpu_cfg_addr);
if (value == PM_RPU_BOOTMEM_LOVEC) {
val &= ~ZYNQMP_VINITHI_MASK;
} else if (value == PM_RPU_BOOTMEM_HIVEC) {
val |= ZYNQMP_VINITHI_MASK;
} else {
return PM_RET_ERROR_ARGS;
}
mmio_write_32(rpu_cfg_addr, val);
return PM_RET_SUCCESS;
}
/**
* pm_ioctl_config_tcm_comb() - Configure TCM combined mode
* @value Value to set (Split/Combined)
*
* This function configures TCM to be in split mode or combined
* mode.
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_config_tcm_comb(uint32_t value)
{
uint32_t val;
val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL);
if (value == PM_RPU_TCM_SPLIT) {
val &= ~ZYNQMP_TCM_COMB_MASK;
} else if (value == PM_RPU_TCM_COMB) {
val |= ZYNQMP_TCM_COMB_MASK;
} else {
return PM_RET_ERROR_ARGS;
}
mmio_write_32(ZYNQMP_RPU_GLBL_CNTL, val);
return PM_RET_SUCCESS;
}
/**
* pm_ioctl_set_tapdelay_bypass() - Enable/Disable tap delay bypass
* @type Type of tap delay to enable/disable (e.g. QSPI)
* @value Enable/Disable
*
* This function enable/disable tap delay bypass.
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_set_tapdelay_bypass(uint32_t type,
uint32_t value)
{
if ((value != PM_TAPDELAY_BYPASS_ENABLE &&
value != PM_TAPDELAY_BYPASS_DISABLE) || type >= PM_TAPDELAY_MAX) {
return PM_RET_ERROR_ARGS;
}
return pm_mmio_write(IOU_TAPDLY_BYPASS, TAP_DELAY_MASK, value << type);
}
/**
* pm_ioctl_set_sgmii_mode() - Set SGMII mode for the GEM device
* @nid Node ID of the device
* @value Enable/Disable
*
* This function enable/disable SGMII mode for the GEM device.
* While enabling SGMII mode, it also ties the GEM PCS Signal
* Detect to 1 and selects EMIO for RX clock generation.
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_set_sgmii_mode(enum pm_node_id nid,
uint32_t value)
{
uint32_t val, mask, shift;
enum pm_ret_status ret;
if (value != PM_SGMII_DISABLE && value != PM_SGMII_ENABLE) {
return PM_RET_ERROR_ARGS;
}
switch (nid) {
case NODE_ETH_0:
shift = 0;
break;
case NODE_ETH_1:
shift = 1;
break;
case NODE_ETH_2:
shift = 2;
break;
case NODE_ETH_3:
shift = 3;
break;
default:
return PM_RET_ERROR_ARGS;
}
if (value == PM_SGMII_DISABLE) {
mask = GEM_SGMII_MASK << GEM_CLK_CTRL_OFFSET * shift;
ret = pm_mmio_write(IOU_GEM_CLK_CTRL, mask, 0U);
} else {
/* Tie the GEM PCS Signal Detect to 1 */
mask = SGMII_SD_MASK << SGMII_SD_OFFSET * shift;
val = SGMII_PCS_SD_1 << SGMII_SD_OFFSET * shift;
ret = pm_mmio_write(IOU_GEM_CTRL, mask, val);
if (ret != PM_RET_SUCCESS) {
return ret;
}
/* Set the GEM to SGMII mode */
mask = GEM_CLK_CTRL_MASK << GEM_CLK_CTRL_OFFSET * shift;
val = GEM_RX_SRC_SEL_GTR | GEM_SGMII_MODE;
val <<= GEM_CLK_CTRL_OFFSET * shift;
ret = pm_mmio_write(IOU_GEM_CLK_CTRL, mask, val);
}
return ret;
}
/**
* pm_ioctl_sd_dll_reset() - Reset DLL logic
* @nid Node ID of the device
* @type Reset type
*
* This function resets DLL logic for the SD device.
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_sd_dll_reset(enum pm_node_id nid,
uint32_t type)
{
uint32_t mask, val;
enum pm_ret_status ret;
if (nid == NODE_SD_0) {
mask = ZYNQMP_SD0_DLL_RST_MASK;
val = ZYNQMP_SD0_DLL_RST;
} else if (nid == NODE_SD_1) {
mask = ZYNQMP_SD1_DLL_RST_MASK;
val = ZYNQMP_SD1_DLL_RST;
} else {
return PM_RET_ERROR_ARGS;
}
switch (type) {
case PM_DLL_RESET_ASSERT:
case PM_DLL_RESET_PULSE:
ret = pm_mmio_write(ZYNQMP_SD_DLL_CTRL, mask, val);
if (ret != PM_RET_SUCCESS) {
return ret;
}
if (type == PM_DLL_RESET_ASSERT) {
break;
}
mdelay(1);
/* Fallthrough */
case PM_DLL_RESET_RELEASE:
ret = pm_mmio_write(ZYNQMP_SD_DLL_CTRL, mask, 0);
break;
default:
ret = PM_RET_ERROR_ARGS;
break;
}
return ret;
}
/**
* pm_ioctl_sd_set_tapdelay() - Set tap delay for the SD device
* @nid Node ID of the device
* @type Type of tap delay to set (input/output)
* @value Value to set fot the tap delay
*
* This function sets input/output tap delay for the SD device.
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_sd_set_tapdelay(enum pm_node_id nid,
enum tap_delay_type type,
uint32_t value)
{
uint32_t shift;
enum pm_ret_status ret;
uint32_t val, mask;
if (nid == NODE_SD_0) {
shift = 0;
mask = ZYNQMP_SD0_DLL_RST_MASK;
} else if (nid == NODE_SD_1) {
shift = ZYNQMP_SD_TAP_OFFSET;
mask = ZYNQMP_SD1_DLL_RST_MASK;
} else {
return PM_RET_ERROR_ARGS;
}
ret = pm_mmio_read(ZYNQMP_SD_DLL_CTRL, &val);
if (ret != PM_RET_SUCCESS) {
return ret;
}
if ((val & mask) == 0U) {
ret = pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_ASSERT);
if (ret != PM_RET_SUCCESS) {
return ret;
}
}
if (type == PM_TAPDELAY_INPUT) {
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPCHGWIN_MASK << shift),
(ZYNQMP_SD_ITAPCHGWIN << shift));
if (ret != PM_RET_SUCCESS) {
goto reset_release;
}
if (value == 0U) {
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPDLYENA_MASK <<
shift), 0);
} else {
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPDLYENA_MASK <<
shift), (ZYNQMP_SD_ITAPDLYENA <<
shift));
}
if (ret != PM_RET_SUCCESS) {
goto reset_release;
}
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPDLYSEL_MASK << shift),
(value << shift));
if (ret != PM_RET_SUCCESS) {
goto reset_release;
}
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPCHGWIN_MASK << shift), 0);
} else if (type == PM_TAPDELAY_OUTPUT) {
ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
(ZYNQMP_SD_OTAPDLYENA_MASK << shift), 0);
if (ret != PM_RET_SUCCESS) {
goto reset_release;
}
ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
(ZYNQMP_SD_OTAPDLYSEL_MASK << shift),
(value << shift));
} else {
ret = PM_RET_ERROR_ARGS;
}
reset_release:
if ((val & mask) == 0) {
(void)pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_RELEASE);
}
return ret;
}
/**
* pm_ioctl_set_pll_frac_mode() - Ioctl function for
* setting pll mode
* @pll PLL clock id
* @mode Mode fraction/integar
*
* This function sets PLL mode
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_set_pll_frac_mode
(uint32_t pll, uint32_t mode)
{
return pm_clock_set_pll_mode(pll, mode);
}
/**
* pm_ioctl_get_pll_frac_mode() - Ioctl function for
* getting pll mode
* @pll PLL clock id
* @mode Mode fraction/integar
*
* This function return current PLL mode
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_get_pll_frac_mode
(uint32_t pll, uint32_t *mode)
{
return pm_clock_get_pll_mode(pll, mode);
}
/**
* pm_ioctl_set_pll_frac_data() - Ioctl function for
* setting pll fraction data
* @pll PLL clock id
* @data fraction data
*
* This function sets fraction data.
* It is valid for fraction mode only.
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_set_pll_frac_data
(uint32_t pll, uint32_t data)
{
enum pm_node_id pll_nid;
enum pm_ret_status status;
/* Get PLL node ID using PLL clock ID */
status = pm_clock_get_pll_node_id(pll, &pll_nid);
if (status != PM_RET_SUCCESS) {
return status;
}
return pm_pll_set_parameter(pll_nid, PM_PLL_PARAM_DATA, data);
}
/**
* pm_ioctl_get_pll_frac_data() - Ioctl function for
* getting pll fraction data
* @pll PLL clock id
* @data fraction data
*
* This function returns fraction data value.
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_get_pll_frac_data
(uint32_t pll, uint32_t *data)
{
enum pm_node_id pll_nid;
enum pm_ret_status status;
/* Get PLL node ID using PLL clock ID */
status = pm_clock_get_pll_node_id(pll, &pll_nid);
if (status != PM_RET_SUCCESS) {
return status;
}
return pm_pll_get_parameter(pll_nid, PM_PLL_PARAM_DATA, data);
}
/**
* pm_ioctl_write_ggs() - Ioctl function for writing
* global general storage (ggs)
* @index GGS register index
* @value Register value to be written
*
* This function writes value to GGS register.
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_write_ggs(uint32_t index,
uint32_t value)
{
if (index >= GGS_NUM_REGS) {
return PM_RET_ERROR_ARGS;
}
return pm_mmio_write(GGS_BASEADDR + (index << 2),
0xFFFFFFFFU, value);
}
/**
* pm_ioctl_read_ggs() - Ioctl function for reading
* global general storage (ggs)
* @index GGS register index
* @value Register value
*
* This function returns GGS register value.
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_read_ggs(uint32_t index,
uint32_t *value)
{
if (index >= GGS_NUM_REGS) {
return PM_RET_ERROR_ARGS;
}
return pm_mmio_read(GGS_BASEADDR + (index << 2), value);
}
/**
* pm_ioctl_write_pggs() - Ioctl function for writing persistent
* global general storage (pggs)
* @index PGGS register index
* @value Register value to be written
*
* This function writes value to PGGS register.
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_write_pggs(uint32_t index,
uint32_t value)
{
if (index >= PGGS_NUM_REGS) {
return PM_RET_ERROR_ARGS;
}
return pm_mmio_write(PGGS_BASEADDR + (index << 2),
0xFFFFFFFFU, value);
}
/**
* pm_ioctl_afi() - Ioctl function for writing afi values
*
* @index AFI register index
* @value Register value to be written
*
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_afi(uint32_t index,
uint32_t value)
{
uint32_t mask;
uint32_t regarr[] = {0xFD360000U,
0xFD360014U,
0xFD370000U,
0xFD370014U,
0xFD380000U,
0xFD380014U,
0xFD390000U,
0xFD390014U,
0xFD3a0000U,
0xFD3a0014U,
0xFD3b0000U,
0xFD3b0014U,
0xFF9b0000U,
0xFF9b0014U,
0xFD615000U,
0xFF419000U,
};
if (index >= ARRAY_SIZE(regarr)) {
return PM_RET_ERROR_ARGS;
}
if (index <= AFIFM6_WRCTRL) {
mask = FABRIC_WIDTH;
} else {
mask = 0xf00;
}
return pm_mmio_write(regarr[index], mask, value);
}
/**
* pm_ioctl_read_pggs() - Ioctl function for reading persistent
* global general storage (pggs)
* @index PGGS register index
* @value Register value
*
* This function returns PGGS register value.
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_read_pggs(uint32_t index,
uint32_t *value)
{
if (index >= PGGS_NUM_REGS) {
return PM_RET_ERROR_ARGS;
}
return pm_mmio_read(PGGS_BASEADDR + (index << 2), value);
}
/**
* pm_ioctl_ulpi_reset() - Ioctl function for performing ULPI reset
*
* This function peerforms the ULPI reset sequence for resetting
* the ULPI transceiver.
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_ulpi_reset(void)
{
enum pm_ret_status ret;
ret = pm_mmio_write(CRL_APB_BOOT_PIN_CTRL, CRL_APB_BOOT_PIN_MASK,
ZYNQMP_ULPI_RESET_VAL_HIGH);
if (ret != PM_RET_SUCCESS) {
return ret;
}
/* Drive ULPI assert for atleast 1ms */
mdelay(1);
ret = pm_mmio_write(CRL_APB_BOOT_PIN_CTRL, CRL_APB_BOOT_PIN_MASK,
ZYNQMP_ULPI_RESET_VAL_LOW);
if (ret != PM_RET_SUCCESS) {
return ret;
}
/* Drive ULPI de-assert for atleast 1ms */
mdelay(1);
ret = pm_mmio_write(CRL_APB_BOOT_PIN_CTRL, CRL_APB_BOOT_PIN_MASK,
ZYNQMP_ULPI_RESET_VAL_HIGH);
return ret;
}
/**
* pm_ioctl_set_boot_health_status() - Ioctl for setting healthy boot status
*
* This function sets healthy bit value to indicate boot health status
* to firmware.
*
* @return Returns status, either success or error+reason
*/
static enum pm_ret_status pm_ioctl_set_boot_health_status(uint32_t value)
{
return pm_mmio_write(PMU_GLOBAL_GEN_STORAGE4,
PM_BOOT_HEALTH_STATUS_MASK, value);
}
/**
* pm_api_ioctl() - PM IOCTL API for device control and configs
* @node_id Node ID of the device
* @ioctl_id ID of the requested IOCTL
* @arg1 Argument 1 to requested IOCTL call
* @arg2 Argument 2 to requested IOCTL call
* @value Returned output value
*
* This function calls IOCTL to firmware for device control and configuration.
*
* @return Returns status, either success or error+reason
*/
enum pm_ret_status pm_api_ioctl(enum pm_node_id nid,
uint32_t ioctl_id,
uint32_t arg1,
uint32_t arg2,
uint32_t *value)
{
enum pm_ret_status ret;
uint32_t payload[PAYLOAD_ARG_CNT];
switch (ioctl_id) {
case IOCTL_GET_RPU_OPER_MODE:
ret = pm_ioctl_get_rpu_oper_mode(value);
break;
case IOCTL_SET_RPU_OPER_MODE:
ret = pm_ioctl_set_rpu_oper_mode(arg1);
break;
case IOCTL_RPU_BOOT_ADDR_CONFIG:
ret = pm_ioctl_config_boot_addr(nid, arg1);
break;
case IOCTL_TCM_COMB_CONFIG:
ret = pm_ioctl_config_tcm_comb(arg1);
break;
case IOCTL_SET_TAPDELAY_BYPASS:
ret = pm_ioctl_set_tapdelay_bypass(arg1, arg2);
break;
case IOCTL_SET_SGMII_MODE:
ret = pm_ioctl_set_sgmii_mode(nid, arg1);
break;
case IOCTL_SD_DLL_RESET:
ret = pm_ioctl_sd_dll_reset(nid, arg1);
break;
case IOCTL_SET_SD_TAPDELAY:
ret = pm_ioctl_sd_set_tapdelay(nid, arg1, arg2);
break;
case IOCTL_SET_PLL_FRAC_MODE:
ret = pm_ioctl_set_pll_frac_mode(arg1, arg2);
break;
case IOCTL_GET_PLL_FRAC_MODE:
ret = pm_ioctl_get_pll_frac_mode(arg1, value);
break;
case IOCTL_SET_PLL_FRAC_DATA:
ret = pm_ioctl_set_pll_frac_data(arg1, arg2);
break;
case IOCTL_GET_PLL_FRAC_DATA:
ret = pm_ioctl_get_pll_frac_data(arg1, value);
break;
case IOCTL_WRITE_GGS:
ret = pm_ioctl_write_ggs(arg1, arg2);
break;
case IOCTL_READ_GGS:
ret = pm_ioctl_read_ggs(arg1, value);
break;
case IOCTL_WRITE_PGGS:
ret = pm_ioctl_write_pggs(arg1, arg2);
break;
case IOCTL_READ_PGGS:
ret = pm_ioctl_read_pggs(arg1, value);
break;
case IOCTL_ULPI_RESET:
ret = pm_ioctl_ulpi_reset();
break;
case IOCTL_SET_BOOT_HEALTH_STATUS:
ret = pm_ioctl_set_boot_health_status(arg1);
break;
case IOCTL_AFI:
ret = pm_ioctl_afi(arg1, arg2);
break;
default:
/* Send request to the PMU */
PM_PACK_PAYLOAD5(payload, PM_IOCTL, nid, ioctl_id, arg1, arg2);
ret = pm_ipi_send_sync(primary_proc, payload, value, 1);
break;
}
return ret;
}
/**
* pm_update_ioctl_bitmask() - API to get supported IOCTL ID mask
* @bit_mask Returned bit mask of supported IOCTL IDs
*/
enum pm_ret_status atf_ioctl_bitmask(uint32_t *bit_mask)
{
uint8_t supported_ids[] = {
IOCTL_GET_RPU_OPER_MODE,
IOCTL_SET_RPU_OPER_MODE,
IOCTL_RPU_BOOT_ADDR_CONFIG,
IOCTL_TCM_COMB_CONFIG,
IOCTL_SET_TAPDELAY_BYPASS,
IOCTL_SET_SGMII_MODE,
IOCTL_SD_DLL_RESET,
IOCTL_SET_SD_TAPDELAY,
IOCTL_SET_PLL_FRAC_MODE,
IOCTL_GET_PLL_FRAC_MODE,
IOCTL_SET_PLL_FRAC_DATA,
IOCTL_GET_PLL_FRAC_DATA,
IOCTL_WRITE_GGS,
IOCTL_READ_GGS,
IOCTL_WRITE_PGGS,
IOCTL_READ_PGGS,
IOCTL_ULPI_RESET,
IOCTL_SET_BOOT_HEALTH_STATUS,
IOCTL_AFI,
};
uint8_t i, ioctl_id;
int32_t ret;
for (i = 0U; i < ARRAY_SIZE(supported_ids); i++) {
ioctl_id = supported_ids[i];
if (ioctl_id >= 64U) {
return PM_RET_ERROR_NOTSUPPORTED;
}
ret = check_api_dependency(ioctl_id);
if (ret == PM_RET_SUCCESS) {
bit_mask[ioctl_id / 32U] |= BIT(ioctl_id % 32U);
}
}
return PM_RET_SUCCESS;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
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/*
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* ZynqMP system level PM-API functions for pin control.
*/
#ifndef PM_API_IOCTL_H
#define PM_API_IOCTL_H
#include "pm_common.h"
//ioctl id
enum {
IOCTL_GET_RPU_OPER_MODE = 0,
IOCTL_SET_RPU_OPER_MODE = 1,
IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
IOCTL_TCM_COMB_CONFIG = 3,
IOCTL_SET_TAPDELAY_BYPASS = 4,
IOCTL_SET_SGMII_MODE = 5,
IOCTL_SD_DLL_RESET = 6,
IOCTL_SET_SD_TAPDELAY = 7,
/* Ioctl for clock driver */
IOCTL_SET_PLL_FRAC_MODE = 8,
IOCTL_GET_PLL_FRAC_MODE = 9,
IOCTL_SET_PLL_FRAC_DATA = 10,
IOCTL_GET_PLL_FRAC_DATA = 11,
IOCTL_WRITE_GGS = 12,
IOCTL_READ_GGS = 13,
IOCTL_WRITE_PGGS = 14,
IOCTL_READ_PGGS = 15,
/* IOCTL for ULPI reset */
IOCTL_ULPI_RESET = 16,
/* Set healthy bit value */
IOCTL_SET_BOOT_HEALTH_STATUS = 17,
IOCTL_AFI = 18,
/* Probe counter read/write */
IOCTL_PROBE_COUNTER_READ = 19,
IOCTL_PROBE_COUNTER_WRITE = 20,
IOCTL_OSPI_MUX_SELECT = 21,
/* IOCTL for USB power request */
IOCTL_USB_SET_STATE = 22,
/* IOCTL to get last reset reason */
IOCTL_GET_LAST_RESET_REASON = 23,
/* AI engine NPI ISR clear */
IOCTL_AIE_ISR_CLEAR = 24,
/* Register SGI to ATF */
IOCTL_REGISTER_SGI = 25,
};
//RPU operation mode
#define PM_RPU_MODE_LOCKSTEP 0U
#define PM_RPU_MODE_SPLIT 1U
//RPU boot mem
#define PM_RPU_BOOTMEM_LOVEC 0U
#define PM_RPU_BOOTMEM_HIVEC 1U
//RPU tcm mpde
#define PM_RPU_TCM_SPLIT 0U
#define PM_RPU_TCM_COMB 1U
//tap delay signal type
#define PM_TAPDELAY_NAND_DQS_IN 0U
#define PM_TAPDELAY_NAND_DQS_OUT 1U
#define PM_TAPDELAY_QSPI 2U
#define PM_TAPDELAY_MAX 3U
//tap delay bypass
#define PM_TAPDELAY_BYPASS_DISABLE 0U
#define PM_TAPDELAY_BYPASS_ENABLE 1U
//sgmii mode
#define PM_SGMII_DISABLE 0U
#define PM_SGMII_ENABLE 1U
enum tap_delay_type {
PM_TAPDELAY_INPUT,
PM_TAPDELAY_OUTPUT,
};
//dll reset type
#define PM_DLL_RESET_ASSERT 0U
#define PM_DLL_RESET_RELEASE 1U
#define PM_DLL_RESET_PULSE 2U
enum pm_ret_status pm_api_ioctl(enum pm_node_id nid,
uint32_t ioctl_id,
uint32_t arg1,
uint32_t arg2,
uint32_t *value);
enum pm_ret_status atf_ioctl_bitmask(uint32_t *bit_mask);
#endif /* PM_API_IOCTL_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
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source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
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/*
* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* ZynqMP system level PM-API functions for pin control.
*/
#ifndef PM_API_PINCTRL_H
#define PM_API_PINCTRL_H
#include "pm_common.h"
#define FUNCTION_NAME_LEN (16U)
#define GROUPS_PAYLOAD_LEN (12U)
#define NUM_GROUPS_PER_RESP (6U)
#define END_OF_FUNCTION "END_OF_FUNCTION"
#define END_OF_GROUPS -1
#define PINCTRL_GRP_RESERVED -2
//pinctrl function ids
enum {
PINCTRL_FUNC_CAN0 = (0U),
PINCTRL_FUNC_CAN1 = (1U),
PINCTRL_FUNC_ETHERNET0 = (2U),
PINCTRL_FUNC_ETHERNET1 = (3U),
PINCTRL_FUNC_ETHERNET2 = (4U),
PINCTRL_FUNC_ETHERNET3 = (5U),
PINCTRL_FUNC_GEMTSU0 = (6U),
PINCTRL_FUNC_GPIO0 = (7U),
PINCTRL_FUNC_I2C0 = (8U),
PINCTRL_FUNC_I2C1 = (9U),
PINCTRL_FUNC_MDIO0 = (10U),
PINCTRL_FUNC_MDIO1 = (11U),
PINCTRL_FUNC_MDIO2 = (12U),
PINCTRL_FUNC_MDIO3 = (13U),
PINCTRL_FUNC_QSPI0 = (14U),
PINCTRL_FUNC_QSPI_FBCLK = (15U),
PINCTRL_FUNC_QSPI_SS = (16U),
PINCTRL_FUNC_SPI0 = (17U),
PINCTRL_FUNC_SPI1 = (18U),
PINCTRL_FUNC_SPI0_SS = (19U),
PINCTRL_FUNC_SPI1_SS = (20U),
PINCTRL_FUNC_SDIO0 = (21U),
PINCTRL_FUNC_SDIO0_PC = (22U),
PINCTRL_FUNC_SDIO0_CD = (23U),
PINCTRL_FUNC_SDIO0_WP = (24U),
PINCTRL_FUNC_SDIO1 = (25U),
PINCTRL_FUNC_SDIO1_PC = (26U),
PINCTRL_FUNC_SDIO1_CD = (27U),
PINCTRL_FUNC_SDIO1_WP = (28U),
PINCTRL_FUNC_NAND0 = (29U),
PINCTRL_FUNC_NAND0_CE = (30U),
PINCTRL_FUNC_NAND0_RB = (31U),
PINCTRL_FUNC_NAND0_DQS = (32U),
PINCTRL_FUNC_TTC0_CLK = (33U),
PINCTRL_FUNC_TTC0_WAV = (34U),
PINCTRL_FUNC_TTC1_CLK = (35U),
PINCTRL_FUNC_TTC1_WAV = (36U),
PINCTRL_FUNC_TTC2_CLK = (37U),
PINCTRL_FUNC_TTC2_WAV = (38U),
PINCTRL_FUNC_TTC3_CLK = (39U),
PINCTRL_FUNC_TTC3_WAV = (40U),
PINCTRL_FUNC_UART0 = (41U),
PINCTRL_FUNC_UART1 = (42U),
PINCTRL_FUNC_USB0 = (43U),
PINCTRL_FUNC_USB1 = (44U),
PINCTRL_FUNC_SWDT0_CLK = (45U),
PINCTRL_FUNC_SWDT0_RST = (46U),
PINCTRL_FUNC_SWDT1_CLK = (47U),
PINCTRL_FUNC_SWDT1_RST = (48U),
PINCTRL_FUNC_PMU0 = (49U),
PINCTRL_FUNC_PCIE0 = (50U),
PINCTRL_FUNC_CSU0 = (51U),
PINCTRL_FUNC_DPAUX0 = (52U),
PINCTRL_FUNC_PJTAG0 = (53U),
PINCTRL_FUNC_TRACE0 = (54U),
PINCTRL_FUNC_TRACE0_CLK = (55U),
PINCTRL_FUNC_TESTSCAN0 = (56U),
END_FUNCTION = (57U),
};
#define MAX_FUNCTION END_FUNCTION
// pinctrl pin numbers
enum {
PINCTRL_PIN_0,
PINCTRL_PIN_1,
PINCTRL_PIN_2,
PINCTRL_PIN_3,
PINCTRL_PIN_4,
PINCTRL_PIN_5,
PINCTRL_PIN_6,
PINCTRL_PIN_7,
PINCTRL_PIN_8,
PINCTRL_PIN_9,
PINCTRL_PIN_10,
PINCTRL_PIN_11,
PINCTRL_PIN_12,
PINCTRL_PIN_13,
PINCTRL_PIN_14,
PINCTRL_PIN_15,
PINCTRL_PIN_16,
PINCTRL_PIN_17,
PINCTRL_PIN_18,
PINCTRL_PIN_19,
PINCTRL_PIN_20,
PINCTRL_PIN_21,
PINCTRL_PIN_22,
PINCTRL_PIN_23,
PINCTRL_PIN_24,
PINCTRL_PIN_25,
PINCTRL_PIN_26,
PINCTRL_PIN_27,
PINCTRL_PIN_28,
PINCTRL_PIN_29,
PINCTRL_PIN_30,
PINCTRL_PIN_31,
PINCTRL_PIN_32,
PINCTRL_PIN_33,
PINCTRL_PIN_34,
PINCTRL_PIN_35,
PINCTRL_PIN_36,
PINCTRL_PIN_37,
PINCTRL_PIN_38,
PINCTRL_PIN_39,
PINCTRL_PIN_40,
PINCTRL_PIN_41,
PINCTRL_PIN_42,
PINCTRL_PIN_43,
PINCTRL_PIN_44,
PINCTRL_PIN_45,
PINCTRL_PIN_46,
PINCTRL_PIN_47,
PINCTRL_PIN_48,
PINCTRL_PIN_49,
PINCTRL_PIN_50,
PINCTRL_PIN_51,
PINCTRL_PIN_52,
PINCTRL_PIN_53,
PINCTRL_PIN_54,
PINCTRL_PIN_55,
PINCTRL_PIN_56,
PINCTRL_PIN_57,
PINCTRL_PIN_58,
PINCTRL_PIN_59,
PINCTRL_PIN_60,
PINCTRL_PIN_61,
PINCTRL_PIN_62,
PINCTRL_PIN_63,
PINCTRL_PIN_64,
PINCTRL_PIN_65,
PINCTRL_PIN_66,
PINCTRL_PIN_67,
PINCTRL_PIN_68,
PINCTRL_PIN_69,
PINCTRL_PIN_70,
PINCTRL_PIN_71,
PINCTRL_PIN_72,
PINCTRL_PIN_73,
PINCTRL_PIN_74,
PINCTRL_PIN_75,
PINCTRL_PIN_76,
PINCTRL_PIN_77,
END_PINS = (78U),
};
#define MAX_PIN END_PINS
// pinctrl group ids
enum {
PINCTRL_GRP_ETHERNET0_0,
PINCTRL_GRP_ETHERNET1_0,
PINCTRL_GRP_ETHERNET2_0,
PINCTRL_GRP_ETHERNET3_0,
PINCTRL_GRP_GEMTSU0_0,
PINCTRL_GRP_GEMTSU0_1,
PINCTRL_GRP_GEMTSU0_2,
PINCTRL_GRP_MDIO0_0,
PINCTRL_GRP_MDIO1_0,
PINCTRL_GRP_MDIO1_1,
PINCTRL_GRP_MDIO2_0,
PINCTRL_GRP_MDIO3_0,
PINCTRL_GRP_QSPI0_0,
PINCTRL_GRP_QSPI_SS,
PINCTRL_GRP_QSPI_FBCLK,
PINCTRL_GRP_SPI0_0,
PINCTRL_GRP_SPI0_1,
PINCTRL_GRP_SPI0_2,
PINCTRL_GRP_SPI0_3,
PINCTRL_GRP_SPI0_4,
PINCTRL_GRP_SPI0_5,
PINCTRL_GRP_SPI0_0_SS0,
PINCTRL_GRP_SPI0_0_SS1,
PINCTRL_GRP_SPI0_0_SS2,
PINCTRL_GRP_SPI0_1_SS0,
PINCTRL_GRP_SPI0_1_SS1,
PINCTRL_GRP_SPI0_1_SS2,
PINCTRL_GRP_SPI0_2_SS0,
PINCTRL_GRP_SPI0_2_SS1,
PINCTRL_GRP_SPI0_2_SS2,
PINCTRL_GRP_SPI0_3_SS0,
PINCTRL_GRP_SPI0_3_SS1,
PINCTRL_GRP_SPI0_3_SS2,
PINCTRL_GRP_SPI0_4_SS0,
PINCTRL_GRP_SPI0_4_SS1,
PINCTRL_GRP_SPI0_4_SS2,
PINCTRL_GRP_SPI0_5_SS0,
PINCTRL_GRP_SPI0_5_SS1,
PINCTRL_GRP_SPI0_5_SS2,
PINCTRL_GRP_SPI1_0,
PINCTRL_GRP_SPI1_1,
PINCTRL_GRP_SPI1_2,
PINCTRL_GRP_SPI1_3,
PINCTRL_GRP_SPI1_4,
PINCTRL_GRP_SPI1_5,
PINCTRL_GRP_SPI1_0_SS0,
PINCTRL_GRP_SPI1_0_SS1,
PINCTRL_GRP_SPI1_0_SS2,
PINCTRL_GRP_SPI1_1_SS0,
PINCTRL_GRP_SPI1_1_SS1,
PINCTRL_GRP_SPI1_1_SS2,
PINCTRL_GRP_SPI1_2_SS0,
PINCTRL_GRP_SPI1_2_SS1,
PINCTRL_GRP_SPI1_2_SS2,
PINCTRL_GRP_SPI1_3_SS0,
PINCTRL_GRP_SPI1_3_SS1,
PINCTRL_GRP_SPI1_3_SS2,
PINCTRL_GRP_SPI1_4_SS0,
PINCTRL_GRP_SPI1_4_SS1,
PINCTRL_GRP_SPI1_4_SS2,
PINCTRL_GRP_SPI1_5_SS0,
PINCTRL_GRP_SPI1_5_SS1,
PINCTRL_GRP_SPI1_5_SS2,
PINCTRL_GRP_SDIO0_0,
PINCTRL_GRP_SDIO0_1,
PINCTRL_GRP_SDIO0_2,
PINCTRL_GRP_SDIO0_4BIT_0_0,
PINCTRL_GRP_SDIO0_4BIT_0_1,
PINCTRL_GRP_SDIO0_4BIT_1_0,
PINCTRL_GRP_SDIO0_4BIT_1_1,
PINCTRL_GRP_SDIO0_4BIT_2_0,
PINCTRL_GRP_SDIO0_4BIT_2_1,
PINCTRL_GRP_SDIO0_1BIT_0_0,
PINCTRL_GRP_SDIO0_1BIT_0_1,
PINCTRL_GRP_SDIO0_1BIT_0_2,
PINCTRL_GRP_SDIO0_1BIT_0_3,
PINCTRL_GRP_SDIO0_1BIT_0_4,
PINCTRL_GRP_SDIO0_1BIT_0_5,
PINCTRL_GRP_SDIO0_1BIT_0_6,
PINCTRL_GRP_SDIO0_1BIT_0_7,
PINCTRL_GRP_SDIO0_1BIT_1_0,
PINCTRL_GRP_SDIO0_1BIT_1_1,
PINCTRL_GRP_SDIO0_1BIT_1_2,
PINCTRL_GRP_SDIO0_1BIT_1_3,
PINCTRL_GRP_SDIO0_1BIT_1_4,
PINCTRL_GRP_SDIO0_1BIT_1_5,
PINCTRL_GRP_SDIO0_1BIT_1_6,
PINCTRL_GRP_SDIO0_1BIT_1_7,
PINCTRL_GRP_SDIO0_1BIT_2_0,
PINCTRL_GRP_SDIO0_1BIT_2_1,
PINCTRL_GRP_SDIO0_1BIT_2_2,
PINCTRL_GRP_SDIO0_1BIT_2_3,
PINCTRL_GRP_SDIO0_1BIT_2_4,
PINCTRL_GRP_SDIO0_1BIT_2_5,
PINCTRL_GRP_SDIO0_1BIT_2_6,
PINCTRL_GRP_SDIO0_1BIT_2_7,
PINCTRL_GRP_SDIO0_0_PC,
PINCTRL_GRP_SDIO0_1_PC,
PINCTRL_GRP_SDIO0_2_PC,
PINCTRL_GRP_SDIO0_0_CD,
PINCTRL_GRP_SDIO0_1_CD,
PINCTRL_GRP_SDIO0_2_CD,
PINCTRL_GRP_SDIO0_0_WP,
PINCTRL_GRP_SDIO0_1_WP,
PINCTRL_GRP_SDIO0_2_WP,
PINCTRL_GRP_SDIO1_0,
PINCTRL_GRP_SDIO1_4BIT_0_0,
PINCTRL_GRP_SDIO1_4BIT_0_1,
PINCTRL_GRP_SDIO1_4BIT_1_0,
PINCTRL_GRP_SDIO1_1BIT_0_0,
PINCTRL_GRP_SDIO1_1BIT_0_1,
PINCTRL_GRP_SDIO1_1BIT_0_2,
PINCTRL_GRP_SDIO1_1BIT_0_3,
PINCTRL_GRP_SDIO1_1BIT_0_4,
PINCTRL_GRP_SDIO1_1BIT_0_5,
PINCTRL_GRP_SDIO1_1BIT_0_6,
PINCTRL_GRP_SDIO1_1BIT_0_7,
PINCTRL_GRP_SDIO1_1BIT_1_0,
PINCTRL_GRP_SDIO1_1BIT_1_1,
PINCTRL_GRP_SDIO1_1BIT_1_2,
PINCTRL_GRP_SDIO1_1BIT_1_3,
PINCTRL_GRP_SDIO1_0_PC,
PINCTRL_GRP_SDIO1_1_PC,
PINCTRL_GRP_SDIO1_0_CD,
PINCTRL_GRP_SDIO1_1_CD,
PINCTRL_GRP_SDIO1_0_WP,
PINCTRL_GRP_SDIO1_1_WP,
PINCTRL_GRP_NAND0_0,
PINCTRL_GRP_NAND0_0_CE,
PINCTRL_GRP_NAND0_1_CE,
PINCTRL_GRP_NAND0_0_RB,
PINCTRL_GRP_NAND0_1_RB,
PINCTRL_GRP_NAND0_0_DQS,
PINCTRL_GRP_NAND0_1_DQS,
PINCTRL_GRP_CAN0_0,
PINCTRL_GRP_CAN0_1,
PINCTRL_GRP_CAN0_2,
PINCTRL_GRP_CAN0_3,
PINCTRL_GRP_CAN0_4,
PINCTRL_GRP_CAN0_5,
PINCTRL_GRP_CAN0_6,
PINCTRL_GRP_CAN0_7,
PINCTRL_GRP_CAN0_8,
PINCTRL_GRP_CAN0_9,
PINCTRL_GRP_CAN0_10,
PINCTRL_GRP_CAN0_11,
PINCTRL_GRP_CAN0_12,
PINCTRL_GRP_CAN0_13,
PINCTRL_GRP_CAN0_14,
PINCTRL_GRP_CAN0_15,
PINCTRL_GRP_CAN0_16,
PINCTRL_GRP_CAN0_17,
PINCTRL_GRP_CAN0_18,
PINCTRL_GRP_CAN1_0,
PINCTRL_GRP_CAN1_1,
PINCTRL_GRP_CAN1_2,
PINCTRL_GRP_CAN1_3,
PINCTRL_GRP_CAN1_4,
PINCTRL_GRP_CAN1_5,
PINCTRL_GRP_CAN1_6,
PINCTRL_GRP_CAN1_7,
PINCTRL_GRP_CAN1_8,
PINCTRL_GRP_CAN1_9,
PINCTRL_GRP_CAN1_10,
PINCTRL_GRP_CAN1_11,
PINCTRL_GRP_CAN1_12,
PINCTRL_GRP_CAN1_13,
PINCTRL_GRP_CAN1_14,
PINCTRL_GRP_CAN1_15,
PINCTRL_GRP_CAN1_16,
PINCTRL_GRP_CAN1_17,
PINCTRL_GRP_CAN1_18,
PINCTRL_GRP_CAN1_19,
PINCTRL_GRP_UART0_0,
PINCTRL_GRP_UART0_1,
PINCTRL_GRP_UART0_2,
PINCTRL_GRP_UART0_3,
PINCTRL_GRP_UART0_4,
PINCTRL_GRP_UART0_5,
PINCTRL_GRP_UART0_6,
PINCTRL_GRP_UART0_7,
PINCTRL_GRP_UART0_8,
PINCTRL_GRP_UART0_9,
PINCTRL_GRP_UART0_10,
PINCTRL_GRP_UART0_11,
PINCTRL_GRP_UART0_12,
PINCTRL_GRP_UART0_13,
PINCTRL_GRP_UART0_14,
PINCTRL_GRP_UART0_15,
PINCTRL_GRP_UART0_16,
PINCTRL_GRP_UART0_17,
PINCTRL_GRP_UART0_18,
PINCTRL_GRP_UART1_0,
PINCTRL_GRP_UART1_1,
PINCTRL_GRP_UART1_2,
PINCTRL_GRP_UART1_3,
PINCTRL_GRP_UART1_4,
PINCTRL_GRP_UART1_5,
PINCTRL_GRP_UART1_6,
PINCTRL_GRP_UART1_7,
PINCTRL_GRP_UART1_8,
PINCTRL_GRP_UART1_9,
PINCTRL_GRP_UART1_10,
PINCTRL_GRP_UART1_11,
PINCTRL_GRP_UART1_12,
PINCTRL_GRP_UART1_13,
PINCTRL_GRP_UART1_14,
PINCTRL_GRP_UART1_15,
PINCTRL_GRP_UART1_16,
PINCTRL_GRP_UART1_17,
PINCTRL_GRP_UART1_18,
PINCTRL_GRP_I2C0_0,
PINCTRL_GRP_I2C0_1,
PINCTRL_GRP_I2C0_2,
PINCTRL_GRP_I2C0_3,
PINCTRL_GRP_I2C0_4,
PINCTRL_GRP_I2C0_5,
PINCTRL_GRP_I2C0_6,
PINCTRL_GRP_I2C0_7,
PINCTRL_GRP_I2C0_8,
PINCTRL_GRP_I2C0_9,
PINCTRL_GRP_I2C0_10,
PINCTRL_GRP_I2C0_11,
PINCTRL_GRP_I2C0_12,
PINCTRL_GRP_I2C0_13,
PINCTRL_GRP_I2C0_14,
PINCTRL_GRP_I2C0_15,
PINCTRL_GRP_I2C0_16,
PINCTRL_GRP_I2C0_17,
PINCTRL_GRP_I2C0_18,
PINCTRL_GRP_I2C1_0,
PINCTRL_GRP_I2C1_1,
PINCTRL_GRP_I2C1_2,
PINCTRL_GRP_I2C1_3,
PINCTRL_GRP_I2C1_4,
PINCTRL_GRP_I2C1_5,
PINCTRL_GRP_I2C1_6,
PINCTRL_GRP_I2C1_7,
PINCTRL_GRP_I2C1_8,
PINCTRL_GRP_I2C1_9,
PINCTRL_GRP_I2C1_10,
PINCTRL_GRP_I2C1_11,
PINCTRL_GRP_I2C1_12,
PINCTRL_GRP_I2C1_13,
PINCTRL_GRP_I2C1_14,
PINCTRL_GRP_I2C1_15,
PINCTRL_GRP_I2C1_16,
PINCTRL_GRP_I2C1_17,
PINCTRL_GRP_I2C1_18,
PINCTRL_GRP_I2C1_19,
PINCTRL_GRP_TTC0_0_CLK,
PINCTRL_GRP_TTC0_1_CLK,
PINCTRL_GRP_TTC0_2_CLK,
PINCTRL_GRP_TTC0_3_CLK,
PINCTRL_GRP_TTC0_4_CLK,
PINCTRL_GRP_TTC0_5_CLK,
PINCTRL_GRP_TTC0_6_CLK,
PINCTRL_GRP_TTC0_7_CLK,
PINCTRL_GRP_TTC0_8_CLK,
PINCTRL_GRP_TTC0_0_WAV,
PINCTRL_GRP_TTC0_1_WAV,
PINCTRL_GRP_TTC0_2_WAV,
PINCTRL_GRP_TTC0_3_WAV,
PINCTRL_GRP_TTC0_4_WAV,
PINCTRL_GRP_TTC0_5_WAV,
PINCTRL_GRP_TTC0_6_WAV,
PINCTRL_GRP_TTC0_7_WAV,
PINCTRL_GRP_TTC0_8_WAV,
PINCTRL_GRP_TTC1_0_CLK,
PINCTRL_GRP_TTC1_1_CLK,
PINCTRL_GRP_TTC1_2_CLK,
PINCTRL_GRP_TTC1_3_CLK,
PINCTRL_GRP_TTC1_4_CLK,
PINCTRL_GRP_TTC1_5_CLK,
PINCTRL_GRP_TTC1_6_CLK,
PINCTRL_GRP_TTC1_7_CLK,
PINCTRL_GRP_TTC1_8_CLK,
PINCTRL_GRP_TTC1_0_WAV,
PINCTRL_GRP_TTC1_1_WAV,
PINCTRL_GRP_TTC1_2_WAV,
PINCTRL_GRP_TTC1_3_WAV,
PINCTRL_GRP_TTC1_4_WAV,
PINCTRL_GRP_TTC1_5_WAV,
PINCTRL_GRP_TTC1_6_WAV,
PINCTRL_GRP_TTC1_7_WAV,
PINCTRL_GRP_TTC1_8_WAV,
PINCTRL_GRP_TTC2_0_CLK,
PINCTRL_GRP_TTC2_1_CLK,
PINCTRL_GRP_TTC2_2_CLK,
PINCTRL_GRP_TTC2_3_CLK,
PINCTRL_GRP_TTC2_4_CLK,
PINCTRL_GRP_TTC2_5_CLK,
PINCTRL_GRP_TTC2_6_CLK,
PINCTRL_GRP_TTC2_7_CLK,
PINCTRL_GRP_TTC2_8_CLK,
PINCTRL_GRP_TTC2_0_WAV,
PINCTRL_GRP_TTC2_1_WAV,
PINCTRL_GRP_TTC2_2_WAV,
PINCTRL_GRP_TTC2_3_WAV,
PINCTRL_GRP_TTC2_4_WAV,
PINCTRL_GRP_TTC2_5_WAV,
PINCTRL_GRP_TTC2_6_WAV,
PINCTRL_GRP_TTC2_7_WAV,
PINCTRL_GRP_TTC2_8_WAV,
PINCTRL_GRP_TTC3_0_CLK,
PINCTRL_GRP_TTC3_1_CLK,
PINCTRL_GRP_TTC3_2_CLK,
PINCTRL_GRP_TTC3_3_CLK,
PINCTRL_GRP_TTC3_4_CLK,
PINCTRL_GRP_TTC3_5_CLK,
PINCTRL_GRP_TTC3_6_CLK,
PINCTRL_GRP_TTC3_7_CLK,
PINCTRL_GRP_TTC3_8_CLK,
PINCTRL_GRP_TTC3_0_WAV,
PINCTRL_GRP_TTC3_1_WAV,
PINCTRL_GRP_TTC3_2_WAV,
PINCTRL_GRP_TTC3_3_WAV,
PINCTRL_GRP_TTC3_4_WAV,
PINCTRL_GRP_TTC3_5_WAV,
PINCTRL_GRP_TTC3_6_WAV,
PINCTRL_GRP_TTC3_7_WAV,
PINCTRL_GRP_TTC3_8_WAV,
PINCTRL_GRP_SWDT0_0_CLK,
PINCTRL_GRP_SWDT0_1_CLK,
PINCTRL_GRP_SWDT0_2_CLK,
PINCTRL_GRP_SWDT0_3_CLK,
PINCTRL_GRP_SWDT0_4_CLK,
PINCTRL_GRP_SWDT0_5_CLK,
PINCTRL_GRP_SWDT0_6_CLK,
PINCTRL_GRP_SWDT0_7_CLK,
PINCTRL_GRP_SWDT0_8_CLK,
PINCTRL_GRP_SWDT0_9_CLK,
PINCTRL_GRP_SWDT0_10_CLK,
PINCTRL_GRP_SWDT0_11_CLK,
PINCTRL_GRP_SWDT0_12_CLK,
PINCTRL_GRP_SWDT0_0_RST,
PINCTRL_GRP_SWDT0_1_RST,
PINCTRL_GRP_SWDT0_2_RST,
PINCTRL_GRP_SWDT0_3_RST,
PINCTRL_GRP_SWDT0_4_RST,
PINCTRL_GRP_SWDT0_5_RST,
PINCTRL_GRP_SWDT0_6_RST,
PINCTRL_GRP_SWDT0_7_RST,
PINCTRL_GRP_SWDT0_8_RST,
PINCTRL_GRP_SWDT0_9_RST,
PINCTRL_GRP_SWDT0_10_RST,
PINCTRL_GRP_SWDT0_11_RST,
PINCTRL_GRP_SWDT0_12_RST,
PINCTRL_GRP_SWDT1_0_CLK,
PINCTRL_GRP_SWDT1_1_CLK,
PINCTRL_GRP_SWDT1_2_CLK,
PINCTRL_GRP_SWDT1_3_CLK,
PINCTRL_GRP_SWDT1_4_CLK,
PINCTRL_GRP_SWDT1_5_CLK,
PINCTRL_GRP_SWDT1_6_CLK,
PINCTRL_GRP_SWDT1_7_CLK,
PINCTRL_GRP_SWDT1_8_CLK,
PINCTRL_GRP_SWDT1_9_CLK,
PINCTRL_GRP_SWDT1_10_CLK,
PINCTRL_GRP_SWDT1_11_CLK,
PINCTRL_GRP_SWDT1_12_CLK,
PINCTRL_GRP_SWDT1_0_RST,
PINCTRL_GRP_SWDT1_1_RST,
PINCTRL_GRP_SWDT1_2_RST,
PINCTRL_GRP_SWDT1_3_RST,
PINCTRL_GRP_SWDT1_4_RST,
PINCTRL_GRP_SWDT1_5_RST,
PINCTRL_GRP_SWDT1_6_RST,
PINCTRL_GRP_SWDT1_7_RST,
PINCTRL_GRP_SWDT1_8_RST,
PINCTRL_GRP_SWDT1_9_RST,
PINCTRL_GRP_SWDT1_10_RST,
PINCTRL_GRP_SWDT1_11_RST,
PINCTRL_GRP_SWDT1_12_RST,
PINCTRL_GRP_GPIO0_0,
PINCTRL_GRP_GPIO0_1,
PINCTRL_GRP_GPIO0_2,
PINCTRL_GRP_GPIO0_3,
PINCTRL_GRP_GPIO0_4,
PINCTRL_GRP_GPIO0_5,
PINCTRL_GRP_GPIO0_6,
PINCTRL_GRP_GPIO0_7,
PINCTRL_GRP_GPIO0_8,
PINCTRL_GRP_GPIO0_9,
PINCTRL_GRP_GPIO0_10,
PINCTRL_GRP_GPIO0_11,
PINCTRL_GRP_GPIO0_12,
PINCTRL_GRP_GPIO0_13,
PINCTRL_GRP_GPIO0_14,
PINCTRL_GRP_GPIO0_15,
PINCTRL_GRP_GPIO0_16,
PINCTRL_GRP_GPIO0_17,
PINCTRL_GRP_GPIO0_18,
PINCTRL_GRP_GPIO0_19,
PINCTRL_GRP_GPIO0_20,
PINCTRL_GRP_GPIO0_21,
PINCTRL_GRP_GPIO0_22,
PINCTRL_GRP_GPIO0_23,
PINCTRL_GRP_GPIO0_24,
PINCTRL_GRP_GPIO0_25,
PINCTRL_GRP_GPIO0_26,
PINCTRL_GRP_GPIO0_27,
PINCTRL_GRP_GPIO0_28,
PINCTRL_GRP_GPIO0_29,
PINCTRL_GRP_GPIO0_30,
PINCTRL_GRP_GPIO0_31,
PINCTRL_GRP_GPIO0_32,
PINCTRL_GRP_GPIO0_33,
PINCTRL_GRP_GPIO0_34,
PINCTRL_GRP_GPIO0_35,
PINCTRL_GRP_GPIO0_36,
PINCTRL_GRP_GPIO0_37,
PINCTRL_GRP_GPIO0_38,
PINCTRL_GRP_GPIO0_39,
PINCTRL_GRP_GPIO0_40,
PINCTRL_GRP_GPIO0_41,
PINCTRL_GRP_GPIO0_42,
PINCTRL_GRP_GPIO0_43,
PINCTRL_GRP_GPIO0_44,
PINCTRL_GRP_GPIO0_45,
PINCTRL_GRP_GPIO0_46,
PINCTRL_GRP_GPIO0_47,
PINCTRL_GRP_GPIO0_48,
PINCTRL_GRP_GPIO0_49,
PINCTRL_GRP_GPIO0_50,
PINCTRL_GRP_GPIO0_51,
PINCTRL_GRP_GPIO0_52,
PINCTRL_GRP_GPIO0_53,
PINCTRL_GRP_GPIO0_54,
PINCTRL_GRP_GPIO0_55,
PINCTRL_GRP_GPIO0_56,
PINCTRL_GRP_GPIO0_57,
PINCTRL_GRP_GPIO0_58,
PINCTRL_GRP_GPIO0_59,
PINCTRL_GRP_GPIO0_60,
PINCTRL_GRP_GPIO0_61,
PINCTRL_GRP_GPIO0_62,
PINCTRL_GRP_GPIO0_63,
PINCTRL_GRP_GPIO0_64,
PINCTRL_GRP_GPIO0_65,
PINCTRL_GRP_GPIO0_66,
PINCTRL_GRP_GPIO0_67,
PINCTRL_GRP_GPIO0_68,
PINCTRL_GRP_GPIO0_69,
PINCTRL_GRP_GPIO0_70,
PINCTRL_GRP_GPIO0_71,
PINCTRL_GRP_GPIO0_72,
PINCTRL_GRP_GPIO0_73,
PINCTRL_GRP_GPIO0_74,
PINCTRL_GRP_GPIO0_75,
PINCTRL_GRP_GPIO0_76,
PINCTRL_GRP_GPIO0_77,
PINCTRL_GRP_USB0_0,
PINCTRL_GRP_USB1_0,
PINCTRL_GRP_PMU0_0,
PINCTRL_GRP_PMU0_1,
PINCTRL_GRP_PMU0_2,
PINCTRL_GRP_PMU0_3,
PINCTRL_GRP_PMU0_4,
PINCTRL_GRP_PMU0_5,
PINCTRL_GRP_PMU0_6,
PINCTRL_GRP_PMU0_7,
PINCTRL_GRP_PMU0_8,
PINCTRL_GRP_PMU0_9,
PINCTRL_GRP_PMU0_10,
PINCTRL_GRP_PMU0_11,
PINCTRL_GRP_PCIE0_0,
PINCTRL_GRP_PCIE0_1,
PINCTRL_GRP_PCIE0_2,
PINCTRL_GRP_PCIE0_3,
PINCTRL_GRP_PCIE0_4,
PINCTRL_GRP_PCIE0_5,
PINCTRL_GRP_PCIE0_6,
PINCTRL_GRP_PCIE0_7,
PINCTRL_GRP_CSU0_0,
PINCTRL_GRP_CSU0_1,
PINCTRL_GRP_CSU0_2,
PINCTRL_GRP_CSU0_3,
PINCTRL_GRP_CSU0_4,
PINCTRL_GRP_CSU0_5,
PINCTRL_GRP_CSU0_6,
PINCTRL_GRP_CSU0_7,
PINCTRL_GRP_CSU0_8,
PINCTRL_GRP_CSU0_9,
PINCTRL_GRP_CSU0_10,
PINCTRL_GRP_CSU0_11,
PINCTRL_GRP_DPAUX0_0,
PINCTRL_GRP_DPAUX0_1,
PINCTRL_GRP_DPAUX0_2,
PINCTRL_GRP_DPAUX0_3,
PINCTRL_GRP_PJTAG0_0,
PINCTRL_GRP_PJTAG0_1,
PINCTRL_GRP_PJTAG0_2,
PINCTRL_GRP_PJTAG0_3,
PINCTRL_GRP_PJTAG0_4,
PINCTRL_GRP_PJTAG0_5,
PINCTRL_GRP_TRACE0_0,
PINCTRL_GRP_TRACE0_1,
PINCTRL_GRP_TRACE0_2,
PINCTRL_GRP_TRACE0_0_CLK,
PINCTRL_GRP_TRACE0_1_CLK,
PINCTRL_GRP_TRACE0_2_CLK,
PINCTRL_GRP_TESTSCAN0_0,
};
// pinctrl config parameters
enum {
PINCTRL_CONFIG_SLEW_RATE,
PINCTRL_CONFIG_BIAS_STATUS,
PINCTRL_CONFIG_PULL_CTRL,
PINCTRL_CONFIG_SCHMITT_CMOS,
PINCTRL_CONFIG_DRIVE_STRENGTH,
PINCTRL_CONFIG_VOLTAGE_STATUS,
PINCTRL_CONFIG_MAX,
};
// pinctrl slew rate
#define PINCTRL_SLEW_RATE_FAST 0U
#define PINCTRL_SLEW_RATE_SLOW 1U
// pinctrl bias status
#define PINCTRL_BIAS_DISABLE 0U
#define PINCTRL_BIAS_ENABLE 1U
// pinctrl pull control
#define PINCTRL_BIAS_PULL_DOWN 0U
#define PINCTRL_BIAS_PULL_UP 1U
// pinctrl schmitt cmos type
#define PINCTRL_INPUT_TYPE_CMOS 0U
#define PINCTRL_INPUT_TYPE_SCHMITT 1U
//pinctrl drive strength values
#define PINCTRL_DRIVE_STRENGTH_2MA 0U
#define PINCTRL_DRIVE_STRENGTH_4MA 1U
#define PINCTRL_DRIVE_STRENGTH_8MA 2U
#define PINCTRL_DRIVE_STRENGTH_12MA 3U
void pm_api_pinctrl_get_function_name(uint32_t fid, char *name);
enum pm_ret_status pm_api_pinctrl_get_function_groups(uint32_t fid,
uint32_t index,
uint16_t *groups);
enum pm_ret_status pm_api_pinctrl_get_pin_groups(uint32_t pin,
uint32_t index,
uint16_t *groups);
enum pm_ret_status pm_api_pinctrl_get_num_pins(uint32_t *npins);
enum pm_ret_status pm_api_pinctrl_get_num_functions(uint32_t *nfuncs);
enum pm_ret_status pm_api_pinctrl_get_num_func_groups(uint32_t fid,
uint32_t *ngroups);
#endif /* PM_API_PINCTRL_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
+1836
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source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/pm_service/pm_api_sys.h
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/*
* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PM_API_SYS_H
#define PM_API_SYS_H
#include <stdint.h>
#include "pm_defs.h"
enum pm_query_id {
PM_QID_INVALID,
PM_QID_CLOCK_GET_NAME,
PM_QID_CLOCK_GET_TOPOLOGY,
PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
PM_QID_CLOCK_GET_PARENTS,
PM_QID_CLOCK_GET_ATTRIBUTES,
PM_QID_PINCTRL_GET_NUM_PINS,
PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
PM_QID_PINCTRL_GET_FUNCTION_NAME,
PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
PM_QID_PINCTRL_GET_PIN_GROUPS,
PM_QID_CLOCK_GET_NUM_CLOCKS,
PM_QID_CLOCK_GET_MAX_DIVISOR,
};
enum pm_register_access_id {
CONFIG_REG_WRITE,
CONFIG_REG_READ,
};
/**
* Assigning of argument values into array elements.
*/
#define PM_PACK_PAYLOAD1(pl, arg0) { \
pl[0] = (uint32_t)(arg0); \
}
#define PM_PACK_PAYLOAD2(pl, arg0, arg1) { \
pl[1] = (uint32_t)(arg1); \
PM_PACK_PAYLOAD1(pl, arg0); \
}
#define PM_PACK_PAYLOAD3(pl, arg0, arg1, arg2) { \
pl[2] = (uint32_t)(arg2); \
PM_PACK_PAYLOAD2(pl, arg0, arg1); \
}
#define PM_PACK_PAYLOAD4(pl, arg0, arg1, arg2, arg3) { \
pl[3] = (uint32_t)(arg3); \
PM_PACK_PAYLOAD3(pl, arg0, arg1, arg2); \
}
#define PM_PACK_PAYLOAD5(pl, arg0, arg1, arg2, arg3, arg4) { \
pl[4] = (uint32_t)(arg4); \
PM_PACK_PAYLOAD4(pl, arg0, arg1, arg2, arg3); \
}
#define PM_PACK_PAYLOAD6(pl, arg0, arg1, arg2, arg3, arg4, arg5) { \
pl[5] = (uint32_t)(arg5); \
PM_PACK_PAYLOAD5(pl, arg0, arg1, arg2, arg3, arg4); \
}
/**********************************************************
* System-level API function declarations
**********************************************************/
enum pm_ret_status pm_req_suspend(enum pm_node_id target,
enum pm_request_ack ack,
uint32_t latency,
uint32_t state);
enum pm_ret_status pm_self_suspend(enum pm_node_id nid,
uint32_t latency,
uint32_t state,
uintptr_t address);
enum pm_ret_status pm_force_powerdown(enum pm_node_id target,
enum pm_request_ack ack);
enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason);
enum pm_ret_status pm_req_wakeup(enum pm_node_id target,
uint32_t set_address,
uintptr_t address,
enum pm_request_ack ack);
enum pm_ret_status pm_set_wakeup_source(enum pm_node_id target,
enum pm_node_id wkup_node,
uint32_t enable);
enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype);
/* API functions for managing PM Slaves */
enum pm_ret_status pm_req_node(enum pm_node_id nid,
uint32_t capabilities,
uint32_t qos,
enum pm_request_ack ack);
enum pm_ret_status pm_set_requirement(enum pm_node_id nid,
uint32_t capabilities,
uint32_t qos,
enum pm_request_ack ack);
/* Miscellaneous API functions */
enum pm_ret_status pm_get_api_version(uint32_t *version);
enum pm_ret_status pm_get_node_status(enum pm_node_id nid,
uint32_t *ret_buff);
/* Direct-Control API functions */
enum pm_ret_status pm_mmio_write(uintptr_t address,
uint32_t mask,
uint32_t value);
enum pm_ret_status pm_mmio_read(uintptr_t address, uint32_t *value);
enum pm_ret_status pm_fpga_load(uint32_t address_low,
uint32_t address_high,
uint32_t size,
uint32_t flags);
enum pm_ret_status pm_fpga_get_status(uint32_t *value);
enum pm_ret_status pm_get_chipid(uint32_t *value);
enum pm_ret_status pm_secure_rsaaes(uint32_t address_low,
uint32_t address_high,
uint32_t size,
uint32_t flags);
uint32_t pm_get_shutdown_scope(void);
void pm_get_callbackdata(uint32_t *data, size_t count);
enum pm_ret_status pm_ioctl(enum pm_node_id nid,
uint32_t ioctl_id,
uint32_t arg1,
uint32_t arg2,
uint32_t *value);
enum pm_ret_status pm_clock_enable(uint32_t clock_id);
enum pm_ret_status pm_clock_disable(uint32_t clock_id);
enum pm_ret_status pm_clock_getstate(uint32_t clock_id,
uint32_t *state);
enum pm_ret_status pm_clock_setdivider(uint32_t clock_id,
uint32_t divider);
enum pm_ret_status pm_clock_getdivider(uint32_t clock_id,
uint32_t *divider);
enum pm_ret_status pm_clock_setrate(uint32_t clock_id,
uint64_t rate);
enum pm_ret_status pm_clock_getrate(uint32_t clock_id,
uint64_t *rate);
enum pm_ret_status pm_clock_setparent(uint32_t clock_id,
uint32_t parent_index);
enum pm_ret_status pm_clock_getparent(uint32_t clock_id,
uint32_t *parent_index);
void pm_query_data(enum pm_query_id qid, uint32_t arg1, uint32_t arg2,
uint32_t arg3, uint32_t *data);
enum pm_ret_status pm_sha_hash(uint32_t address_high,
uint32_t address_low,
uint32_t size,
uint32_t flags);
enum pm_ret_status pm_rsa_core(uint32_t address_high,
uint32_t address_low,
uint32_t size,
uint32_t flags);
enum pm_ret_status pm_secure_image(uint32_t address_low,
uint32_t address_high,
uint32_t key_lo,
uint32_t key_hi,
uint32_t *value);
enum pm_ret_status pm_fpga_read(uint32_t reg_numframes,
uint32_t address_low,
uint32_t address_high,
uint32_t readback_type,
uint32_t *value);
enum pm_ret_status pm_aes_engine(uint32_t address_high,
uint32_t address_low,
uint32_t *value);
enum pm_ret_status pm_register_access(uint32_t register_access_id,
uint32_t address,
uint32_t mask,
uint32_t value,
uint32_t *out);
enum pm_ret_status pm_pll_set_parameter(enum pm_node_id nid,
enum pm_pll_param param_id,
uint32_t value);
enum pm_ret_status pm_pll_get_parameter(enum pm_node_id nid,
enum pm_pll_param param_id,
uint32_t *value);
enum pm_ret_status pm_pll_set_mode(enum pm_node_id nid, enum pm_pll_mode mode);
enum pm_ret_status pm_pll_get_mode(enum pm_node_id nid, enum pm_pll_mode *mode);
enum pm_ret_status pm_efuse_access(uint32_t address_high,
uint32_t address_low, uint32_t *value);
enum pm_ret_status em_set_action(uint32_t *value);
enum pm_ret_status em_remove_action(uint32_t *value);
enum pm_ret_status em_send_errors(uint32_t *value);
enum pm_ret_status pm_feature_check(uint32_t api_id, uint32_t *version,
uint32_t *bit_mask, uint8_t len);
enum pm_ret_status check_api_dependency(uint8_t id);
#endif /* PM_API_SYS_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/pm_service/pm_client.c
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/*
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* APU specific definition of processors in the subsystem as well as functions
* for getting information about and changing state of the APU.
*/
#include <assert.h>
#include <string.h>
#include <common/bl_common.h>
#include <drivers/arm/gic_common.h>
#include <drivers/arm/gicv2.h>
#include <lib/bakery_lock.h>
#include <lib/mmio.h>
#include <lib/utils.h>
#include <plat_ipi.h>
#include <zynqmp_def.h>
#include "pm_api_sys.h"
#include "pm_client.h"
#include "pm_ipi.h"
#define IRQ_MAX 84U
#define NUM_GICD_ISENABLER ((IRQ_MAX >> 5U) + 1U)
#define UNDEFINED_CPUID (~0U)
#define PM_SUSPEND_MODE_STD 0U
#define PM_SUSPEND_MODE_POWER_OFF 1U
DEFINE_BAKERY_LOCK(pm_client_secure_lock);
extern const struct pm_ipi apu_ipi;
const struct pm_ipi apu_ipi = {
.local_ipi_id = IPI_ID_APU,
.remote_ipi_id = IPI_ID_PMU0,
.buffer_base = IPI_BUFFER_APU_BASE,
};
static uint32_t suspend_mode = PM_SUSPEND_MODE_STD;
/* Order in pm_procs_all array must match cpu ids */
static const struct pm_proc pm_procs_all[] = {
{
.node_id = NODE_APU_0,
.pwrdn_mask = APU_0_PWRCTL_CPUPWRDWNREQ_MASK,
.ipi = &apu_ipi,
},
{
.node_id = NODE_APU_1,
.pwrdn_mask = APU_1_PWRCTL_CPUPWRDWNREQ_MASK,
.ipi = &apu_ipi,
},
{
.node_id = NODE_APU_2,
.pwrdn_mask = APU_2_PWRCTL_CPUPWRDWNREQ_MASK,
.ipi = &apu_ipi,
},
{
.node_id = NODE_APU_3,
.pwrdn_mask = APU_3_PWRCTL_CPUPWRDWNREQ_MASK,
.ipi = &apu_ipi,
},
};
/* Interrupt to PM node ID map */
static enum pm_node_id irq_node_map[IRQ_MAX + 1U] = {
NODE_UNKNOWN,
NODE_UNKNOWN,
NODE_UNKNOWN,
NODE_UNKNOWN, /* 3 */
NODE_UNKNOWN,
NODE_UNKNOWN,
NODE_UNKNOWN,
NODE_UNKNOWN, /* 7 */
NODE_UNKNOWN,
NODE_UNKNOWN,
NODE_UNKNOWN,
NODE_UNKNOWN, /* 11 */
NODE_UNKNOWN,
NODE_UNKNOWN,
NODE_NAND,
NODE_QSPI, /* 15 */
NODE_GPIO,
NODE_I2C_0,
NODE_I2C_1,
NODE_SPI_0, /* 19 */
NODE_SPI_1,
NODE_UART_0,
NODE_UART_1,
NODE_CAN_0, /* 23 */
NODE_CAN_1,
NODE_UNKNOWN,
NODE_RTC,
NODE_RTC, /* 27 */
NODE_UNKNOWN,
NODE_UNKNOWN,
NODE_UNKNOWN,
NODE_UNKNOWN, /* 31 */
NODE_UNKNOWN,
NODE_UNKNOWN,
NODE_UNKNOWN,
NODE_UNKNOWN, /* 35, NODE_IPI_APU */
NODE_TTC_0,
NODE_TTC_0,
NODE_TTC_0,
NODE_TTC_1, /* 39 */
NODE_TTC_1,
NODE_TTC_1,
NODE_TTC_2,
NODE_TTC_2, /* 43 */
NODE_TTC_2,
NODE_TTC_3,
NODE_TTC_3,
NODE_TTC_3, /* 47 */
NODE_SD_0,
NODE_SD_1,
NODE_SD_0,
NODE_SD_1, /* 51 */
NODE_UNKNOWN,
NODE_UNKNOWN,
NODE_UNKNOWN,
NODE_UNKNOWN, /* 55 */
NODE_UNKNOWN,
NODE_ETH_0,
NODE_ETH_0,
NODE_ETH_1, /* 59 */
NODE_ETH_1,
NODE_ETH_2,
NODE_ETH_2,
NODE_ETH_3, /* 63 */
NODE_ETH_3,
NODE_USB_0,
NODE_USB_0,
NODE_USB_0, /* 67 */
NODE_USB_0,
NODE_USB_0,
NODE_USB_1,
NODE_USB_1, /* 71 */
NODE_USB_1,
NODE_USB_1,
NODE_USB_1,
NODE_USB_0, /* 75 */
NODE_USB_0,
NODE_ADMA,
NODE_ADMA,
NODE_ADMA, /* 79 */
NODE_ADMA,
NODE_ADMA,
NODE_ADMA,
NODE_ADMA, /* 83 */
NODE_ADMA,
};
/**
* irq_to_pm_node - Get PM node ID corresponding to the interrupt number
* @irq: Interrupt number
*
* Return: PM node ID corresponding to the specified interrupt
*/
static enum pm_node_id irq_to_pm_node(uint32_t irq)
{
assert(irq <= IRQ_MAX);
return irq_node_map[irq];
}
/**
* pm_client_set_wakeup_sources - Set all slaves with enabled interrupts as wake
* sources in the PMU firmware
*/
static void pm_client_set_wakeup_sources(void)
{
uint32_t reg_num;
uint8_t pm_wakeup_nodes_set[NODE_MAX] = { 0 };
uintptr_t isenabler1 = BASE_GICD_BASE + GICD_ISENABLER + 4U;
/* In case of power-off suspend, only NODE_EXTERN must be set */
if (suspend_mode == PM_SUSPEND_MODE_POWER_OFF) {
enum pm_ret_status ret;
ret = pm_set_wakeup_source(NODE_APU, NODE_EXTERN, 1U);
/**
* If NODE_EXTERN could not be set as wake source, proceed with
* standard suspend (no one will wake the system otherwise)
*/
if (ret == PM_RET_SUCCESS) {
return;
}
}
zeromem(&pm_wakeup_nodes_set, sizeof(pm_wakeup_nodes_set));
for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) {
uint32_t base_irq = reg_num << ISENABLER_SHIFT;
uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2U));
if (reg == 0) {
continue;
}
while (reg) {
enum pm_node_id node;
uint32_t idx, ret, irq, lowest_set = reg & (-reg);
idx = __builtin_ctz(lowest_set);
irq = base_irq + idx;
if (irq > IRQ_MAX) {
break;
}
node = irq_to_pm_node(irq);
reg &= ~lowest_set;
if (node > NODE_UNKNOWN && node < NODE_MAX) {
if (pm_wakeup_nodes_set[node] == 0U) {
ret = pm_set_wakeup_source(NODE_APU, node, 1U);
pm_wakeup_nodes_set[node] = (ret == PM_RET_SUCCESS) ? 1U : 0U;
}
}
}
}
}
/**
* pm_get_proc() - returns pointer to the proc structure
* @cpuid: id of the cpu whose proc struct pointer should be returned
*
* Return: pointer to a proc structure if proc is found, otherwise NULL
*/
const struct pm_proc *pm_get_proc(uint32_t cpuid)
{
if (cpuid < ARRAY_SIZE(pm_procs_all)) {
return &pm_procs_all[cpuid];
}
return NULL;
}
/**
* pm_get_proc_by_node() - returns pointer to the proc structure
* @nid: node id of the processor
*
* Return: pointer to a proc structure if proc is found, otherwise NULL
*/
const struct pm_proc *pm_get_proc_by_node(enum pm_node_id nid)
{
for (size_t i = 0; i < ARRAY_SIZE(pm_procs_all); i++) {
if (nid == pm_procs_all[i].node_id) {
return &pm_procs_all[i];
}
}
return NULL;
}
/**
* pm_get_cpuid() - get the local cpu ID for a global node ID
* @nid: node id of the processor
*
* Return: the cpu ID (starting from 0) for the subsystem
*/
static uint32_t pm_get_cpuid(enum pm_node_id nid)
{
for (size_t i = 0; i < ARRAY_SIZE(pm_procs_all); i++) {
if (pm_procs_all[i].node_id == nid) {
return i;
}
}
return UNDEFINED_CPUID;
}
const struct pm_proc *primary_proc = &pm_procs_all[0];
/**
* pm_client_suspend() - Client-specific suspend actions
*
* This function should contain any PU-specific actions
* required prior to sending suspend request to PMU
* Actions taken depend on the state system is suspending to.
*/
void pm_client_suspend(const struct pm_proc *proc, uint32_t state)
{
bakery_lock_get(&pm_client_secure_lock);
if (state == PM_STATE_SUSPEND_TO_RAM) {
pm_client_set_wakeup_sources();
}
/* Set powerdown request */
mmio_write_32(APU_PWRCTL, mmio_read_32(APU_PWRCTL) | proc->pwrdn_mask);
bakery_lock_release(&pm_client_secure_lock);
}
/**
* pm_client_abort_suspend() - Client-specific abort-suspend actions
*
* This function should contain any PU-specific actions
* required for aborting a prior suspend request
*/
void pm_client_abort_suspend(void)
{
/* Enable interrupts at processor level (for current cpu) */
gicv2_cpuif_enable();
bakery_lock_get(&pm_client_secure_lock);
/* Clear powerdown request */
mmio_write_32(APU_PWRCTL,
mmio_read_32(APU_PWRCTL) & ~primary_proc->pwrdn_mask);
bakery_lock_release(&pm_client_secure_lock);
}
/**
* pm_client_wakeup() - Client-specific wakeup actions
*
* This function should contain any PU-specific actions
* required for waking up another APU core
*/
void pm_client_wakeup(const struct pm_proc *proc)
{
uint32_t cpuid = pm_get_cpuid(proc->node_id);
if (cpuid == UNDEFINED_CPUID) {
return;
}
bakery_lock_get(&pm_client_secure_lock);
/* clear powerdown bit for affected cpu */
uint32_t val = mmio_read_32(APU_PWRCTL);
val &= ~(proc->pwrdn_mask);
mmio_write_32(APU_PWRCTL, val);
bakery_lock_release(&pm_client_secure_lock);
}
enum pm_ret_status pm_set_suspend_mode(uint32_t mode)
{
if ((mode != PM_SUSPEND_MODE_STD) &&
(mode != PM_SUSPEND_MODE_POWER_OFF)) {
return PM_RET_ERROR_ARGS;
}
suspend_mode = mode;
return PM_RET_SUCCESS;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/pm_service/pm_defs.h
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/*
* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* ZynqMP power management enums and defines */
#ifndef PM_DEFS_H
#define PM_DEFS_H
/*********************************************************************
* Macro definitions
********************************************************************/
/*
* Version number is a 32bit value, like:
* (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR
*/
#define PM_VERSION_MAJOR 1U
#define PM_VERSION_MINOR 1U
#define PM_VERSION ((PM_VERSION_MAJOR << 16U) | PM_VERSION_MINOR)
/**
* PM API versions
*/
/* Expected version of firmware APIs */
#define FW_API_BASE_VERSION (1U)
/* Expected version of firmware API for feature check */
#define FW_API_VERSION_2 (2U)
/* Version of APIs implemented in ATF */
#define ATF_API_BASE_VERSION (1U)
/* Capabilities for RAM */
#define PM_CAP_ACCESS 0x1U
#define PM_CAP_CONTEXT 0x2U
#define MAX_LATENCY (~0U)
#define MAX_QOS 100U
/* State arguments of the self suspend */
#define PM_STATE_CPU_IDLE 0x0U
#define PM_STATE_SUSPEND_TO_RAM 0xFU
/* APU processor states */
#define PM_PROC_STATE_FORCEDOFF 0U
#define PM_PROC_STATE_ACTIVE 1U
#define PM_PROC_STATE_SLEEP 2U
#define PM_PROC_STATE_SUSPENDING 3U
#define EM_FUNID_NUM_MASK 0xF0000U
#define PM_GET_CALLBACK_DATA 0xa01
#define PM_SET_SUSPEND_MODE 0xa02
#define PM_GET_TRUSTZONE_VERSION 0xa03
/*********************************************************************
* Enum definitions
********************************************************************/
enum pm_api_id {
/* Miscellaneous API functions: */
PM_GET_API_VERSION = 1, /* Do not change or move */
PM_SET_CONFIGURATION,
PM_GET_NODE_STATUS,
PM_GET_OP_CHARACTERISTIC,
PM_REGISTER_NOTIFIER,
/* API for suspending of PUs: */
PM_REQ_SUSPEND,
PM_SELF_SUSPEND,
PM_FORCE_POWERDOWN,
PM_ABORT_SUSPEND,
PM_REQ_WAKEUP,
PM_SET_WAKEUP_SOURCE,
PM_SYSTEM_SHUTDOWN,
/* API for managing PM slaves: */
PM_REQ_NODE,
PM_RELEASE_NODE,
PM_SET_REQUIREMENT,
PM_SET_MAX_LATENCY,
/* Direct control API functions: */
PM_RESET_ASSERT,
PM_RESET_GET_STATUS,
PM_MMIO_WRITE,
PM_MMIO_READ,
PM_INIT_FINALIZE,
PM_FPGA_LOAD,
PM_FPGA_GET_STATUS,
PM_GET_CHIPID,
PM_SECURE_RSA_AES,
PM_SECURE_SHA,
PM_SECURE_RSA,
PM_PINCTRL_REQUEST,
PM_PINCTRL_RELEASE,
PM_PINCTRL_GET_FUNCTION,
PM_PINCTRL_SET_FUNCTION,
PM_PINCTRL_CONFIG_PARAM_GET,
PM_PINCTRL_CONFIG_PARAM_SET,
PM_IOCTL,
/* API to query information from firmware */
PM_QUERY_DATA,
/* Clock control API functions */
PM_CLOCK_ENABLE,
PM_CLOCK_DISABLE,
PM_CLOCK_GETSTATE,
PM_CLOCK_SETDIVIDER,
PM_CLOCK_GETDIVIDER,
PM_CLOCK_SETRATE,
PM_CLOCK_GETRATE,
PM_CLOCK_SETPARENT,
PM_CLOCK_GETPARENT,
PM_SECURE_IMAGE,
/* FPGA PL Readback */
PM_FPGA_READ,
PM_SECURE_AES,
/* PLL control API functions */
PM_PLL_SET_PARAMETER,
PM_PLL_GET_PARAMETER,
PM_PLL_SET_MODE,
PM_PLL_GET_MODE,
/* PM Register Access API */
PM_REGISTER_ACCESS,
PM_EFUSE_ACCESS,
PM_FPGA_GET_VERSION,
PM_FPGA_GET_FEATURE_LIST,
PM_FEATURE_CHECK = 63,
PM_API_MAX
};
enum pm_node_id {
NODE_UNKNOWN = 0,
NODE_APU,
NODE_APU_0,
NODE_APU_1,
NODE_APU_2,
NODE_APU_3,
NODE_RPU,
NODE_RPU_0,
NODE_RPU_1,
NODE_PLD,
NODE_FPD,
NODE_OCM_BANK_0,
NODE_OCM_BANK_1,
NODE_OCM_BANK_2,
NODE_OCM_BANK_3,
NODE_TCM_0_A,
NODE_TCM_0_B,
NODE_TCM_1_A,
NODE_TCM_1_B,
NODE_L2,
NODE_GPU_PP_0,
NODE_GPU_PP_1,
NODE_USB_0,
NODE_USB_1,
NODE_TTC_0,
NODE_TTC_1,
NODE_TTC_2,
NODE_TTC_3,
NODE_SATA,
NODE_ETH_0,
NODE_ETH_1,
NODE_ETH_2,
NODE_ETH_3,
NODE_UART_0,
NODE_UART_1,
NODE_SPI_0,
NODE_SPI_1,
NODE_I2C_0,
NODE_I2C_1,
NODE_SD_0,
NODE_SD_1,
NODE_DP,
NODE_GDMA,
NODE_ADMA,
NODE_NAND,
NODE_QSPI,
NODE_GPIO,
NODE_CAN_0,
NODE_CAN_1,
NODE_EXTERN,
NODE_APLL,
NODE_VPLL,
NODE_DPLL,
NODE_RPLL,
NODE_IOPLL,
NODE_DDR,
NODE_IPI_APU,
NODE_IPI_RPU_0,
NODE_GPU,
NODE_PCIE,
NODE_PCAP,
NODE_RTC,
NODE_LPD,
NODE_VCU,
NODE_IPI_RPU_1,
NODE_IPI_PL_0,
NODE_IPI_PL_1,
NODE_IPI_PL_2,
NODE_IPI_PL_3,
NODE_PL,
NODE_GEM_TSU,
NODE_SWDT_0,
NODE_SWDT_1,
NODE_CSU,
NODE_PJTAG,
NODE_TRACE,
NODE_TESTSCAN,
NODE_PMU,
NODE_MAX,
};
enum pm_request_ack {
REQ_ACK_NO = 1,
REQ_ACK_BLOCKING,
REQ_ACK_NON_BLOCKING,
};
enum pm_abort_reason {
ABORT_REASON_WKUP_EVENT = 100,
ABORT_REASON_PU_BUSY,
ABORT_REASON_NO_PWRDN,
ABORT_REASON_UNKNOWN,
};
enum pm_suspend_reason {
SUSPEND_REASON_PU_REQ = 201,
SUSPEND_REASON_ALERT,
SUSPEND_REASON_SYS_SHUTDOWN,
};
enum pm_ram_state {
PM_RAM_STATE_OFF = 1,
PM_RAM_STATE_RETENTION,
PM_RAM_STATE_ON,
};
enum pm_opchar_type {
PM_OPCHAR_TYPE_POWER = 1,
PM_OPCHAR_TYPE_TEMP,
PM_OPCHAR_TYPE_LATENCY,
};
/**
* @PM_RET_SUCCESS: success
* @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated)
* @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated)
* @PM_RET_ERROR_NOT_ENABLED: feature is not enabled
* @PM_RET_ERROR_INTERNAL: internal error
* @PM_RET_ERROR_CONFLICT: conflict
* @PM_RET_ERROR_ACCESS: access rights violation
* @PM_RET_ERROR_INVALID_NODE: invalid node
* @PM_RET_ERROR_DOUBLE_REQ: duplicate request for same node
* @PM_RET_ERROR_ABORT_SUSPEND: suspend procedure has been aborted
* @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU
* @PM_RET_ERROR_NODE_USED: node is already in use
*/
enum pm_ret_status {
PM_RET_SUCCESS = (0U),
PM_RET_ERROR_ARGS = (1U),
PM_RET_ERROR_NOTSUPPORTED = (4U),
PM_RET_ERROR_NOT_ENABLED = (29U),
PM_RET_ERROR_INTERNAL = (2000U),
PM_RET_ERROR_CONFLICT = (2001U),
PM_RET_ERROR_ACCESS = (2002U),
PM_RET_ERROR_INVALID_NODE = (2003U),
PM_RET_ERROR_DOUBLE_REQ = (2004U),
PM_RET_ERROR_ABORT_SUSPEND = (2005U),
PM_RET_ERROR_TIMEOUT = (2006U),
PM_RET_ERROR_NODE_USED = (2007U),
PM_RET_ERROR_NO_FEATURE = (2008U)
};
/**
* @PM_INITIAL_BOOT: boot is a fresh system startup
* @PM_RESUME: boot is a resume
* @PM_BOOT_ERROR: error, boot cause cannot be identified
*/
enum pm_boot_status {
PM_INITIAL_BOOT,
PM_RESUME,
PM_BOOT_ERROR,
};
/**
* @PMF_SHUTDOWN_TYPE_SHUTDOWN: shutdown
* @PMF_SHUTDOWN_TYPE_RESET: reset/reboot
* @PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY: set the shutdown/reboot scope
*/
enum pm_shutdown_type {
PMF_SHUTDOWN_TYPE_SHUTDOWN,
PMF_SHUTDOWN_TYPE_RESET,
PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY,
};
/**
* @PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM: shutdown/reboot APU subsystem only
* @PMF_SHUTDOWN_SUBTYPE_PS_ONLY: shutdown/reboot entire PS (but not PL)
* @PMF_SHUTDOWN_SUBTYPE_SYSTEM: shutdown/reboot entire system
*/
enum pm_shutdown_subtype {
PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM,
PMF_SHUTDOWN_SUBTYPE_PS_ONLY,
PMF_SHUTDOWN_SUBTYPE_SYSTEM,
};
/**
* @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL
* @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL
* @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL
* @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input
* @PM_PLL_PARAM_POST_SRC: Clock source for PLL Bypass mode
* @PM_PLL_PARAM_LOCK_DLY: Lock circuit config settings for lock windowsize
* @PM_PLL_PARAM_LOCK_CNT: Lock circuit counter setting
* @PM_PLL_PARAM_LFHF: PLL loop filter high frequency capacitor control
* @PM_PLL_PARAM_CP: PLL charge pump control
* @PM_PLL_PARAM_RES: PLL loop filter resistor control
*/
enum pm_pll_param {
PM_PLL_PARAM_DIV2,
PM_PLL_PARAM_FBDIV,
PM_PLL_PARAM_DATA,
PM_PLL_PARAM_PRE_SRC,
PM_PLL_PARAM_POST_SRC,
PM_PLL_PARAM_LOCK_DLY,
PM_PLL_PARAM_LOCK_CNT,
PM_PLL_PARAM_LFHF,
PM_PLL_PARAM_CP,
PM_PLL_PARAM_RES,
PM_PLL_PARAM_MAX,
};
/**
* @PM_PLL_MODE_RESET: PLL is in reset (not locked)
* @PM_PLL_MODE_INTEGER: PLL is locked in integer mode
* @PM_PLL_MODE_FRACTIONAL: PLL is locked in fractional mode
*/
enum pm_pll_mode {
PM_PLL_MODE_RESET,
PM_PLL_MODE_INTEGER,
PM_PLL_MODE_FRACTIONAL,
PM_PLL_MODE_MAX,
};
/**
* @PM_CLOCK_DIV0_ID: Clock divider 0
* @PM_CLOCK_DIV1_ID: Clock divider 1
*/
enum pm_clock_div_id {
PM_CLOCK_DIV0_ID,
PM_CLOCK_DIV1_ID,
};
/**
* EM API IDs
*/
enum em_api_id {
EM_SET_ACTION = 1,
EM_REMOVE_ACTION,
EM_SEND_ERRORS,
};
#endif /* PM_DEFS_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
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/*
* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* Top-level SMC handler for ZynqMP power management calls and
* IPI setup functions for communication with PMU.
*/
#include <errno.h>
#include <common/runtime_svc.h>
#if ZYNQMP_WDT_RESTART
#include <arch_helpers.h>
#include <drivers/arm/gicv2.h>
#include <lib/mmio.h>
#include <lib/spinlock.h>
#include <plat/common/platform.h>
#endif
#include <plat_private.h>
#include "pm_api_sys.h"
#include "pm_client.h"
#include "pm_defs.h"
#include "pm_ipi.h"
/* pm_up = !0 - UP, pm_up = 0 - DOWN */
static int32_t pm_up, ipi_irq_flag;
#if ZYNQMP_WDT_RESTART
static spinlock_t inc_lock;
static int active_cores = 0;
#endif
/**
* pm_context - Structure which contains data for power management
* @api_version version of PM API, must match with one on PMU side
* @payload payload array used to store received
* data from ipi buffer registers
*/
static struct {
uint32_t api_version;
uint32_t payload[PAYLOAD_ARG_CNT];
} pm_ctx;
#if ZYNQMP_WDT_RESTART
/**
* trigger_wdt_restart() - Trigger warm restart event to APU cores
*
* This function triggers SGI for all active APU CPUs. SGI handler then
* power down CPU and call system reset.
*/
static void trigger_wdt_restart(void)
{
uint32_t core_count = 0;
uint32_t core_status[3];
uint32_t target_cpu_list = 0;
int i;
for (i = 0; i < 4; i++) {
pm_get_node_status(NODE_APU_0 + i, core_status);
if (core_status[0] == 1) {
core_count++;
target_cpu_list |= (1 << i);
}
}
spin_lock(&inc_lock);
active_cores = core_count;
spin_unlock(&inc_lock);
INFO("Active Cores: %d\n", active_cores);
for (i = PLATFORM_CORE_COUNT - 1; i >= 0; i--) {
if (target_cpu_list & (1 << i)) {
/* trigger SGI to active cores */
plat_ic_raise_el3_sgi(ARM_IRQ_SEC_SGI_7, i);
}
}
}
/**
* ttc_fiq_handler() - TTC Handler for timer event
* @id number of the highest priority pending interrupt of the type
* that this handler was registered for
* @flags security state, bit[0]
* @handler pointer to 'cpu_context' structure of the current CPU for the
* security state specified in the 'flags' parameter
* @cookie unused
*
* Function registered as INTR_TYPE_EL3 interrupt handler
*
* When WDT event is received in PMU, PMU needs to notify master to do cleanup
* if required. PMU sets up timer and starts timer to overflow in zero time upon
* WDT event. ATF handles this timer event and takes necessary action required
* for warm restart.
*
* In presence of non-secure software layers (EL1/2) sets the interrupt
* at registered entrance in GIC and informs that PMU responsed or demands
* action.
*/
static uint64_t ttc_fiq_handler(uint32_t id, uint32_t flags, void *handle,
void *cookie)
{
INFO("BL31: Got TTC FIQ\n");
plat_ic_end_of_interrupt(id);
/* Clear TTC interrupt by reading interrupt register */
mmio_read_32(TTC3_INTR_REGISTER_1);
/* Disable the timer interrupts */
mmio_write_32(TTC3_INTR_ENABLE_1, 0);
trigger_wdt_restart();
return 0;
}
/**
* zynqmp_sgi7_irq() - Handler for SGI7 IRQ
* @id number of the highest priority pending interrupt of the type
* that this handler was registered for
* @flags security state, bit[0]
* @handler pointer to 'cpu_context' structure of the current CPU for the
* security state specified in the 'flags' parameter
* @cookie unused
*
* Function registered as INTR_TYPE_EL3 interrupt handler
*
* On receiving WDT event from PMU, ATF generates SGI7 to all running CPUs.
* In response to SGI7 interrupt, each CPUs do clean up if required and last
* running CPU calls system restart.
*/
static uint64_t __unused __dead2 zynqmp_sgi7_irq(uint32_t id, uint32_t flags,
void *handle, void *cookie)
{
int i;
uint32_t value;
/* enter wfi and stay there */
INFO("Entering wfi\n");
spin_lock(&inc_lock);
active_cores--;
for (i = 0; i < 4; i++) {
mmio_write_32(BASE_GICD_BASE + GICD_CPENDSGIR + 4 * i,
0xffffffff);
}
dsb();
spin_unlock(&inc_lock);
if (active_cores == 0) {
pm_mmio_read(PMU_GLOBAL_GEN_STORAGE4, &value);
value = (value & RESTART_SCOPE_MASK) >> RESTART_SCOPE_SHIFT;
pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET, value);
}
/* enter wfi and stay there */
while (1)
wfi();
}
/**
* pm_wdt_restart_setup() - Setup warm restart interrupts
*
* This function sets up handler for SGI7 and TTC interrupts
* used for warm restart.
*/
static int pm_wdt_restart_setup(void)
{
int ret;
/* register IRQ handler for SGI7 */
ret = request_intr_type_el3(ARM_IRQ_SEC_SGI_7, zynqmp_sgi7_irq);
if (ret) {
WARN("BL31: registering SGI7 interrupt failed\n");
goto err;
}
ret = request_intr_type_el3(IRQ_TTC3_1, ttc_fiq_handler);
if (ret)
WARN("BL31: registering TTC3 interrupt failed\n");
err:
return ret;
}
#endif
/**
* pm_setup() - PM service setup
*
* @return On success, the initialization function must return 0.
* Any other return value will cause the framework to ignore
* the service
*
* Initialization functions for ZynqMP power management for
* communicaton with PMU.
*
* Called from sip_svc_setup initialization function with the
* rt_svc_init signature.
*/
int32_t pm_setup(void)
{
pm_ipi_init(primary_proc);
pm_get_api_version(&pm_ctx.api_version);
if (pm_ctx.api_version < PM_VERSION) {
ERROR("BL31: Platform Management API version error. Expected: "
"v%d.%d - Found: v%d.%d\n", PM_VERSION_MAJOR,
PM_VERSION_MINOR, pm_ctx.api_version >> 16,
pm_ctx.api_version & 0xFFFFU);
return -EINVAL;
}
int32_t status = 0, ret = 0;
#if ZYNQMP_WDT_RESTART
status = pm_wdt_restart_setup();
if (status)
WARN("BL31: warm-restart setup failed\n");
#endif
if (status >= 0) {
INFO("BL31: PM Service Init Complete: API v%d.%d\n",
PM_VERSION_MAJOR, PM_VERSION_MINOR);
ret = 0;
} else {
INFO("BL31: PM Service Init Failed, Error Code %d!\n", status);
ret = status;
}
pm_up = !status;
return ret;
}
/**
* pm_smc_handler() - SMC handler for PM-API calls coming from EL1/EL2.
* @smc_fid - Function Identifier
* @x1 - x4 - Arguments
* @cookie - Unused
* @handler - Pointer to caller's context structure
*
* @return - Unused
*
* Determines that smc_fid is valid and supported PM SMC Function ID from the
* list of pm_api_ids, otherwise completes the request with
* the unknown SMC Function ID
*
* The SMC calls for PM service are forwarded from SIP Service SMC handler
* function with rt_svc_handle signature
*/
uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint64_t x4, const void *cookie, void *handle, uint64_t flags)
{
enum pm_ret_status ret;
uint32_t payload[PAYLOAD_ARG_CNT];
uint32_t pm_arg[5];
uint32_t result[PAYLOAD_ARG_CNT] = {0};
uint32_t api_id;
/* Handle case where PM wasn't initialized properly */
if (pm_up == 0)
SMC_RET1(handle, SMC_UNK);
pm_arg[0] = (uint32_t)x1;
pm_arg[1] = (uint32_t)(x1 >> 32);
pm_arg[2] = (uint32_t)x2;
pm_arg[3] = (uint32_t)(x2 >> 32);
pm_arg[4] = (uint32_t)x3;
api_id = smc_fid & FUNCID_NUM_MASK;
switch (api_id) {
/* PM API Functions */
case PM_SELF_SUSPEND:
ret = pm_self_suspend(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3]);
SMC_RET1(handle, (uint64_t)ret);
case PM_REQ_SUSPEND:
ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3]);
SMC_RET1(handle, (uint64_t)ret);
case PM_REQ_WAKEUP:
{
/* Use address flag is encoded in the 1st bit of the low-word */
uint32_t set_addr = pm_arg[1] & 0x1U;
uint64_t address = (uint64_t)pm_arg[2] << 32U;
address |= pm_arg[1] & (~0x1U);
ret = pm_req_wakeup(pm_arg[0], set_addr, address,
pm_arg[3]);
SMC_RET1(handle, (uint64_t)ret);
}
case PM_FORCE_POWERDOWN:
ret = pm_force_powerdown(pm_arg[0], pm_arg[1]);
SMC_RET1(handle, (uint64_t)ret);
case PM_ABORT_SUSPEND:
ret = pm_abort_suspend(pm_arg[0]);
SMC_RET1(handle, (uint64_t)ret);
case PM_SET_WAKEUP_SOURCE:
ret = pm_set_wakeup_source(pm_arg[0], pm_arg[1], pm_arg[2]);
SMC_RET1(handle, (uint64_t)ret);
case PM_SYSTEM_SHUTDOWN:
ret = pm_system_shutdown(pm_arg[0], pm_arg[1]);
SMC_RET1(handle, (uint64_t)ret);
case PM_REQ_NODE:
ret = pm_req_node(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]);
SMC_RET1(handle, (uint64_t)ret);
case PM_SET_REQUIREMENT:
ret = pm_set_requirement(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3]);
SMC_RET1(handle, (uint64_t)ret);
case PM_GET_API_VERSION:
/* Check is PM API version already verified */
if (pm_ctx.api_version >= PM_VERSION) {
if (ipi_irq_flag == 0U) {
/*
* Enable IPI IRQ
* assume the rich OS is OK to handle callback IRQs now.
* Even if we were wrong, it would not enable the IRQ in
* the GIC.
*/
pm_ipi_irq_enable(primary_proc);
ipi_irq_flag = 1U;
}
SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS |
((uint64_t)pm_ctx.api_version << 32));
}
case PM_FPGA_LOAD:
ret = pm_fpga_load(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]);
SMC_RET1(handle, (uint64_t)ret);
case PM_FPGA_GET_STATUS:
{
uint32_t value = 0;
ret = pm_fpga_get_status(&value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
}
case PM_SECURE_RSA_AES:
ret = pm_secure_rsaaes(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3]);
SMC_RET1(handle, (uint64_t)ret);
case PM_GET_CALLBACK_DATA:
pm_get_callbackdata(result, ARRAY_SIZE(result));
SMC_RET2(handle,
(uint64_t)result[0] | ((uint64_t)result[1] << 32),
(uint64_t)result[2] | ((uint64_t)result[3] << 32));
case PM_IOCTL:
{
uint32_t value = 0;
ret = pm_ioctl(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
}
case PM_QUERY_DATA:
{
uint32_t data[4] = { 0 };
pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], data);
SMC_RET2(handle, (uint64_t)data[0] | ((uint64_t)data[1] << 32),
(uint64_t)data[2] | ((uint64_t)data[3] << 32));
}
case PM_CLOCK_ENABLE:
ret = pm_clock_enable(pm_arg[0]);
SMC_RET1(handle, (uint64_t)ret);
case PM_CLOCK_DISABLE:
ret = pm_clock_disable(pm_arg[0]);
SMC_RET1(handle, (uint64_t)ret);
case PM_CLOCK_GETSTATE:
{
uint32_t value = 0;
ret = pm_clock_getstate(pm_arg[0], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
}
case PM_CLOCK_SETDIVIDER:
ret = pm_clock_setdivider(pm_arg[0], pm_arg[1]);
SMC_RET1(handle, (uint64_t)ret);
case PM_CLOCK_GETDIVIDER:
{
uint32_t value = 0;
ret = pm_clock_getdivider(pm_arg[0], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
}
case PM_CLOCK_SETRATE:
ret = pm_clock_setrate(pm_arg[0],
((uint64_t)pm_arg[2]) << 32 | pm_arg[1]);
SMC_RET1(handle, (uint64_t)ret);
case PM_CLOCK_GETRATE:
{
uint64_t value = 0;
ret = pm_clock_getrate(pm_arg[0], &value);
SMC_RET2(handle, (uint64_t)ret |
(((uint64_t)value & 0xFFFFFFFFU) << 32U),
(value >> 32U) & 0xFFFFFFFFU);
}
case PM_CLOCK_SETPARENT:
ret = pm_clock_setparent(pm_arg[0], pm_arg[1]);
SMC_RET1(handle, (uint64_t)ret);
case PM_CLOCK_GETPARENT:
{
uint32_t value = 0;
ret = pm_clock_getparent(pm_arg[0], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
}
case PM_GET_TRUSTZONE_VERSION:
SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS |
((uint64_t)ZYNQMP_TZ_VERSION << 32U));
case PM_SET_SUSPEND_MODE:
ret = pm_set_suspend_mode(pm_arg[0]);
SMC_RET1(handle, (uint64_t)ret);
case PM_SECURE_SHA:
ret = pm_sha_hash(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3]);
SMC_RET1(handle, (uint64_t)ret);
case PM_SECURE_RSA:
ret = pm_rsa_core(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3]);
SMC_RET1(handle, (uint64_t)ret);
case PM_SECURE_IMAGE:
{
ret = pm_secure_image(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], &result[0]);
SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U),
result[1]);
}
case PM_FPGA_READ:
{
uint32_t value = 0;
ret = pm_fpga_read(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3],
&value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
}
case PM_SECURE_AES:
{
uint32_t value = 0;
ret = pm_aes_engine(pm_arg[0], pm_arg[1], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
}
case PM_PLL_SET_PARAMETER:
ret = pm_pll_set_parameter(pm_arg[0], pm_arg[1], pm_arg[2]);
SMC_RET1(handle, (uint64_t)ret);
case PM_PLL_GET_PARAMETER:
{
uint32_t value = 0;
ret = pm_pll_get_parameter(pm_arg[0], pm_arg[1], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32U));
}
case PM_PLL_SET_MODE:
ret = pm_pll_set_mode(pm_arg[0], pm_arg[1]);
SMC_RET1(handle, (uint64_t)ret);
case PM_PLL_GET_MODE:
{
uint32_t mode = 0;
ret = pm_pll_get_mode(pm_arg[0], &mode);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32U));
}
case PM_REGISTER_ACCESS:
{
uint32_t value = 0;
ret = pm_register_access(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
}
case PM_EFUSE_ACCESS:
{
uint32_t value = 0;
#if defined(ZYNQMP_SECURE_EFUSES)
if (is_caller_non_secure(flags)) {
SMC_RET1(handle,
(((uint64_t)PM_RET_ERROR_NOT_ENABLED) << 32U) |
(uint64_t)PM_RET_ERROR_ACCESS);
}
#endif
ret = pm_efuse_access(pm_arg[0], pm_arg[1], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
}
case PM_FPGA_GET_VERSION:
case PM_FPGA_GET_FEATURE_LIST:
{
uint32_t ret_payload[PAYLOAD_ARG_CNT];
PM_PACK_PAYLOAD5(payload, smc_fid & FUNCID_NUM_MASK,
pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]);
ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, 3U);
SMC_RET2(handle, (uint64_t)ret | (uint64_t)ret_payload[0] << 32U,
(uint64_t)ret_payload[1] | (uint64_t)ret_payload[2] << 32U);
}
case PM_FEATURE_CHECK:
{
uint32_t version = 0;
uint32_t bit_mask[2] = {0};
ret = pm_feature_check(pm_arg[0], &version, bit_mask,
ARRAY_SIZE(bit_mask));
SMC_RET2(handle, (uint64_t)ret | ((uint64_t)version << 32U),
(uint64_t)bit_mask[0] | ((uint64_t)bit_mask[1] << 32U));
}
default:
/* Send request to the PMU */
PM_PACK_PAYLOAD6(payload, api_id, pm_arg[0], pm_arg[1],
pm_arg[2], pm_arg[3], pm_arg[4]);
ret = pm_ipi_send_sync(primary_proc, payload, result,
PAYLOAD_ARG_CNT);
SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U),
(uint64_t)result[1] | ((uint64_t)result[2] << 32U));
}
}
/**
* em_smc_handler() - SMC handler for EM-API calls coming from EL1/EL2.
* @smc_fid - Function Identifier
* @x1 - x4 - Arguments
* @cookie - Unused
* @handler - Pointer to caller's context structure
*
* @return - Unused
*
* Determines that smc_fid is valid and supported EM SMC Function ID from the
* list of em_api_ids, otherwise completes the request with
* the unknown SMC Function ID
*
* The SMC calls for EM service are forwarded from SIP Service SMC handler
* function with rt_svc_handle signature
*/
uint64_t em_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint64_t x4, const void *cookie, void *handle, uint64_t flags)
{
enum pm_ret_status ret;
switch (smc_fid & FUNCID_NUM_MASK) {
/* EM API Functions */
case EM_SET_ACTION:
{
uint32_t value;
ret = em_set_action(&value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
}
case EM_REMOVE_ACTION:
{
uint32_t value;
ret = em_remove_action(&value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
}
case EM_SEND_ERRORS:
{
uint32_t value;
ret = em_send_errors(&value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
}
default:
WARN("Unimplemented EM Service Call: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
}
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/pm_service/pm_svc_main.h
+20
View File
@@ -0,0 +1,20 @@
/*
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PM_SVC_MAIN_H
#define PM_SVC_MAIN_H
#include "pm_common.h"
int32_t pm_setup(void);
uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint64_t x4, const void *cookie, void *handle,
uint64_t flags);
uint64_t em_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint64_t x4, const void *cookie, void *handle,
uint64_t flags);
#endif /* PM_SVC_MAIN_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/sip_svc_setup.c
+105
View File
@@ -0,0 +1,105 @@
/*
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* Top level SMC handler for SiP calls. Dispatch PM calls to PM SMC handler. */
#include <common/runtime_svc.h>
#include <tools_share/uuid.h>
#include "ipi_mailbox_svc.h"
#include "pm_svc_main.h"
/* SMC function IDs for SiP Service queries */
#define ZYNQMP_SIP_SVC_CALL_COUNT U(0x8200ff00)
#define ZYNQMP_SIP_SVC_UID U(0x8200ff01)
#define ZYNQMP_SIP_SVC_VERSION U(0x8200ff03)
/* SiP Service Calls version numbers */
#define SIP_SVC_VERSION_MAJOR 0
#define SIP_SVC_VERSION_MINOR 1
/* These macros are used to identify PM, IPI calls from the SMC function ID */
#define PM_FID_MASK 0xf000u
#define PM_FID_VALUE 0u
#define IPI_FID_VALUE 0x1000u
#define EM_FID_MASK 0xf0000u
#define EM_FID_VALUE 0xE0000u
#define is_em_fid(_fid) (((_fid) & EM_FID_MASK) == EM_FID_VALUE)
#define is_pm_fid(_fid) (((_fid) & PM_FID_MASK) == PM_FID_VALUE)
#define is_ipi_fid(_fid) (((_fid) & PM_FID_MASK) == IPI_FID_VALUE)
/* SiP Service UUID */
DEFINE_SVC_UUID2(zynqmp_sip_uuid,
0x5c9b1b2a, 0x0586, 0x2340, 0xa6, 0x1b,
0xb9, 0x25, 0x82, 0x2d, 0xe3, 0xa5);
/**
* sip_svc_setup() - Setup SiP Service
*
* Invokes PM setup
*/
static int32_t sip_svc_setup(void)
{
/* PM implementation as SiP Service */
return pm_setup();
}
/**
* sip_svc_smc_handler() - Top-level SiP Service SMC handler
*
* Handler for all SiP SMC calls. Handles standard SIP requests
* and calls PM SMC handler if the call is for a PM-API function.
*/
static uintptr_t sip_svc_smc_handler(uint32_t smc_fid,
u_register_t x1,
u_register_t x2,
u_register_t x3,
u_register_t x4,
void *cookie,
void *handle,
u_register_t flags)
{
/* Let EM SMC handler deal with EM-related requests */
if (is_em_fid(smc_fid)) {
return em_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle,
flags);
} else if (is_pm_fid(smc_fid)) {
/* Let PM SMC handler deal with PM-related requests */
return pm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle,
flags);
}
/* Let IPI SMC handler deal with IPI-related requests */
if (is_ipi_fid(smc_fid)) {
return ipi_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle,
flags);
}
switch (smc_fid) {
case ZYNQMP_SIP_SVC_CALL_COUNT:
/* PM functions + default functions */
SMC_RET1(handle, PM_API_MAX + 2);
case ZYNQMP_SIP_SVC_UID:
SMC_UUID_RET(handle, zynqmp_sip_uuid);
case ZYNQMP_SIP_SVC_VERSION:
SMC_RET2(handle, SIP_SVC_VERSION_MAJOR, SIP_SVC_VERSION_MINOR);
default:
WARN("Unimplemented SiP Service Call: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
}
}
/* Register PM Service Calls as runtime service */
DECLARE_RT_SVC(
sip_svc,
OEN_SIP_START,
OEN_SIP_END,
(uint8_t)SMC_TYPE_FAST,
sip_svc_setup,
sip_svc_smc_handler);
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/tsp/tsp-zynqmp.mk
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#
# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
# TSP source files specific to ZynqMP platform
BL32_SOURCES += plat/common/aarch64/platform_mp_stack.S \
plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
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/*
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/console.h>
#include <plat/arm/common/plat_arm.h>
#include <plat_private.h>
#include <platform_tsp.h>
/*******************************************************************************
* Initialize the UART
******************************************************************************/
void tsp_early_platform_setup(void)
{
/*
* Register a different console than already in use to display
* messages from TSP
*/
static console_t tsp_boot_console;
(void)console_cdns_register(ZYNQMP_UART_BASE,
zynqmp_get_uart_clk(),
ZYNQMP_UART_BAUDRATE,
&tsp_boot_console);
console_set_scope(&tsp_boot_console,
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT);
/* Initialize the platform config for future decision making */
zynqmp_config_setup();
}
/*******************************************************************************
* Perform platform specific setup placeholder
******************************************************************************/
void tsp_platform_setup(void)
{
plat_arm_gic_driver_init();
plat_arm_gic_init();
}
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the MMU
******************************************************************************/
void tsp_plat_arch_setup(void)
{
const mmap_region_t bl_regions[] = {
MAP_REGION_FLAT(BL32_BASE, BL32_END - BL32_BASE,
MT_MEMORY | MT_RW | MT_SECURE),
MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE),
MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
MT_RO_DATA | MT_SECURE),
MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
MT_DEVICE | MT_RW | MT_SECURE),
{0}
};
setup_page_tables(bl_regions, plat_arm_get_mmap());
enable_mmu_el1(0);
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/zynqmp_ehf.c
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/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) Siemens AG, 2020-2021
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <platform_def.h>
#include <bl31/ehf.h>
/*
* Enumeration of priority levels on ARM platforms.
*/
ehf_pri_desc_t zynqmp_exceptions[] = {
/* Critical priority SDEI */
EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_CRITICAL_PRI),
/* Normal priority SDEI */
EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_NORMAL_PRI),
};
/* Plug in ARM exceptions to Exception Handling Framework. */
EHF_REGISTER_PRIORITIES(zynqmp_exceptions, ARRAY_SIZE(zynqmp_exceptions), PLAT_PRI_BITS);
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/zynqmp_ipi.c
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/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* Zynq UltraScale+ MPSoC IPI agent registers access management
*/
#include <errno.h>
#include <string.h>
#include <common/debug.h>
#include <common/runtime_svc.h>
#include <lib/bakery_lock.h>
#include <lib/mmio.h>
#include <ipi.h>
#include <plat_ipi.h>
#include <plat_private.h>
/* Zynqmp ipi configuration table */
const static struct ipi_config zynqmp_ipi_table[] = {
/* APU IPI */
{
.ipi_bit_mask = 0x1,
.ipi_reg_base = 0xFF300000U,
.secure_only = 0,
},
/* RPU0 IPI */
{
.ipi_bit_mask = 0x100,
.ipi_reg_base = 0xFF310000U,
.secure_only = 0,
},
/* RPU1 IPI */
{
.ipi_bit_mask = 0x200,
.ipi_reg_base = 0xFF320000U,
.secure_only = 0,
},
/* PMU0 IPI */
{
.ipi_bit_mask = 0x10000,
.ipi_reg_base = 0xFF330000U,
.secure_only = IPI_SECURE_MASK,
},
/* PMU1 IPI */
{
.ipi_bit_mask = 0x20000,
.ipi_reg_base = 0xFF331000U,
.secure_only = 0,
},
/* PMU2 IPI */
{
.ipi_bit_mask = 0x40000,
.ipi_reg_base = 0xFF332000U,
.secure_only = IPI_SECURE_MASK,
},
/* PMU3 IPI */
{
.ipi_bit_mask = 0x80000,
.ipi_reg_base = 0xFF333000U,
.secure_only = IPI_SECURE_MASK,
},
/* PL0 IPI */
{
.ipi_bit_mask = 0x1000000,
.ipi_reg_base = 0xFF340000U,
.secure_only = 0,
},
/* PL1 IPI */
{
.ipi_bit_mask = 0x2000000,
.ipi_reg_base = 0xFF350000U,
.secure_only = 0,
},
/* PL2 IPI */
{
.ipi_bit_mask = 0x4000000,
.ipi_reg_base = 0xFF360000U,
.secure_only = 0,
},
/* PL3 IPI */
{
.ipi_bit_mask = 0x8000000,
.ipi_reg_base = 0xFF370000U,
.secure_only = 0,
},
};
/**
* zynqmp_ipi_config_table_init() - Initialize ZynqMP IPI configuration data
*
*/
void zynqmp_ipi_config_table_init(void)
{
ipi_config_table_init(zynqmp_ipi_table, ARRAY_SIZE(zynqmp_ipi_table));
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/xilinx/zynqmp/zynqmp_sdei.c
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/*
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) Siemens AG, 2020-2021
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* SDEI configuration for ARM platforms */
#include <bl31/ehf.h>
#include <common/debug.h>
#include <services/sdei.h>
#include <plat/common/platform.h>
#include <platform_def.h>
int arm_validate_ns_entrypoint(uintptr_t entrypoint)
{
return (entrypoint < BL31_BASE || entrypoint > BL31_LIMIT) ? 0 : -1;
}
/* Private event mappings */
static sdei_ev_map_t zynqmp_sdei_private[] = {
SDEI_DEFINE_EVENT_0(ZYNQMP_SDEI_SGI_PRIVATE),
};
/* Shared event mappings */
static sdei_ev_map_t zynqmp_sdei_shared[] = {
};
void plat_sdei_setup(void)
{
INFO("SDEI platform setup\n");
}
/* Export ARM SDEI events */
REGISTER_SDEI_MAP(zynqmp_sdei_private, zynqmp_sdei_shared);