GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <string.h>
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#include <common/debug.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <plat_ipi.h>
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#include <plat_private.h>
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#include <plat/common/platform.h>
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#include "pm_api_sys.h"
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/*
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* Table of regions to map using the MMU.
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* This doesn't include TZRAM as the 'mem_layout' argument passed to
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* configure_mmu_elx() will give the available subset of that,
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*/
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const mmap_region_t plat_arm_mmap[] = {
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{ DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
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{ DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
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{ CRF_APB_BASE, CRF_APB_BASE, CRF_APB_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
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{0}
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};
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static uint32_t zynqmp_get_silicon_ver(void)
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{
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static unsigned int ver;
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if (!ver) {
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ver = mmio_read_32(ZYNQMP_CSU_BASEADDR +
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ZYNQMP_CSU_VERSION_OFFSET);
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ver &= ZYNQMP_SILICON_VER_MASK;
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ver >>= ZYNQMP_SILICON_VER_SHIFT;
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}
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return ver;
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}
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uint32_t zynqmp_get_uart_clk(void)
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{
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unsigned int ver = zynqmp_get_silicon_ver();
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if (ver == ZYNQMP_CSU_VERSION_QEMU) {
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return 133000000;
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} else {
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return 100000000;
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}
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}
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#if LOG_LEVEL >= LOG_LEVEL_NOTICE
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static const struct {
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uint32_t id;
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uint32_t ver;
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char *name;
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bool evexists;
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} zynqmp_devices[] = {
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{
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.id = 0x10,
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.name = "XCZU3EG",
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},
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{
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.id = 0x10,
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.ver = 0x2c,
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.name = "XCZU3CG",
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},
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{
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.id = 0x11,
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.name = "XCZU2EG",
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},
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{
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.id = 0x11,
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.ver = 0x2c,
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.name = "XCZU2CG",
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},
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{
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.id = 0x20,
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.name = "XCZU5EV",
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.evexists = true,
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},
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{
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.id = 0x20,
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.ver = 0x100,
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.name = "XCZU5EG",
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.evexists = true,
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},
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{
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.id = 0x20,
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.ver = 0x12c,
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.name = "XCZU5CG",
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},
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{
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.id = 0x21,
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.name = "XCZU4EV",
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.evexists = true,
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},
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{
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.id = 0x21,
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.ver = 0x100,
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.name = "XCZU4EG",
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.evexists = true,
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},
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{
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.id = 0x21,
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.ver = 0x12c,
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.name = "XCZU4CG",
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},
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{
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.id = 0x30,
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.name = "XCZU7EV",
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.evexists = true,
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},
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{
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.id = 0x30,
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.ver = 0x100,
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.name = "XCZU7EG",
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.evexists = true,
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},
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{
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.id = 0x30,
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.ver = 0x12c,
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.name = "XCZU7CG",
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},
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{
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.id = 0x38,
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.name = "XCZU9EG",
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},
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{
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.id = 0x38,
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.ver = 0x2c,
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.name = "XCZU9CG",
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},
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{
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.id = 0x39,
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.name = "XCZU6EG",
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},
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{
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.id = 0x39,
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.ver = 0x2c,
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.name = "XCZU6CG",
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},
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{
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.id = 0x40,
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.name = "XCZU11EG",
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},
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{
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.id = 0x50,
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.name = "XCZU15EG",
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},
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{
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.id = 0x58,
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.name = "XCZU19EG",
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},
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{
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.id = 0x59,
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.name = "XCZU17EG",
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},
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{
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.id = 0x60,
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.name = "XCZU28DR",
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},
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{
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.id = 0x61,
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.name = "XCZU21DR",
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},
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{
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.id = 0x62,
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.name = "XCZU29DR",
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},
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{
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.id = 0x63,
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.name = "XCZU23DR",
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},
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{
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.id = 0x64,
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.name = "XCZU27DR",
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},
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{
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.id = 0x65,
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.name = "XCZU25DR",
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},
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{
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.id = 0x66,
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.name = "XCZU39DR",
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},
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{
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.id = 0x7d,
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.name = "XCZU43DR",
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},
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{
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.id = 0x78,
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.name = "XCZU46DR",
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},
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{
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.id = 0x7f,
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.name = "XCZU47DR",
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},
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{
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.id = 0x7b,
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.name = "XCZU48DR",
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},
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{
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.id = 0x7e,
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.name = "XCZU49DR",
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},
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};
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#define ZYNQMP_PL_STATUS_BIT 9
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#define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
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#define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
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#define SILICON_ID_XCK24 0x4714093U
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#define SILICON_ID_XCK26 0x4724093U
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static char *zynqmp_get_silicon_idcode_name(void)
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{
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uint32_t id, ver, chipid[2];
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size_t i, j, len;
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const char *name = "EG/EV";
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#ifdef IMAGE_BL32
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/*
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* For BL32, get the chip id info directly by reading corresponding
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* registers instead of making pm call. This has limitation
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* that these registers should be configured to have access
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* from APU which is default case.
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*/
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chipid[0] = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
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chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET);
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#else
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if (pm_get_chipid(chipid) != PM_RET_SUCCESS) {
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return "XCZUUNKN";
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}
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#endif
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id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
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ZYNQMP_CSU_IDCODE_SVD_MASK);
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id >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
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ver = chipid[1] >> ZYNQMP_EFUSE_IPDISABLE_SHIFT;
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for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
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if (zynqmp_devices[i].id == id &&
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zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK)) {
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break;
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}
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}
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if (i >= ARRAY_SIZE(zynqmp_devices)) {
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switch (chipid[0]) {
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case SILICON_ID_XCK24:
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return "XCK24";
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case SILICON_ID_XCK26:
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return "XCK26";
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default:
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return "XCZUUNKN";
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}
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}
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if (!zynqmp_devices[i].evexists) {
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return zynqmp_devices[i].name;
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}
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if ((ver & ZYNQMP_PL_STATUS_MASK) != 0U) {
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return zynqmp_devices[i].name;
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}
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len = strlen(zynqmp_devices[i].name) - 2;
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for (j = 0; j < strlen(name); j++) {
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zynqmp_devices[i].name[len] = name[j];
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len++;
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}
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zynqmp_devices[i].name[len] = '\0';
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return zynqmp_devices[i].name;
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}
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static unsigned int zynqmp_get_rtl_ver(void)
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{
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uint32_t ver;
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ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET);
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ver &= ZYNQMP_RTL_VER_MASK;
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ver >>= ZYNQMP_RTL_VER_SHIFT;
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return ver;
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}
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static char *zynqmp_print_silicon_idcode(void)
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{
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uint32_t id, maskid, tmp;
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id = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
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tmp = id;
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tmp &= ZYNQMP_CSU_IDCODE_XILINX_ID_MASK |
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ZYNQMP_CSU_IDCODE_FAMILY_MASK;
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maskid = ZYNQMP_CSU_IDCODE_XILINX_ID << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT |
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ZYNQMP_CSU_IDCODE_FAMILY << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT;
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if (tmp != maskid) {
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ERROR("Incorrect XILINX IDCODE 0x%x, maskid 0x%x\n", id, maskid);
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return "UNKN";
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}
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VERBOSE("Xilinx IDCODE 0x%x\n", id);
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return zynqmp_get_silicon_idcode_name();
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}
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static uint32_t zynqmp_get_ps_ver(void)
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{
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uint32_t ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET);
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ver &= ZYNQMP_PS_VER_MASK;
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ver >>= ZYNQMP_PS_VER_SHIFT;
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return ver + 1U;
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}
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static void zynqmp_print_platform_name(void)
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{
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uint32_t ver = zynqmp_get_silicon_ver();
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uint32_t rtl = zynqmp_get_rtl_ver();
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char *label = "Unknown";
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switch (ver) {
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case ZYNQMP_CSU_VERSION_QEMU:
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label = "QEMU";
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break;
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case ZYNQMP_CSU_VERSION_SILICON:
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label = "silicon";
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break;
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default:
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/* Do nothing in default case */
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break;
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}
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VERBOSE("TF-A running on %s/%s at 0x%x\n",
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zynqmp_print_silicon_idcode(), label, BL31_BASE);
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VERBOSE("TF-A running on v%d/RTL%d.%d\n",
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zynqmp_get_ps_ver(), (rtl & 0xf0) >> 4, rtl & 0xf);
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}
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#else
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static inline void zynqmp_print_platform_name(void) { }
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#endif
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uint32_t zynqmp_get_bootmode(void)
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{
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uint32_t r;
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unsigned int ret;
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ret = pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r);
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if (ret != PM_RET_SUCCESS) {
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r = mmio_read_32(CRL_APB_BOOT_MODE_USER);
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}
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return r & CRL_APB_BOOT_MODE_MASK;
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}
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void zynqmp_config_setup(void)
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{
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uint64_t counter_freq;
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/* Configure IPI data for ZynqMP */
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zynqmp_ipi_config_table_init();
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zynqmp_print_platform_name();
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/* Configure counter frequency */
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counter_freq = read_cntfrq_el0();
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if (counter_freq == ZYNQMP_DEFAULT_COUNTER_FREQ) {
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write_cntfrq_el0(plat_get_syscnt_freq2());
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}
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generic_delay_timer_init();
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}
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uint32_t plat_get_syscnt_freq2(void)
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{
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uint32_t ver = zynqmp_get_silicon_ver();
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if (ver == ZYNQMP_CSU_VERSION_QEMU) {
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return 65000000;
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} else {
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return mmio_read_32(IOU_SCNTRS_BASEFREQ);
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}
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}
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+86
@@ -0,0 +1,86 @@
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/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <drivers/arm/gicv2.h>
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#include <platform_def.h>
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.globl plat_secondary_cold_boot_setup
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.globl plat_is_my_cpu_primary
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.globl zynqmp_calc_core_pos
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.globl plat_my_core_pos
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.globl platform_mem_init
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* TODO: Should we read the PSYS register to make sure
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* that the request has gone through.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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mrs x0, mpidr_el1
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/* Deactivate the gic cpu interface */
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ldr x1, =BASE_GICC_BASE
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mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
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orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
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str w0, [x1, #GICC_CTLR]
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/*
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* There is no sane reason to come out of this wfi. This
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* cpu will be powered on and reset by the cpu_on pm api
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*/
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dsb sy
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1:
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no_ret plat_panic_handler
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endfunc plat_secondary_cold_boot_setup
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func plat_is_my_cpu_primary
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mov x9, x30
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bl plat_my_core_pos
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cmp x0, #ZYNQMP_PRIMARY_CPU
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cset x0, eq
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ret x9
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This function uses the zynqmp_calc_core_pos()
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* definition to get the index of the calling CPU.
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b zynqmp_calc_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned int zynqmp_calc_core_pos(u_register_t mpidr)
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* Helper function to calculate the core position.
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* With this function: CorePos = (ClusterId * 4) +
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* CoreId
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* -----------------------------------------------------
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*/
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func zynqmp_calc_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc zynqmp_calc_core_pos
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/* ---------------------------------------------------------------------
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* We don't need to carry out any memory initialization on ARM
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* platforms. The Secure RAM is accessible straight away.
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* ---------------------------------------------------------------------
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*/
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func platform_mem_init
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ret
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endfunc platform_mem_init
|
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