GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* ZynqMP IPI management enums and defines */
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#ifndef PLAT_IPI_H
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#define PLAT_IPI_H
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#include <stdint.h>
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#include <ipi.h>
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/*********************************************************************
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* IPI agent IDs macros
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********************************************************************/
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#define IPI_ID_APU 0U
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#define IPI_ID_RPU0 1U
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#define IPI_ID_RPU1 2U
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#define IPI_ID_PMU0 3U
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#define IPI_ID_PMU1 4U
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#define IPI_ID_PMU2 5U
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#define IPI_ID_PMU3 6U
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#define IPI_ID_PL0 7U
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#define IPI_ID_PL1 8U
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#define IPI_ID_PL2 9U
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#define IPI_ID_PL3 10U
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/*********************************************************************
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* IPI message buffers
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********************************************************************/
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#define IPI_BUFFER_BASEADDR 0xFF990000U
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#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U)
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#define IPI_BUFFER_PMU_BASE (IPI_BUFFER_BASEADDR + 0xE00U)
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#define IPI_BUFFER_LOCAL_BASE IPI_BUFFER_APU_BASE
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#define IPI_BUFFER_REMOTE_BASE IPI_BUFFER_PMU_BASE
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#define IPI_BUFFER_TARGET_LOCAL_OFFSET 0x80U
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#define IPI_BUFFER_TARGET_REMOTE_OFFSET 0x1C0U
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#define IPI_BUFFER_MAX_WORDS 8U
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#define IPI_BUFFER_REQ_OFFSET 0x0U
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#define IPI_BUFFER_RESP_OFFSET 0x20U
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/*********************************************************************
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* Platform specific IPI API declarations
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********************************************************************/
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/* Configure IPI table for zynqmp */
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void zynqmp_ipi_config_table_init(void);
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#endif /* PLAT_IPI_H */
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+28
@@ -0,0 +1,28 @@
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/*
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* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_MACROS_S
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#define PLAT_MACROS_S
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#include <arm_macros.S>
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#include <cci_macros.S>
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#include "zynqmp_def.h"
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/* ---------------------------------------------
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* The below required platform porting macro
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* prints out relevant GIC and CCI registers
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* whenever an unhandled exception is taken in
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* BL31.
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* Clobbers: x0 - x10, x16, x17, sp
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* ---------------------------------------------
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*/
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.macro plat_crash_print_regs
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mov_imm x17, BASE_GICC_BASE
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mov_imm x16, BASE_GICD_BASE
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arm_print_gic_regs
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print_cci_regs
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.endm
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#endif /* PLAT_MACROS_S */
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+24
@@ -0,0 +1,24 @@
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/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Contains platform specific definitions of commonly used macros data types
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* for PU Power Management. This file should be common for all PU's.
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*/
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#ifndef PLAT_PM_COMMON_H
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#define PLAT_PM_COMMON_H
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#include <stdint.h>
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#include <common/debug.h>
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#include "pm_defs.h"
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#define ZYNQMP_TZ_VERSION_MAJOR 1
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#define ZYNQMP_TZ_VERSION_MINOR 0
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#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
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ZYNQMP_TZ_VERSION_MINOR)
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#endif /* _PLAT_PM_COMMON_H_ */
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+33
@@ -0,0 +1,33 @@
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/*
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* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_PRIVATE_H
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#define PLAT_PRIVATE_H
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#include <stdint.h>
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#include <bl31/interrupt_mgmt.h>
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#include <common/bl_common.h>
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#include <drivers/cadence/cdns_uart.h>
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void zynqmp_config_setup(void);
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uint32_t zynqmp_calc_core_pos(u_register_t mpidr);
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/* ZynqMP specific functions */
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uint32_t zynqmp_get_uart_clk(void);
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uint32_t zynqmp_get_bootmode(void);
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#if ZYNQMP_WDT_RESTART
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/*
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* Register handler to specific GIC entrance
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* for INTR_TYPE_EL3 type of interrupt
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*/
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int request_intr_type_el3(uint32_t, interrupt_type_handler_t);
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#endif
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#endif /* PLAT_PRIVATE_H */
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+161
@@ -0,0 +1,161 @@
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/*
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* Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <common/interrupt_props.h>
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#include <drivers/arm/gic_common.h>
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#include <lib/utils_def.h>
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#include "zynqmp_def.h"
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#define PLATFORM_STACK_SIZE 0x440
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#define PLATFORM_CORE_COUNT U(4)
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#define PLAT_NUM_POWER_DOMAINS U(5)
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#define PLAT_MAX_PWR_LVL U(1)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
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* present). BL31_BASE is calculated using the current BL31 debug size plus a
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* little space for growth.
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*/
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#ifndef ZYNQMP_ATF_MEM_BASE
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#if !DEBUG && defined(SPD_none) && !SDEI_SUPPORT
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# define BL31_BASE U(0xfffea000)
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# define BL31_LIMIT U(0x100000000)
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#else
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# define BL31_BASE U(0xfffe5000)
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# define BL31_LIMIT U(0x100000000)
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#endif
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#else
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# define BL31_BASE (ZYNQMP_ATF_MEM_BASE)
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# define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1)
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# ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE
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# define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1)
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# endif
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#endif
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/*******************************************************************************
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* BL32 specific defines.
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******************************************************************************/
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#ifndef ZYNQMP_BL32_MEM_BASE
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# define BL32_BASE U(0x60000000)
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# define BL32_LIMIT U(0x7fffffff)
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#else
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# define BL32_BASE (ZYNQMP_BL32_MEM_BASE)
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# define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1)
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#endif
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/*******************************************************************************
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* BL33 specific defines.
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******************************************************************************/
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#ifndef PRELOADED_BL33_BASE
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# define PLAT_ARM_NS_IMAGE_BASE U(0x8000000)
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#else
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# define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE
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#endif
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/*******************************************************************************
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* TSP specific defines.
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******************************************************************************/
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#define TSP_SEC_MEM_BASE BL32_BASE
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#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
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/* ID of the secure physical generic timer interrupt used by the TSP */
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#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define XILINX_OF_BOARD_DTB_ADDR U(0x100000)
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#define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000)
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#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
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#define MAX_MMAP_REGIONS 8
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#define MAX_XLAT_TABLES 6
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#else
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#define MAX_MMAP_REGIONS 7
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#define MAX_XLAT_TABLES 5
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#endif
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#define ZYNQMP_SDEI_SGI_PRIVATE U(8)
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/* Platform macros to support exception handling framework */
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#define PLAT_PRI_BITS U(3)
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#define PLAT_SDEI_CRITICAL_PRI 0x10
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#define PLAT_SDEI_NORMAL_PRI 0x20
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#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
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/*
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* Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#if !ZYNQMP_WDT_RESTART
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE)
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#else
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE)
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#endif
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#define PLAT_ARM_G0_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \
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GIC_INTR_CFG_EDGE)
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#endif /* PLATFORM_DEF_H */
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+365
@@ -0,0 +1,365 @@
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/*
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* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ZYNQMP_DEF_H
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#define ZYNQMP_DEF_H
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#include <plat/arm/common/smccc_def.h>
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#include <plat/common/common_def.h>
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#define ZYNQMP_CONSOLE_ID_cadence 1
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#define ZYNQMP_CONSOLE_ID_cadence0 1
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#define ZYNQMP_CONSOLE_ID_cadence1 2
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#define ZYNQMP_CONSOLE_ID_dcc 3
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#define ZYNQMP_CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE)
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/* Default counter frequency */
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#define ZYNQMP_DEFAULT_COUNTER_FREQ 0U
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/* Firmware Image Package */
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#define ZYNQMP_PRIMARY_CPU 0
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/* Memory location options for Shared data and TSP in ZYNQMP */
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#define ZYNQMP_IN_TRUSTED_SRAM 0
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#define ZYNQMP_IN_TRUSTED_DRAM 1
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/*******************************************************************************
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* ZYNQMP memory map related constants
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******************************************************************************/
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/* Aggregate of all devices in the first GB */
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#define DEVICE0_BASE U(0xFF000000)
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#define DEVICE0_SIZE U(0x00E00000)
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#define DEVICE1_BASE U(0xF9000000)
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#define DEVICE1_SIZE U(0x00800000)
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/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
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#define CRF_APB_BASE U(0xFD1A0000)
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#define CRF_APB_SIZE U(0x00600000)
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#define CRF_APB_CLK_BASE U(0xFD1A0020)
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/* CRF registers and bitfields */
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#define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104)
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#define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0)
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#define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10)
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/* CRL registers and bitfields */
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#define CRL_APB_BASE U(0xFF5E0000)
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#define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200)
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#define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218)
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#define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C)
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#define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250))
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#define CRL_APB_CLK_BASE U(0xFF5E0020)
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#define CRL_APB_RPU_AMBA_RESET (U(1) << 2)
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#define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3)
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#define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4)
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#define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0)
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#define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0)
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#define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9)
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#define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1)
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#define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << \
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CRL_APB_BOOT_ENABLE_PIN_1_SHIFT)
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#define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << \
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CRL_APB_BOOT_DRIVE_PIN_1_SHIFT)
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#define ZYNQMP_BOOTMODE_JTAG U(0)
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#define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | \
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CRL_APB_BOOT_DRIVE_PIN_1)
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#define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1
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/* system counter registers and bitfields */
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#define IOU_SCNTRS_BASE U(0xFF260000)
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#define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20)
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/* APU registers and bitfields */
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#define APU_BASE U(0xFD5C0000)
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#define APU_CONFIG_0 (APU_BASE + 0x20)
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#define APU_RVBAR_L_0 (APU_BASE + 0x40)
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#define APU_RVBAR_H_0 (APU_BASE + 0x44)
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#define APU_PWRCTL (APU_BASE + 0x90)
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#define APU_CONFIG_0_VINITHI_SHIFT 8
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#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1
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#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2
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#define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4
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#define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8
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/* PMU registers and bitfields */
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||||
#define PMU_GLOBAL_BASE U(0xFFD80000)
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#define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0)
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#define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48)
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||||
#define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110)
|
||||
#define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118)
|
||||
#define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c)
|
||||
#define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120)
|
||||
|
||||
#define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4)
|
||||
|
||||
/*******************************************************************************
|
||||
* CCI-400 related constants
|
||||
******************************************************************************/
|
||||
#define PLAT_ARM_CCI_BASE U(0xFD6E0000)
|
||||
#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3
|
||||
#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4
|
||||
|
||||
/*******************************************************************************
|
||||
* GIC-400 & interrupt handling related constants
|
||||
******************************************************************************/
|
||||
#define BASE_GICD_BASE U(0xF9010000)
|
||||
#define BASE_GICC_BASE U(0xF9020000)
|
||||
#define BASE_GICH_BASE U(0xF9040000)
|
||||
#define BASE_GICV_BASE U(0xF9060000)
|
||||
|
||||
#if ZYNQMP_WDT_RESTART
|
||||
#define IRQ_SEC_IPI_APU 67
|
||||
#define IRQ_TTC3_1 77
|
||||
#define TTC3_BASE_ADDR U(0xFF140000)
|
||||
#define TTC3_INTR_REGISTER_1 (TTC3_BASE_ADDR + 0x54)
|
||||
#define TTC3_INTR_ENABLE_1 (TTC3_BASE_ADDR + 0x60)
|
||||
#endif
|
||||
|
||||
#define ARM_IRQ_SEC_PHY_TIMER 29
|
||||
|
||||
#define ARM_IRQ_SEC_SGI_0 8
|
||||
#define ARM_IRQ_SEC_SGI_1 9
|
||||
#define ARM_IRQ_SEC_SGI_2 10
|
||||
#define ARM_IRQ_SEC_SGI_3 11
|
||||
#define ARM_IRQ_SEC_SGI_4 12
|
||||
#define ARM_IRQ_SEC_SGI_5 13
|
||||
#define ARM_IRQ_SEC_SGI_6 14
|
||||
#define ARM_IRQ_SEC_SGI_7 15
|
||||
|
||||
#define MAX_INTR_EL3 128
|
||||
|
||||
/*******************************************************************************
|
||||
* UART related constants
|
||||
******************************************************************************/
|
||||
#define ZYNQMP_UART0_BASE U(0xFF000000)
|
||||
#define ZYNQMP_UART1_BASE U(0xFF010000)
|
||||
|
||||
#if ZYNQMP_CONSOLE_IS(cadence) || ZYNQMP_CONSOLE_IS(dcc)
|
||||
# define ZYNQMP_UART_BASE ZYNQMP_UART0_BASE
|
||||
#elif ZYNQMP_CONSOLE_IS(cadence1)
|
||||
# define ZYNQMP_UART_BASE ZYNQMP_UART1_BASE
|
||||
#else
|
||||
# error "invalid ZYNQMP_CONSOLE"
|
||||
#endif
|
||||
|
||||
#define ZYNQMP_CRASH_UART_BASE ZYNQMP_UART_BASE
|
||||
/* impossible to call C routine how it is done now - hardcode any value */
|
||||
#define ZYNQMP_CRASH_UART_CLK_IN_HZ 100000000 /* FIXME */
|
||||
/* Must be non zero */
|
||||
#define ZYNQMP_UART_BAUDRATE 115200
|
||||
|
||||
/* Silicon version detection */
|
||||
#define ZYNQMP_SILICON_VER_MASK 0xF000
|
||||
#define ZYNQMP_SILICON_VER_SHIFT 12
|
||||
#define ZYNQMP_CSU_VERSION_SILICON 0
|
||||
#define ZYNQMP_CSU_VERSION_QEMU 3
|
||||
|
||||
#define ZYNQMP_RTL_VER_MASK 0xFF0U
|
||||
#define ZYNQMP_RTL_VER_SHIFT 4
|
||||
|
||||
#define ZYNQMP_PS_VER_MASK 0xFU
|
||||
#define ZYNQMP_PS_VER_SHIFT 0
|
||||
|
||||
#define ZYNQMP_CSU_BASEADDR U(0xFFCA0000)
|
||||
#define ZYNQMP_CSU_IDCODE_OFFSET 0x40U
|
||||
|
||||
#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0U
|
||||
#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFFU << \
|
||||
ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT)
|
||||
#define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093
|
||||
|
||||
#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12U
|
||||
#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7U << \
|
||||
ZYNQMP_CSU_IDCODE_SVD_SHIFT)
|
||||
#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15U
|
||||
#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xFU << \
|
||||
ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
|
||||
#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19U
|
||||
#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3U << \
|
||||
ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT)
|
||||
#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21U
|
||||
#define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7FU << \
|
||||
ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
|
||||
#define ZYNQMP_CSU_IDCODE_FAMILY 0x23
|
||||
|
||||
#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28U
|
||||
#define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xFU << \
|
||||
ZYNQMP_CSU_IDCODE_REVISION_SHIFT)
|
||||
#define ZYNQMP_CSU_IDCODE_REVISION 0U
|
||||
|
||||
#define ZYNQMP_CSU_VERSION_OFFSET 0x44U
|
||||
|
||||
/* Efuse */
|
||||
#define EFUSE_BASEADDR U(0xFFCC0000)
|
||||
#define EFUSE_IPDISABLE_OFFSET 0x1018
|
||||
#define EFUSE_IPDISABLE_VERSION 0x1FFU
|
||||
#define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20
|
||||
|
||||
/* Access control register defines */
|
||||
#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
|
||||
#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
|
||||
|
||||
#define FPD_SLCR_BASEADDR U(0xFD610000)
|
||||
#define IOU_SLCR_BASEADDR U(0xFF180000)
|
||||
|
||||
#define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000)
|
||||
#define ZYNQMP_RPU0_CFG U(0xFF9A0100)
|
||||
#define ZYNQMP_RPU1_CFG U(0xFF9A0200)
|
||||
#define ZYNQMP_SLSPLIT_MASK U(0x08)
|
||||
#define ZYNQMP_TCM_COMB_MASK U(0x40)
|
||||
#define ZYNQMP_SLCLAMP_MASK U(0x10)
|
||||
#define ZYNQMP_VINITHI_MASK U(0x04)
|
||||
|
||||
/* Tap delay bypass */
|
||||
#define IOU_TAPDLY_BYPASS U(0XFF180390)
|
||||
#define TAP_DELAY_MASK U(0x7)
|
||||
|
||||
/* SGMII mode */
|
||||
#define IOU_GEM_CTRL U(0xFF180360)
|
||||
#define IOU_GEM_CLK_CTRL U(0xFF180308)
|
||||
#define SGMII_SD_MASK U(0x3)
|
||||
#define SGMII_SD_OFFSET U(2)
|
||||
#define SGMII_PCS_SD_0 U(0x0)
|
||||
#define SGMII_PCS_SD_1 U(0x1)
|
||||
#define SGMII_PCS_SD_PHY U(0x2)
|
||||
#define GEM_SGMII_MASK U(0x4)
|
||||
#define GEM_CLK_CTRL_MASK U(0xF)
|
||||
#define GEM_CLK_CTRL_OFFSET U(5)
|
||||
#define GEM_RX_SRC_SEL_GTR U(0x1)
|
||||
#define GEM_SGMII_MODE U(0x4)
|
||||
|
||||
/* SD DLL reset */
|
||||
#define ZYNQMP_SD_DLL_CTRL U(0xFF180358)
|
||||
#define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004)
|
||||
#define ZYNQMP_SD0_DLL_RST U(0x00000004)
|
||||
#define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000)
|
||||
#define ZYNQMP_SD1_DLL_RST U(0x00040000)
|
||||
|
||||
/* SD tap delay */
|
||||
#define ZYNQMP_SD_DLL_CTRL U(0xFF180358)
|
||||
#define ZYNQMP_SD_ITAP_DLY U(0xFF180314)
|
||||
#define ZYNQMP_SD_OTAP_DLY U(0xFF180318)
|
||||
#define ZYNQMP_SD_TAP_OFFSET U(16)
|
||||
#define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200)
|
||||
#define ZYNQMP_SD_ITAPCHGWIN U(0x200)
|
||||
#define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100)
|
||||
#define ZYNQMP_SD_ITAPDLYENA U(0x100)
|
||||
#define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF)
|
||||
#define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F)
|
||||
#define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40)
|
||||
#define ZYNQMP_SD_OTAPDLYENA U(0x40)
|
||||
|
||||
/* Clock control registers */
|
||||
/* Full power domain clocks */
|
||||
#define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00)
|
||||
#define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c)
|
||||
#define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18)
|
||||
#define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24)
|
||||
#define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28)
|
||||
#define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c)
|
||||
#define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30)
|
||||
/* Peripheral clocks */
|
||||
#define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40)
|
||||
#define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44)
|
||||
#define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48)
|
||||
#define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50)
|
||||
#define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54)
|
||||
#define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c)
|
||||
#define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60)
|
||||
#define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64)
|
||||
#define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80)
|
||||
#define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94)
|
||||
#define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98)
|
||||
#define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c)
|
||||
#define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0)
|
||||
#define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4)
|
||||
#define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8)
|
||||
#define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8)
|
||||
|
||||
/* Low power domain clocks */
|
||||
#define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00)
|
||||
#define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10)
|
||||
#define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20)
|
||||
#define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24)
|
||||
#define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28)
|
||||
/* Peripheral clocks */
|
||||
#define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c)
|
||||
#define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30)
|
||||
#define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34)
|
||||
#define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38)
|
||||
#define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c)
|
||||
#define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40)
|
||||
#define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44)
|
||||
#define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48)
|
||||
#define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c)
|
||||
#define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50)
|
||||
#define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54)
|
||||
#define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58)
|
||||
#define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c)
|
||||
#define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60)
|
||||
#define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64)
|
||||
#define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68)
|
||||
#define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70)
|
||||
#define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c)
|
||||
#define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80)
|
||||
#define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84)
|
||||
#define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88)
|
||||
#define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c)
|
||||
#define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90)
|
||||
#define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94)
|
||||
#define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98)
|
||||
#define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0)
|
||||
#define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4)
|
||||
#define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8)
|
||||
#define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac)
|
||||
#define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4)
|
||||
#define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc)
|
||||
#define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4)
|
||||
#define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc)
|
||||
#define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0)
|
||||
#define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4)
|
||||
#define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8)
|
||||
#define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100)
|
||||
#define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104)
|
||||
#define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108)
|
||||
#define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308)
|
||||
#define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304)
|
||||
#define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100)
|
||||
#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300)
|
||||
|
||||
/* Global general storage register base address */
|
||||
#define GGS_BASEADDR (0xFFD80030U)
|
||||
#define GGS_NUM_REGS U(4)
|
||||
|
||||
/* Persistent global general storage register base address */
|
||||
#define PGGS_BASEADDR (0xFFD80050U)
|
||||
#define PGGS_NUM_REGS U(4)
|
||||
|
||||
/* PMU GGS4 register 4 is used for warm restart boot health status */
|
||||
#define PMU_GLOBAL_GEN_STORAGE4 (GGS_BASEADDR + 0x10)
|
||||
/* Warm restart boot health status mask */
|
||||
#define PM_BOOT_HEALTH_STATUS_MASK U(0x01)
|
||||
/* WDT restart scope shift and mask */
|
||||
#define RESTART_SCOPE_SHIFT (3)
|
||||
#define RESTART_SCOPE_MASK (0x3U << RESTART_SCOPE_SHIFT)
|
||||
|
||||
/* AFI registers */
|
||||
#define AFIFM6_WRCTRL U(13)
|
||||
#define FABRIC_WIDTH U(3)
|
||||
|
||||
/* CSUDMA Module Base Address*/
|
||||
#define CSUDMA_BASE U(0xFFC80000)
|
||||
|
||||
/* RSA-CORE Module Base Address*/
|
||||
#define RSA_CORE_BASE U(0xFFCE0000)
|
||||
|
||||
#endif /* ZYNQMP_DEF_H */
|
||||
Reference in New Issue
Block a user