GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*******************************************************************************
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* This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a
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* plug-in component to the Secure Monitor, registered as a runtime service. The
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* SPD is expected to be a functional extension of the Secure Payload (SP) that
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* executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting
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* the Trusted OS/Applications range to the dispatcher. The SPD will either
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* handle the request locally or delegate it to the Secure Payload. It is also
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* responsible for initialising and maintaining communication with the SP.
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******************************************************************************/
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#include <assert.h>
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#include <errno.h>
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#include <stddef.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <bl31/bl31.h>
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#include <bl31/ehf.h>
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#include <bl32/tsp/tsp.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <plat/common/platform.h>
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#include <tools_share/uuid.h>
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#include "tspd_private.h"
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/*******************************************************************************
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* Address of the entrypoint vector table in the Secure Payload. It is
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* initialised once on the primary core after a cold boot.
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******************************************************************************/
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tsp_vectors_t *tsp_vectors;
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/*******************************************************************************
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* Array to keep track of per-cpu Secure Payload state
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******************************************************************************/
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tsp_context_t tspd_sp_context[TSPD_CORE_COUNT];
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/* TSP UID */
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DEFINE_SVC_UUID2(tsp_uuid,
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0xa056305b, 0x9132, 0x7b42, 0x98, 0x11,
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0x71, 0x68, 0xca, 0x50, 0xf3, 0xfa);
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int32_t tspd_init(void);
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/*
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* This helper function handles Secure EL1 preemption. The preemption could be
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* due Non Secure interrupts or EL3 interrupts. In both the cases we context
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* switch to the normal world and in case of EL3 interrupts, it will again be
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* routed to EL3 which will get handled at the exception vectors.
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*/
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uint64_t tspd_handle_sp_preemption(void *handle)
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{
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cpu_context_t *ns_cpu_context;
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assert(handle == cm_get_context(SECURE));
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cm_el1_sysregs_context_save(SECURE);
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/* Get a reference to the non-secure context */
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ns_cpu_context = cm_get_context(NON_SECURE);
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assert(ns_cpu_context);
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/*
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* To allow Secure EL1 interrupt handler to re-enter TSP while TSP
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* is preempted, the secure system register context which will get
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* overwritten must be additionally saved. This is currently done
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* by the TSPD S-EL1 interrupt handler.
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*/
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/*
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* Restore non-secure state.
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*/
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cm_el1_sysregs_context_restore(NON_SECURE);
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cm_set_next_eret_context(NON_SECURE);
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/*
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* The TSP was preempted during execution of a Yielding SMC Call.
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* Return back to the normal world with SMC_PREEMPTED as error
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* code in x0.
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*/
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SMC_RET1(ns_cpu_context, SMC_PREEMPTED);
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}
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/*******************************************************************************
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* This function is the handler registered for S-EL1 interrupts by the TSPD. It
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* validates the interrupt and upon success arranges entry into the TSP at
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* 'tsp_sel1_intr_entry()' for handling the interrupt.
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* Typically, interrupts for a specific security state get handled in the same
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* security execption level if the execution is in the same security state. For
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* example, if a non-secure interrupt gets fired when CPU is executing in NS-EL2
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* it gets handled in the non-secure world.
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* However, interrupts belonging to the opposite security state typically demand
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* a world(context) switch. This is inline with the security principle which
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* states a secure interrupt has to be handled in the secure world.
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* Hence, the TSPD in EL3 expects the context(handle) for a secure interrupt to
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* be non-secure and vice versa.
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* However, a race condition between non-secure and secure interrupts can lead to
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* a scenario where the above assumptions do not hold true. This is demonstrated
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* below through Note 1.
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******************************************************************************/
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static uint64_t tspd_sel1_interrupt_handler(uint32_t id,
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uint32_t flags,
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void *handle,
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void *cookie)
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{
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uint32_t linear_id;
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tsp_context_t *tsp_ctx;
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/* Get a reference to this cpu's TSP context */
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linear_id = plat_my_core_pos();
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tsp_ctx = &tspd_sp_context[linear_id];
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#if TSP_NS_INTR_ASYNC_PREEMPT
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/*
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* Note 1:
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* Under the current interrupt routing model, interrupts from other
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* world are routed to EL3 when TSP_NS_INTR_ASYNC_PREEMPT is enabled.
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* Consider the following scenario:
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* 1/ A non-secure payload(like tftf) requests a secure service from
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* TSP by invoking a yielding SMC call.
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* 2/ Later, execution jumps to TSP in S-EL1 with the help of TSP
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* Dispatcher in Secure Monitor(EL3).
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* 3/ While CPU is executing TSP, a Non-secure interrupt gets fired.
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* this demands a context switch to the non-secure world through
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* secure monitor.
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* 4/ Consequently, TSP in S-EL1 get asynchronously pre-empted and
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* execution switches to secure monitor(EL3).
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* 5/ EL3 tries to triage the (Non-secure) interrupt based on the
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* highest pending interrupt.
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* 6/ However, while the NS Interrupt was pending, secure timer gets
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* fired which makes a S-EL1 interrupt to be pending.
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* 7/ Hence, execution jumps to this companion handler of S-EL1
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* interrupt (i.e., tspd_sel1_interrupt_handler) even though the TSP
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* was pre-empted due to non-secure interrupt.
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* 8/ The above sequence of events explain how TSP was pre-empted by
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* S-EL1 interrupt indirectly in an asynchronous way.
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* 9/ Hence, we track the TSP pre-emption by S-EL1 interrupt using a
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* boolean variable per each core.
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* 10/ This helps us to indicate that SMC call for TSP service was
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* pre-empted when execution resumes in non-secure world.
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*/
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/* Check the security state when the exception was generated */
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if (get_interrupt_src_ss(flags) == NON_SECURE) {
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/* Sanity check the pointer to this cpu's context */
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assert(handle == cm_get_context(NON_SECURE));
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/* Save the non-secure context before entering the TSP */
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cm_el1_sysregs_context_save(NON_SECURE);
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tsp_ctx->preempted_by_sel1_intr = false;
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} else {
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/* Sanity check the pointer to this cpu's context */
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assert(handle == cm_get_context(SECURE));
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/* Save the secure context before entering the TSP for S-EL1
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* interrupt handling
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*/
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cm_el1_sysregs_context_save(SECURE);
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tsp_ctx->preempted_by_sel1_intr = true;
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}
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#else
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/* Check the security state when the exception was generated */
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assert(get_interrupt_src_ss(flags) == NON_SECURE);
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/* Sanity check the pointer to this cpu's context */
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assert(handle == cm_get_context(NON_SECURE));
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/* Save the non-secure context before entering the TSP */
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cm_el1_sysregs_context_save(NON_SECURE);
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#endif
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assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE));
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/*
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* Determine if the TSP was previously preempted. Its last known
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* context has to be preserved in this case.
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* The TSP should return control to the TSPD after handling this
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* S-EL1 interrupt. Preserve essential EL3 context to allow entry into
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* the TSP at the S-EL1 interrupt entry point using the 'cpu_context'
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* structure. There is no need to save the secure system register
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* context since the TSP is supposed to preserve it during S-EL1
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* interrupt handling.
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*/
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if (get_yield_smc_active_flag(tsp_ctx->state)) {
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tsp_ctx->saved_spsr_el3 = (uint32_t)SMC_GET_EL3(&tsp_ctx->cpu_ctx,
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CTX_SPSR_EL3);
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tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx,
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CTX_ELR_EL3);
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#if TSP_NS_INTR_ASYNC_PREEMPT
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memcpy(&tsp_ctx->sp_ctx, &tsp_ctx->cpu_ctx, TSPD_SP_CTX_SIZE);
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#endif
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}
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cm_el1_sysregs_context_restore(SECURE);
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cm_set_elr_spsr_el3(SECURE, (uint64_t) &tsp_vectors->sel1_intr_entry,
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SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS));
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cm_set_next_eret_context(SECURE);
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/*
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* Tell the TSP that it has to handle a S-EL1 interrupt synchronously.
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* Also the instruction in normal world where the interrupt was
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* generated is passed for debugging purposes. It is safe to retrieve
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* this address from ELR_EL3 as the secure context will not take effect
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* until el3_exit().
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*/
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SMC_RET2(&tsp_ctx->cpu_ctx, TSP_HANDLE_SEL1_INTR_AND_RETURN, read_elr_el3());
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}
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#if TSP_NS_INTR_ASYNC_PREEMPT
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/*******************************************************************************
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* This function is the handler registered for Non secure interrupts by the
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* TSPD. It validates the interrupt and upon success arranges entry into the
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* normal world for handling the interrupt.
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******************************************************************************/
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static uint64_t tspd_ns_interrupt_handler(uint32_t id,
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uint32_t flags,
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void *handle,
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void *cookie)
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{
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/* Check the security state when the exception was generated */
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assert(get_interrupt_src_ss(flags) == SECURE);
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/*
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* Disable the routing of NS interrupts from secure world to EL3 while
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* interrupted on this core.
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*/
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disable_intr_rm_local(INTR_TYPE_NS, SECURE);
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return tspd_handle_sp_preemption(handle);
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}
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#endif
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/*******************************************************************************
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* Secure Payload Dispatcher setup. The SPD finds out the SP entrypoint and type
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* (aarch32/aarch64) if not already known and initialises the context for entry
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* into the SP for its initialisation.
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******************************************************************************/
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static int32_t tspd_setup(void)
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{
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entry_point_info_t *tsp_ep_info;
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uint32_t linear_id;
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linear_id = plat_my_core_pos();
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/*
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* Get information about the Secure Payload (BL32) image. Its
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* absence is a critical failure. TODO: Add support to
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* conditionally include the SPD service
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*/
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tsp_ep_info = bl31_plat_get_next_image_ep_info(SECURE);
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if (!tsp_ep_info) {
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WARN("No TSP provided by BL2 boot loader, Booting device"
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" without TSP initialization. SMC`s destined for TSP"
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" will return SMC_UNK\n");
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return 1;
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}
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/*
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* If there's no valid entry point for SP, we return a non-zero value
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* signalling failure initializing the service. We bail out without
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* registering any handlers
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*/
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if (!tsp_ep_info->pc)
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return 1;
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/*
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* We could inspect the SP image and determine its execution
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* state i.e whether AArch32 or AArch64. Assuming it's AArch64
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* for the time being.
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*/
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tspd_init_tsp_ep_state(tsp_ep_info,
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TSP_AARCH64,
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tsp_ep_info->pc,
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&tspd_sp_context[linear_id]);
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#if TSP_INIT_ASYNC
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bl31_set_next_image_type(SECURE);
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#else
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/*
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* All TSPD initialization done. Now register our init function with
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* BL31 for deferred invocation
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*/
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bl31_register_bl32_init(&tspd_init);
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#endif
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return 0;
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}
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/*******************************************************************************
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* This function passes control to the Secure Payload image (BL32) for the first
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* time on the primary cpu after a cold boot. It assumes that a valid secure
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* context has already been created by tspd_setup() which can be directly used.
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* It also assumes that a valid non-secure context has been initialised by PSCI
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* so it does not need to save and restore any non-secure state. This function
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* performs a synchronous entry into the Secure payload. The SP passes control
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* back to this routine through a SMC.
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******************************************************************************/
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int32_t tspd_init(void)
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{
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uint32_t linear_id = plat_my_core_pos();
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tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
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entry_point_info_t *tsp_entry_point;
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uint64_t rc;
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/*
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* Get information about the Secure Payload (BL32) image. Its
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* absence is a critical failure.
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*/
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tsp_entry_point = bl31_plat_get_next_image_ep_info(SECURE);
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assert(tsp_entry_point);
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cm_init_my_context(tsp_entry_point);
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/*
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* Arrange for an entry into the test secure payload. It will be
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* returned via TSP_ENTRY_DONE case
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*/
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rc = tspd_synchronous_sp_entry(tsp_ctx);
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assert(rc != 0);
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return rc;
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}
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/*******************************************************************************
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* This function is responsible for handling all SMCs in the Trusted OS/App
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* range from the non-secure state as defined in the SMC Calling Convention
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* Document. It is also responsible for communicating with the Secure payload
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* to delegate work and return results back to the non-secure state. Lastly it
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* will also return any information that the secure payload needs to do the
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* work assigned to it.
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******************************************************************************/
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static uintptr_t tspd_smc_handler(uint32_t smc_fid,
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u_register_t x1,
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u_register_t x2,
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u_register_t x3,
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u_register_t x4,
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void *cookie,
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void *handle,
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u_register_t flags)
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{
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cpu_context_t *ns_cpu_context;
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uint32_t linear_id = plat_my_core_pos(), ns;
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tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
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uint64_t rc;
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#if TSP_INIT_ASYNC
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entry_point_info_t *next_image_info;
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#endif
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/* Determine which security state this SMC originated from */
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ns = is_caller_non_secure(flags);
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switch (smc_fid) {
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/*
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* This function ID is used by TSP to indicate that it was
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* preempted by a normal world IRQ.
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*
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*/
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case TSP_PREEMPTED:
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if (ns)
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SMC_RET1(handle, SMC_UNK);
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return tspd_handle_sp_preemption(handle);
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/*
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* This function ID is used only by the TSP to indicate that it has
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* finished handling a S-EL1 interrupt or was preempted by a higher
|
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* priority pending EL3 interrupt. Execution should resume
|
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* in the normal world.
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*/
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case TSP_HANDLED_S_EL1_INTR:
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if (ns)
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SMC_RET1(handle, SMC_UNK);
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assert(handle == cm_get_context(SECURE));
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/*
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* Restore the relevant EL3 state which saved to service
|
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* this SMC.
|
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*/
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if (get_yield_smc_active_flag(tsp_ctx->state)) {
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SMC_SET_EL3(&tsp_ctx->cpu_ctx,
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CTX_SPSR_EL3,
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tsp_ctx->saved_spsr_el3);
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SMC_SET_EL3(&tsp_ctx->cpu_ctx,
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CTX_ELR_EL3,
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tsp_ctx->saved_elr_el3);
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#if TSP_NS_INTR_ASYNC_PREEMPT
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/*
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* Need to restore the previously interrupted
|
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* secure context.
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*/
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memcpy(&tsp_ctx->cpu_ctx, &tsp_ctx->sp_ctx,
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TSPD_SP_CTX_SIZE);
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#endif
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}
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/* Get a reference to the non-secure context */
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ns_cpu_context = cm_get_context(NON_SECURE);
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assert(ns_cpu_context);
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/*
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* Restore non-secure state. There is no need to save the
|
||||
* secure system register context since the TSP was supposed
|
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* to preserve it during S-EL1 interrupt handling.
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*/
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cm_el1_sysregs_context_restore(NON_SECURE);
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cm_set_next_eret_context(NON_SECURE);
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/* Refer to Note 1 in function tspd_sel1_interrupt_handler()*/
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#if TSP_NS_INTR_ASYNC_PREEMPT
|
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if (tsp_ctx->preempted_by_sel1_intr) {
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/* Reset the flag */
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tsp_ctx->preempted_by_sel1_intr = false;
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SMC_RET1(ns_cpu_context, SMC_PREEMPTED);
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} else {
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SMC_RET0((uint64_t) ns_cpu_context);
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}
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#else
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SMC_RET0((uint64_t) ns_cpu_context);
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#endif
|
||||
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||||
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||||
/*
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||||
* This function ID is used only by the SP to indicate it has
|
||||
* finished initialising itself after a cold boot
|
||||
*/
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||||
case TSP_ENTRY_DONE:
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if (ns)
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SMC_RET1(handle, SMC_UNK);
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||||
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||||
/*
|
||||
* Stash the SP entry points information. This is done
|
||||
* only once on the primary cpu
|
||||
*/
|
||||
assert(tsp_vectors == NULL);
|
||||
tsp_vectors = (tsp_vectors_t *) x1;
|
||||
|
||||
if (tsp_vectors) {
|
||||
set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON);
|
||||
|
||||
/*
|
||||
* TSP has been successfully initialized. Register power
|
||||
* management hooks with PSCI
|
||||
*/
|
||||
psci_register_spd_pm_hook(&tspd_pm);
|
||||
|
||||
/*
|
||||
* Register an interrupt handler for S-EL1 interrupts
|
||||
* when generated during code executing in the
|
||||
* non-secure state.
|
||||
*/
|
||||
flags = 0;
|
||||
set_interrupt_rm_flag(flags, NON_SECURE);
|
||||
rc = register_interrupt_type_handler(INTR_TYPE_S_EL1,
|
||||
tspd_sel1_interrupt_handler,
|
||||
flags);
|
||||
if (rc)
|
||||
panic();
|
||||
|
||||
#if TSP_NS_INTR_ASYNC_PREEMPT
|
||||
/*
|
||||
* Register an interrupt handler for NS interrupts when
|
||||
* generated during code executing in secure state are
|
||||
* routed to EL3.
|
||||
*/
|
||||
flags = 0;
|
||||
set_interrupt_rm_flag(flags, SECURE);
|
||||
|
||||
rc = register_interrupt_type_handler(INTR_TYPE_NS,
|
||||
tspd_ns_interrupt_handler,
|
||||
flags);
|
||||
if (rc)
|
||||
panic();
|
||||
|
||||
/*
|
||||
* Disable the NS interrupt locally.
|
||||
*/
|
||||
disable_intr_rm_local(INTR_TYPE_NS, SECURE);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#if TSP_INIT_ASYNC
|
||||
/* Save the Secure EL1 system register context */
|
||||
assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx);
|
||||
cm_el1_sysregs_context_save(SECURE);
|
||||
|
||||
/* Program EL3 registers to enable entry into the next EL */
|
||||
next_image_info = bl31_plat_get_next_image_ep_info(NON_SECURE);
|
||||
assert(next_image_info);
|
||||
assert(NON_SECURE ==
|
||||
GET_SECURITY_STATE(next_image_info->h.attr));
|
||||
|
||||
cm_init_my_context(next_image_info);
|
||||
cm_prepare_el3_exit(NON_SECURE);
|
||||
SMC_RET0(cm_get_context(NON_SECURE));
|
||||
#else
|
||||
/*
|
||||
* SP reports completion. The SPD must have initiated
|
||||
* the original request through a synchronous entry
|
||||
* into the SP. Jump back to the original C runtime
|
||||
* context.
|
||||
*/
|
||||
tspd_synchronous_sp_exit(tsp_ctx, x1);
|
||||
break;
|
||||
#endif
|
||||
/*
|
||||
* This function ID is used only by the SP to indicate it has finished
|
||||
* aborting a preempted Yielding SMC Call.
|
||||
*/
|
||||
case TSP_ABORT_DONE:
|
||||
|
||||
/*
|
||||
* These function IDs are used only by the SP to indicate it has
|
||||
* finished:
|
||||
* 1. turning itself on in response to an earlier psci
|
||||
* cpu_on request
|
||||
* 2. resuming itself after an earlier psci cpu_suspend
|
||||
* request.
|
||||
*/
|
||||
case TSP_ON_DONE:
|
||||
case TSP_RESUME_DONE:
|
||||
|
||||
/*
|
||||
* These function IDs are used only by the SP to indicate it has
|
||||
* finished:
|
||||
* 1. suspending itself after an earlier psci cpu_suspend
|
||||
* request.
|
||||
* 2. turning itself off in response to an earlier psci
|
||||
* cpu_off request.
|
||||
*/
|
||||
case TSP_OFF_DONE:
|
||||
case TSP_SUSPEND_DONE:
|
||||
case TSP_SYSTEM_OFF_DONE:
|
||||
case TSP_SYSTEM_RESET_DONE:
|
||||
if (ns)
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
|
||||
/*
|
||||
* SP reports completion. The SPD must have initiated the
|
||||
* original request through a synchronous entry into the SP.
|
||||
* Jump back to the original C runtime context, and pass x1 as
|
||||
* return value to the caller
|
||||
*/
|
||||
tspd_synchronous_sp_exit(tsp_ctx, x1);
|
||||
break;
|
||||
|
||||
/*
|
||||
* Request from non-secure client to perform an
|
||||
* arithmetic operation or response from secure
|
||||
* payload to an earlier request.
|
||||
*/
|
||||
case TSP_FAST_FID(TSP_ADD):
|
||||
case TSP_FAST_FID(TSP_SUB):
|
||||
case TSP_FAST_FID(TSP_MUL):
|
||||
case TSP_FAST_FID(TSP_DIV):
|
||||
|
||||
case TSP_YIELD_FID(TSP_ADD):
|
||||
case TSP_YIELD_FID(TSP_SUB):
|
||||
case TSP_YIELD_FID(TSP_MUL):
|
||||
case TSP_YIELD_FID(TSP_DIV):
|
||||
/*
|
||||
* Request from non-secure client to perform a check
|
||||
* of the DIT PSTATE bit.
|
||||
*/
|
||||
case TSP_YIELD_FID(TSP_CHECK_DIT):
|
||||
if (ns) {
|
||||
/*
|
||||
* This is a fresh request from the non-secure client.
|
||||
* The parameters are in x1 and x2. Figure out which
|
||||
* registers need to be preserved, save the non-secure
|
||||
* state and send the request to the secure payload.
|
||||
*/
|
||||
assert(handle == cm_get_context(NON_SECURE));
|
||||
|
||||
/* Check if we are already preempted */
|
||||
if (get_yield_smc_active_flag(tsp_ctx->state))
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
|
||||
cm_el1_sysregs_context_save(NON_SECURE);
|
||||
|
||||
/* Save x1 and x2 for use by TSP_GET_ARGS call below */
|
||||
store_tsp_args(tsp_ctx, x1, x2);
|
||||
|
||||
/*
|
||||
* We are done stashing the non-secure context. Ask the
|
||||
* secure payload to do the work now.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Verify if there is a valid context to use, copy the
|
||||
* operation type and parameters to the secure context
|
||||
* and jump to the fast smc entry point in the secure
|
||||
* payload. Entry into S-EL1 will take place upon exit
|
||||
* from this function.
|
||||
*/
|
||||
assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE));
|
||||
|
||||
/* Set appropriate entry for SMC.
|
||||
* We expect the TSP to manage the PSTATE.I and PSTATE.F
|
||||
* flags as appropriate.
|
||||
*/
|
||||
if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_FAST) {
|
||||
cm_set_elr_el3(SECURE, (uint64_t)
|
||||
&tsp_vectors->fast_smc_entry);
|
||||
} else {
|
||||
set_yield_smc_active_flag(tsp_ctx->state);
|
||||
cm_set_elr_el3(SECURE, (uint64_t)
|
||||
&tsp_vectors->yield_smc_entry);
|
||||
#if TSP_NS_INTR_ASYNC_PREEMPT
|
||||
/*
|
||||
* Enable the routing of NS interrupts to EL3
|
||||
* during processing of a Yielding SMC Call on
|
||||
* this core.
|
||||
*/
|
||||
enable_intr_rm_local(INTR_TYPE_NS, SECURE);
|
||||
#endif
|
||||
|
||||
#if EL3_EXCEPTION_HANDLING
|
||||
/*
|
||||
* With EL3 exception handling, while an SMC is
|
||||
* being processed, Non-secure interrupts can't
|
||||
* preempt Secure execution. However, for
|
||||
* yielding SMCs, we want preemption to happen;
|
||||
* so explicitly allow NS preemption in this
|
||||
* case, and supply the preemption return code
|
||||
* for TSP.
|
||||
*/
|
||||
ehf_allow_ns_preemption(TSP_PREEMPTED);
|
||||
#endif
|
||||
}
|
||||
|
||||
cm_el1_sysregs_context_restore(SECURE);
|
||||
cm_set_next_eret_context(SECURE);
|
||||
SMC_RET3(&tsp_ctx->cpu_ctx, smc_fid, x1, x2);
|
||||
} else {
|
||||
/*
|
||||
* This is the result from the secure client of an
|
||||
* earlier request. The results are in x1-x3. Copy it
|
||||
* into the non-secure context, save the secure state
|
||||
* and return to the non-secure state.
|
||||
*/
|
||||
assert(handle == cm_get_context(SECURE));
|
||||
cm_el1_sysregs_context_save(SECURE);
|
||||
|
||||
/* Get a reference to the non-secure context */
|
||||
ns_cpu_context = cm_get_context(NON_SECURE);
|
||||
assert(ns_cpu_context);
|
||||
|
||||
/* Restore non-secure state */
|
||||
cm_el1_sysregs_context_restore(NON_SECURE);
|
||||
cm_set_next_eret_context(NON_SECURE);
|
||||
if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_YIELD) {
|
||||
clr_yield_smc_active_flag(tsp_ctx->state);
|
||||
#if TSP_NS_INTR_ASYNC_PREEMPT
|
||||
/*
|
||||
* Disable the routing of NS interrupts to EL3
|
||||
* after processing of a Yielding SMC Call on
|
||||
* this core is finished.
|
||||
*/
|
||||
disable_intr_rm_local(INTR_TYPE_NS, SECURE);
|
||||
#endif
|
||||
}
|
||||
|
||||
SMC_RET3(ns_cpu_context, x1, x2, x3);
|
||||
}
|
||||
assert(0); /* Unreachable */
|
||||
|
||||
/*
|
||||
* Request from the non-secure world to abort a preempted Yielding SMC
|
||||
* Call.
|
||||
*/
|
||||
case TSP_FID_ABORT:
|
||||
/* ABORT should only be invoked by normal world */
|
||||
if (!ns) {
|
||||
assert(0);
|
||||
break;
|
||||
}
|
||||
|
||||
assert(handle == cm_get_context(NON_SECURE));
|
||||
cm_el1_sysregs_context_save(NON_SECURE);
|
||||
|
||||
/* Abort the preempted SMC request */
|
||||
if (!tspd_abort_preempted_smc(tsp_ctx)) {
|
||||
/*
|
||||
* If there was no preempted SMC to abort, return
|
||||
* SMC_UNK.
|
||||
*
|
||||
* Restoring the NON_SECURE context is not necessary as
|
||||
* the synchronous entry did not take place if the
|
||||
* return code of tspd_abort_preempted_smc is zero.
|
||||
*/
|
||||
cm_set_next_eret_context(NON_SECURE);
|
||||
break;
|
||||
}
|
||||
|
||||
cm_el1_sysregs_context_restore(NON_SECURE);
|
||||
cm_set_next_eret_context(NON_SECURE);
|
||||
SMC_RET1(handle, SMC_OK);
|
||||
|
||||
/*
|
||||
* Request from non secure world to resume the preempted
|
||||
* Yielding SMC Call.
|
||||
*/
|
||||
case TSP_FID_RESUME:
|
||||
/* RESUME should be invoked only by normal world */
|
||||
if (!ns) {
|
||||
assert(0);
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* This is a resume request from the non-secure client.
|
||||
* save the non-secure state and send the request to
|
||||
* the secure payload.
|
||||
*/
|
||||
assert(handle == cm_get_context(NON_SECURE));
|
||||
|
||||
/* Check if we are already preempted before resume */
|
||||
if (!get_yield_smc_active_flag(tsp_ctx->state))
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
|
||||
cm_el1_sysregs_context_save(NON_SECURE);
|
||||
|
||||
/*
|
||||
* We are done stashing the non-secure context. Ask the
|
||||
* secure payload to do the work now.
|
||||
*/
|
||||
#if TSP_NS_INTR_ASYNC_PREEMPT
|
||||
/*
|
||||
* Enable the routing of NS interrupts to EL3 during resumption
|
||||
* of a Yielding SMC Call on this core.
|
||||
*/
|
||||
enable_intr_rm_local(INTR_TYPE_NS, SECURE);
|
||||
#endif
|
||||
|
||||
#if EL3_EXCEPTION_HANDLING
|
||||
/*
|
||||
* Allow the resumed yielding SMC processing to be preempted by
|
||||
* Non-secure interrupts. Also, supply the preemption return
|
||||
* code for TSP.
|
||||
*/
|
||||
ehf_allow_ns_preemption(TSP_PREEMPTED);
|
||||
#endif
|
||||
|
||||
/* We just need to return to the preempted point in
|
||||
* TSP and the execution will resume as normal.
|
||||
*/
|
||||
cm_el1_sysregs_context_restore(SECURE);
|
||||
cm_set_next_eret_context(SECURE);
|
||||
SMC_RET0(&tsp_ctx->cpu_ctx);
|
||||
|
||||
/*
|
||||
* This is a request from the secure payload for more arguments
|
||||
* for an ongoing arithmetic operation requested by the
|
||||
* non-secure world. Simply return the arguments from the non-
|
||||
* secure client in the original call.
|
||||
*/
|
||||
case TSP_GET_ARGS:
|
||||
if (ns)
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
|
||||
get_tsp_args(tsp_ctx, x1, x2);
|
||||
SMC_RET2(handle, x1, x2);
|
||||
|
||||
case TOS_CALL_COUNT:
|
||||
/*
|
||||
* Return the number of service function IDs implemented to
|
||||
* provide service to non-secure
|
||||
*/
|
||||
SMC_RET1(handle, TSP_NUM_FID);
|
||||
|
||||
case TOS_UID:
|
||||
/* Return TSP UID to the caller */
|
||||
SMC_UUID_RET(handle, tsp_uuid);
|
||||
|
||||
case TOS_CALL_VERSION:
|
||||
/* Return the version of current implementation */
|
||||
SMC_RET2(handle, TSP_VERSION_MAJOR, TSP_VERSION_MINOR);
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
}
|
||||
|
||||
/* Define a SPD runtime service descriptor for fast SMC calls */
|
||||
DECLARE_RT_SVC(
|
||||
tspd_fast,
|
||||
|
||||
OEN_TOS_START,
|
||||
OEN_TOS_END,
|
||||
SMC_TYPE_FAST,
|
||||
tspd_setup,
|
||||
tspd_smc_handler
|
||||
);
|
||||
|
||||
/* Define a SPD runtime service descriptor for Yielding SMC Calls */
|
||||
DECLARE_RT_SVC(
|
||||
tspd_std,
|
||||
|
||||
OEN_TOS_START,
|
||||
OEN_TOS_END,
|
||||
SMC_TYPE_YIELD,
|
||||
NULL,
|
||||
tspd_smc_handler
|
||||
);
|
||||
Reference in New Issue
Block a user