GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/trusted-firmware/trusted-firmware-a-2.8/services/std_svc/drtm/drtm_dma_prot.c

@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ * DRTM DMA protection.
+ *
+ * Authors:
+ *      Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
+ *
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <drivers/arm/smmu_v3.h>
+#include "drtm_dma_prot.h"
+#include "drtm_main.h"
+#include "drtm_remediation.h"
+#include <plat/common/platform.h>
+#include <smccc_helpers.h>
+
+/*
+ *  ________________________  LAUNCH success        ________________________
+ * |        Initial         | -------------------> |      Prot engaged      |
+ * |````````````````````````|                      |````````````````````````|
+ * |  request.type == NONE  |                      |  request.type != NONE  |
+ * |                        | <------------------- |                        |
+ * `________________________'        UNPROTECT_MEM `________________________'
+ *
+ * Transitions that are not shown correspond to ABI calls that do not change
+ * state and result in an error being returned to the caller.
+ */
+static struct dma_prot active_prot = {
+	.type = PROTECT_NONE,
+};
+
+/* Version-independent type. */
+typedef struct drtm_dl_dma_prot_args_v1 struct_drtm_dl_dma_prot_args;
+
+/*
+ * This function checks that platform supports complete DMA protection.
+ * and returns false - if the platform supports complete DMA protection.
+ * and returns true - if the platform does not support complete DMA protection.
+ */
+bool drtm_dma_prot_init(void)
+{
+	bool must_init_fail = false;
+	const uintptr_t *smmus;
+	size_t num_smmus = 0;
+	unsigned int total_smmus;
+
+	/* Warns presence of non-host platforms */
+	if (plat_has_non_host_platforms()) {
+		WARN("DRTM: the platform includes trusted DMA-capable devices"
+				" (non-host platforms)\n");
+	}
+
+	/*
+	 * DLME protection is uncertain on platforms with peripherals whose
+	 * DMA is not managed by an SMMU. DRTM doesn't work on such platforms.
+	 */
+	if (plat_has_unmanaged_dma_peripherals()) {
+		ERROR("DRTM: this platform does not provide DMA protection\n");
+		must_init_fail = true;
+	}
+
+	/*
+	 * Check that the platform reported all SMMUs.
+	 * It is acceptable if the platform doesn't have any SMMUs when it
+	 * doesn't have any DMA-capable devices.
+	 */
+	total_smmus = plat_get_total_smmus();
+	plat_enumerate_smmus(&smmus, &num_smmus);
+	if (num_smmus != total_smmus) {
+		ERROR("DRTM: could not discover all SMMUs\n");
+		must_init_fail = true;
+	}
+
+	return must_init_fail;
+}
+
+/*
+ * Checks that the DMA protection arguments are valid and that the given
+ * protected regions are covered by DMA protection.
+ */
+enum drtm_retc drtm_dma_prot_check_args(const struct_drtm_dl_dma_prot_args *a,
+					int a_dma_prot_type,
+					drtm_mem_region_t p)
+{
+	switch ((enum dma_prot_type)a_dma_prot_type) {
+	case PROTECT_MEM_ALL:
+		if (a->dma_prot_table_paddr || a->dma_prot_table_size) {
+			ERROR("DRTM: invalid launch due to inconsistent"
+			      " DMA protection arguments\n");
+			return MEM_PROTECT_INVALID;
+		}
+		/*
+		 * Full DMA protection ought to ensure that the DLME and NWd
+		 * DCE regions are protected, no further checks required.
+		 */
+		return SUCCESS;
+
+	default:
+		ERROR("DRTM: invalid launch due to unsupported DMA protection type\n");
+		return MEM_PROTECT_INVALID;
+	}
+}
+
+enum drtm_retc drtm_dma_prot_engage(const struct_drtm_dl_dma_prot_args *a,
+				    int a_dma_prot_type)
+{
+	const uintptr_t *smmus;
+	size_t num_smmus = 0;
+
+	if (active_prot.type != PROTECT_NONE) {
+		ERROR("DRTM: launch denied as previous DMA protection"
+		      " is still engaged\n");
+		return DENIED;
+	}
+
+	if (a_dma_prot_type == PROTECT_NONE) {
+		return SUCCESS;
+		/* Only PROTECT_MEM_ALL is supported currently. */
+	} else if (a_dma_prot_type != PROTECT_MEM_ALL) {
+		ERROR("%s(): unimplemented DMA protection type\n", __func__);
+		panic();
+	}
+
+	/*
+	 * Engage SMMUs in accordance with the request we have previously received.
+	 * Only PROTECT_MEM_ALL is implemented currently.
+	 */
+	plat_enumerate_smmus(&smmus, &num_smmus);
+	for (const uintptr_t *smmu = smmus; smmu < smmus+num_smmus; smmu++) {
+		/*
+		 * TODO: Invalidate SMMU's Stage-1 and Stage-2 TLB entries.  This ensures
+		 * that any outstanding device transactions are completed, see Section
+		 * 3.21.1, specification IHI_0070_C_a for an approximate reference.
+		 */
+		int rc = smmuv3_ns_set_abort_all(*smmu);
+		if (rc != 0) {
+			ERROR("DRTM: SMMU at PA 0x%lx failed to engage DMA protection"
+			      " rc=%d\n", *smmu, rc);
+			return INTERNAL_ERROR;
+		}
+	}
+
+	/*
+	 * TODO: Restrict DMA from the GIC.
+	 *
+	 * Full DMA protection may be achieved as follows:
+	 *
+	 * With a GICv3:
+	 * - Set GICR_CTLR.EnableLPIs to 0, for each GICR;
+	 *   GICR_CTLR.RWP == 0 must be the case before finishing, for each GICR.
+	 * - Set GITS_CTLR.Enabled to 0;
+	 *   GITS_CTLR.Quiescent == 1 must be the case before finishing.
+	 *
+	 * In addition, with a GICv4:
+	 * - Set GICR_VPENDBASER.Valid to 0, for each GICR;
+	 *   GICR_CTLR.RWP == 0 must be the case before finishing, for each GICR.
+	 *
+	 * Alternatively, e.g. if some bit values cannot be changed at runtime,
+	 * this procedure should return an error if the LPI Pending and
+	 * Configuration tables overlap the regions being protected.
+	 */
+
+	active_prot.type = a_dma_prot_type;
+
+	return SUCCESS;
+}
+
+/*
+ * Undo what has previously been done in drtm_dma_prot_engage(), or enter
+ * remediation if it is not possible.
+ */
+enum drtm_retc drtm_dma_prot_disengage(void)
+{
+	const uintptr_t *smmus;
+	size_t num_smmus = 0;
+	const char *err_str = "cannot undo PROTECT_MEM_ALL SMMU config";
+
+	if (active_prot.type == PROTECT_NONE) {
+		return SUCCESS;
+		/* Only PROTECT_MEM_ALL is supported currently. */
+	} else if (active_prot.type != PROTECT_MEM_ALL) {
+		ERROR("%s(): unimplemented DMA protection type\n", __func__);
+		panic();
+	}
+
+	/*
+	 * For PROTECT_MEM_ALL, undo the SMMU configuration for "abort all" mode
+	 * done during engage().
+	 */
+	/* Simply enter remediation for now. */
+	(void)smmus;
+	(void)num_smmus;
+	drtm_enter_remediation(1ULL, err_str);
+
+	/* TODO: Undo GIC DMA restrictions. */
+
+	active_prot.type = PROTECT_NONE;
+
+	return SUCCESS;
+}
+
+uint64_t drtm_unprotect_mem(void *ctx)
+{
+	enum drtm_retc ret;
+
+	switch (active_prot.type) {
+	case PROTECT_NONE:
+		ERROR("DRTM: invalid UNPROTECT_MEM, no DMA protection has"
+		      " previously been engaged\n");
+		ret = DENIED;
+		break;
+
+	case PROTECT_MEM_ALL:
+		/*
+		 * UNPROTECT_MEM is a no-op for PROTECT_MEM_ALL:  DRTM must not touch
+		 * the NS SMMU as it is expected that the DLME has configured it.
+		 */
+		active_prot.type = PROTECT_NONE;
+
+		ret = SUCCESS;
+		break;
+
+	default:
+		ret = drtm_dma_prot_disengage();
+		break;
+	}
+
+	SMC_RET1(ctx, ret);
+}
+
+void drtm_dma_prot_serialise_table(uint8_t *dst, size_t *size_out)
+{
+	if (active_prot.type == PROTECT_NONE) {
+		return;
+	} else if (active_prot.type != PROTECT_MEM_ALL) {
+		ERROR("%s(): unimplemented DMA protection type\n", __func__);
+		panic();
+	}
+
+	struct __packed descr_table_1 {
+		drtm_memory_region_descriptor_table_t header;
+		drtm_mem_region_t regions[1];
+	} prot_table = {
+		.header = {
+			.revision = 1,
+			.num_regions = sizeof(((struct descr_table_1 *)NULL)->regions) /
+				sizeof(((struct descr_table_1 *)NULL)->regions[0])
+		},
+		.regions = {
+			{.region_address = 0, PAGES_AND_TYPE(UINT64_MAX, 0x3)},
+		}
+	};
+
+	memcpy(dst, &prot_table, sizeof(prot_table));
+	*size_out = sizeof(prot_table);
+}

source/trusted-firmware/trusted-firmware-a-2.8/services/std_svc/drtm/drtm_dma_prot.h

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ */
+#ifndef DRTM_DMA_PROT_H
+#define DRTM_DMA_PROT_H
+
+#include <stdint.h>
+#include <plat/common/platform.h>
+#include <services/drtm_svc.h>
+
+struct __packed drtm_dl_dma_prot_args_v1 {
+	uint64_t dma_prot_table_paddr;
+	uint64_t dma_prot_table_size;
+};
+
+/* Values for DRTM_PROTECT_MEMORY */
+enum dma_prot_type {
+	PROTECT_NONE    = -1,
+	PROTECT_MEM_ALL = 0,
+	PROTECT_MEM_REGION = 2,
+};
+
+struct dma_prot {
+	enum dma_prot_type type;
+};
+
+#define DRTM_MEM_REGION_PAGES_AND_TYPE(pages, type) \
+	(((uint64_t)(pages) & (((uint64_t)1 << 52) - 1)) \
+	 | (((uint64_t)(type) & 0x7) << 52))
+
+#define PAGES_AND_TYPE(pages, type) \
+		.region_size_type = DRTM_MEM_REGION_PAGES_AND_TYPE(pages, type)
+
+/* Opaque / encapsulated type. */
+typedef struct drtm_dl_dma_prot_args_v1 drtm_dl_dma_prot_args_v1_t;
+
+bool drtm_dma_prot_init(void);
+enum drtm_retc drtm_dma_prot_check_args(const drtm_dl_dma_prot_args_v1_t *a,
+					int a_dma_prot_type,
+					drtm_mem_region_t p);
+enum drtm_retc drtm_dma_prot_engage(const drtm_dl_dma_prot_args_v1_t *a,
+				    int a_dma_prot_type);
+enum drtm_retc drtm_dma_prot_disengage(void);
+uint64_t drtm_unprotect_mem(void *ctx);
+void drtm_dma_prot_serialise_table(uint8_t *dst, size_t *size_out);
+
+#endif /* DRTM_DMA_PROT_H */

source/trusted-firmware/trusted-firmware-a-2.8/services/std_svc/drtm/drtm_main.c

@@ -0,0 +1,839 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ * DRTM service
+ *
+ * Authors:
+ *	Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
+ *	Brian Nezvadovitz <brinez@microsoft.com> 2021-02-01
+ */
+
+#include <stdint.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <drivers/auth/crypto_mod.h>
+#include "drtm_main.h"
+#include "drtm_measurements.h"
+#include "drtm_remediation.h"
+#include <lib/el3_runtime/context_mgmt.h>
+#include <lib/psci/psci_lib.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <plat/common/platform.h>
+#include <services/drtm_svc.h>
+#include <services/sdei.h>
+#include <platform_def.h>
+
+/* Structure to store DRTM features specific to the platform. */
+static drtm_features_t plat_drtm_features;
+
+/* DRTM-formatted memory map. */
+static drtm_memory_region_descriptor_table_t *plat_drtm_mem_map;
+
+/* DLME header */
+struct_dlme_data_header dlme_data_hdr_init;
+
+/* Minimum data memory requirement */
+uint64_t dlme_data_min_size;
+
+int drtm_setup(void)
+{
+	bool rc;
+	const plat_drtm_tpm_features_t *plat_tpm_feat;
+	const plat_drtm_dma_prot_features_t *plat_dma_prot_feat;
+
+	INFO("DRTM service setup\n");
+
+	/* Read boot PE ID from MPIDR */
+	plat_drtm_features.boot_pe_id = read_mpidr_el1() & MPIDR_AFFINITY_MASK;
+
+	rc = drtm_dma_prot_init();
+	if (rc) {
+		return INTERNAL_ERROR;
+	}
+
+	/*
+	 * initialise the platform supported crypto module that will
+	 * be used by the DRTM-service to calculate hash of DRTM-
+	 * implementation specific components
+	 */
+	crypto_mod_init();
+
+	/* Build DRTM-compatible address map. */
+	plat_drtm_mem_map = drtm_build_address_map();
+	if (plat_drtm_mem_map == NULL) {
+		return INTERNAL_ERROR;
+	}
+
+	/* Get DRTM features from platform hooks. */
+	plat_tpm_feat = plat_drtm_get_tpm_features();
+	if (plat_tpm_feat == NULL) {
+		return INTERNAL_ERROR;
+	}
+
+	plat_dma_prot_feat = plat_drtm_get_dma_prot_features();
+	if (plat_dma_prot_feat == NULL) {
+		return INTERNAL_ERROR;
+	}
+
+	/*
+	 * Add up minimum DLME data memory.
+	 *
+	 * For systems with complete DMA protection there is only one entry in
+	 * the protected regions table.
+	 */
+	if (plat_dma_prot_feat->dma_protection_support ==
+			ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_COMPLETE) {
+		dlme_data_min_size =
+			sizeof(drtm_memory_region_descriptor_table_t) +
+			sizeof(drtm_mem_region_t);
+		dlme_data_hdr_init.dlme_prot_regions_size = dlme_data_min_size;
+	} else {
+		/*
+		 * TODO set protected regions table size based on platform DMA
+		 * protection configuration
+		 */
+		panic();
+	}
+
+	dlme_data_hdr_init.dlme_addr_map_size = drtm_get_address_map_size();
+	dlme_data_hdr_init.dlme_tcb_hashes_table_size =
+				plat_drtm_get_tcb_hash_table_size();
+	dlme_data_hdr_init.dlme_impdef_region_size =
+				plat_drtm_get_imp_def_dlme_region_size();
+
+	dlme_data_min_size += dlme_data_hdr_init.dlme_addr_map_size +
+			      PLAT_DRTM_EVENT_LOG_MAX_SIZE +
+			      dlme_data_hdr_init.dlme_tcb_hashes_table_size +
+			      dlme_data_hdr_init.dlme_impdef_region_size;
+
+	dlme_data_min_size = page_align(dlme_data_min_size, UP)/PAGE_SIZE;
+
+	/* Fill out platform DRTM features structure */
+	/* Only support default PCR schema (0x1) in this implementation. */
+	ARM_DRTM_TPM_FEATURES_SET_PCR_SCHEMA(plat_drtm_features.tpm_features,
+		ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_DEFAULT);
+	ARM_DRTM_TPM_FEATURES_SET_TPM_HASH(plat_drtm_features.tpm_features,
+		plat_tpm_feat->tpm_based_hash_support);
+	ARM_DRTM_TPM_FEATURES_SET_FW_HASH(plat_drtm_features.tpm_features,
+		plat_tpm_feat->firmware_hash_algorithm);
+	ARM_DRTM_MIN_MEM_REQ_SET_MIN_DLME_DATA_SIZE(plat_drtm_features.minimum_memory_requirement,
+		dlme_data_min_size);
+	ARM_DRTM_MIN_MEM_REQ_SET_DCE_SIZE(plat_drtm_features.minimum_memory_requirement,
+		plat_drtm_get_min_size_normal_world_dce());
+	ARM_DRTM_DMA_PROT_FEATURES_SET_MAX_REGIONS(plat_drtm_features.dma_prot_features,
+		plat_dma_prot_feat->max_num_mem_prot_regions);
+	ARM_DRTM_DMA_PROT_FEATURES_SET_DMA_SUPPORT(plat_drtm_features.dma_prot_features,
+		plat_dma_prot_feat->dma_protection_support);
+	ARM_DRTM_TCB_HASH_FEATURES_SET_MAX_NUM_HASHES(plat_drtm_features.tcb_hash_features,
+		plat_drtm_get_tcb_hash_features());
+
+	return 0;
+}
+
+static inline void invalidate_icache_all(void)
+{
+	__asm__ volatile("ic      ialluis");
+	dsb();
+	isb();
+}
+
+static inline uint64_t drtm_features_tpm(void *ctx)
+{
+	SMC_RET2(ctx, 1ULL, /* TPM feature is supported */
+		 plat_drtm_features.tpm_features);
+}
+
+static inline uint64_t drtm_features_mem_req(void *ctx)
+{
+	SMC_RET2(ctx, 1ULL, /* memory req Feature is supported */
+		 plat_drtm_features.minimum_memory_requirement);
+}
+
+static inline uint64_t drtm_features_boot_pe_id(void *ctx)
+{
+	SMC_RET2(ctx, 1ULL, /* Boot PE feature is supported */
+		 plat_drtm_features.boot_pe_id);
+}
+
+static inline uint64_t drtm_features_dma_prot(void *ctx)
+{
+	SMC_RET2(ctx, 1ULL, /* DMA protection feature is supported */
+		 plat_drtm_features.dma_prot_features);
+}
+
+static inline uint64_t drtm_features_tcb_hashes(void *ctx)
+{
+	SMC_RET2(ctx, 1ULL, /* TCB hash feature is supported */
+		 plat_drtm_features.tcb_hash_features);
+}
+
+static enum drtm_retc drtm_dl_check_caller_el(void *ctx)
+{
+	uint64_t spsr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SPSR_EL3);
+	uint64_t dl_caller_el;
+	uint64_t dl_caller_aarch;
+
+	dl_caller_el = spsr_el3 >> MODE_EL_SHIFT & MODE_EL_MASK;
+	dl_caller_aarch = spsr_el3 >> MODE_RW_SHIFT & MODE_RW_MASK;
+
+	/* Caller's security state is checked from drtm_smc_handle function */
+
+	/* Caller can be NS-EL2/EL1 */
+	if (dl_caller_el == MODE_EL3) {
+		ERROR("DRTM: invalid launch from EL3\n");
+		return DENIED;
+	}
+
+	if (dl_caller_aarch != MODE_RW_64) {
+		ERROR("DRTM: invalid launch from non-AArch64 execution state\n");
+		return DENIED;
+	}
+
+	return SUCCESS;
+}
+
+static enum drtm_retc drtm_dl_check_cores(void)
+{
+	bool running_on_single_core;
+	uint64_t this_pe_aff_value = read_mpidr_el1() & MPIDR_AFFINITY_MASK;
+
+	if (this_pe_aff_value != plat_drtm_features.boot_pe_id) {
+		ERROR("DRTM: invalid launch on a non-boot PE\n");
+		return DENIED;
+	}
+
+	running_on_single_core = psci_is_last_on_cpu_safe();
+	if (!running_on_single_core) {
+		ERROR("DRTM: invalid launch due to non-boot PE not being turned off\n");
+		return DENIED;
+	}
+
+	return SUCCESS;
+}
+
+static enum drtm_retc drtm_dl_prepare_dlme_data(const struct_drtm_dl_args *args)
+{
+	int rc;
+	uint64_t dlme_data_paddr;
+	size_t dlme_data_max_size;
+	uintptr_t dlme_data_mapping;
+	struct_dlme_data_header *dlme_data_hdr;
+	uint8_t *dlme_data_cursor;
+	size_t dlme_data_mapping_bytes;
+	size_t serialised_bytes_actual;
+
+	dlme_data_paddr = args->dlme_paddr + args->dlme_data_off;
+	dlme_data_max_size = args->dlme_size - args->dlme_data_off;
+
+	/*
+	 * The capacity of the given DLME data region is checked when
+	 * the other dynamic launch arguments are.
+	 */
+	if (dlme_data_max_size < dlme_data_min_size) {
+		ERROR("%s: assertion failed:"
+		      " dlme_data_max_size (%ld) < dlme_data_total_bytes_req (%ld)\n",
+		      __func__, dlme_data_max_size, dlme_data_min_size);
+		panic();
+	}
+
+	/* Map the DLME data region as NS memory. */
+	dlme_data_mapping_bytes = ALIGNED_UP(dlme_data_max_size, DRTM_PAGE_SIZE);
+	rc = mmap_add_dynamic_region_alloc_va(dlme_data_paddr,
+					      &dlme_data_mapping,
+					      dlme_data_mapping_bytes,
+					      MT_RW_DATA | MT_NS |
+					      MT_SHAREABILITY_ISH);
+	if (rc != 0) {
+		WARN("DRTM: %s: mmap_add_dynamic_region() failed rc=%d\n",
+		     __func__, rc);
+		return INTERNAL_ERROR;
+	}
+	dlme_data_hdr = (struct_dlme_data_header *)dlme_data_mapping;
+	dlme_data_cursor = (uint8_t *)dlme_data_hdr + sizeof(*dlme_data_hdr);
+
+	memcpy(dlme_data_hdr, (const void *)&dlme_data_hdr_init,
+	       sizeof(*dlme_data_hdr));
+
+	/* Set the header version and size. */
+	dlme_data_hdr->version = 1;
+	dlme_data_hdr->this_hdr_size = sizeof(*dlme_data_hdr);
+
+	/* Prepare DLME protected regions. */
+	drtm_dma_prot_serialise_table(dlme_data_cursor,
+				      &serialised_bytes_actual);
+	assert(serialised_bytes_actual ==
+	       dlme_data_hdr->dlme_prot_regions_size);
+	dlme_data_cursor += serialised_bytes_actual;
+
+	/* Prepare DLME address map. */
+	if (plat_drtm_mem_map != NULL) {
+		memcpy(dlme_data_cursor, plat_drtm_mem_map,
+		       dlme_data_hdr->dlme_addr_map_size);
+	} else {
+		WARN("DRTM: DLME address map is not in the cache\n");
+	}
+	dlme_data_cursor += dlme_data_hdr->dlme_addr_map_size;
+
+	/* Prepare DRTM event log for DLME. */
+	drtm_serialise_event_log(dlme_data_cursor, &serialised_bytes_actual);
+	assert(serialised_bytes_actual <= PLAT_DRTM_EVENT_LOG_MAX_SIZE);
+	dlme_data_hdr->dlme_tpm_log_size = serialised_bytes_actual;
+	dlme_data_cursor += serialised_bytes_actual;
+
+	/*
+	 * TODO: Prepare the TCB hashes for DLME, currently its size
+	 * 0
+	 */
+	dlme_data_cursor += dlme_data_hdr->dlme_tcb_hashes_table_size;
+
+	/* Implementation-specific region size is unused. */
+	dlme_data_cursor += dlme_data_hdr->dlme_impdef_region_size;
+
+	/*
+	 * Prepare DLME data size, includes all data region referenced above
+	 * alongwith the DLME data header
+	 */
+	dlme_data_hdr->dlme_data_size = dlme_data_cursor - (uint8_t *)dlme_data_hdr;
+
+	/* Unmap the DLME data region. */
+	rc = mmap_remove_dynamic_region(dlme_data_mapping, dlme_data_mapping_bytes);
+	if (rc != 0) {
+		ERROR("%s(): mmap_remove_dynamic_region() failed"
+		      " unexpectedly rc=%d\n", __func__, rc);
+		panic();
+	}
+
+	return SUCCESS;
+}
+
+/*
+ * Note: accesses to the dynamic launch args, and to the DLME data are
+ * little-endian as required, thanks to TF-A BL31 init requirements.
+ */
+static enum drtm_retc drtm_dl_check_args(uint64_t x1,
+					 struct_drtm_dl_args *a_out)
+{
+	uint64_t dlme_start, dlme_end;
+	uint64_t dlme_img_start, dlme_img_ep, dlme_img_end;
+	uint64_t dlme_data_start, dlme_data_end;
+	uintptr_t va_mapping;
+	size_t va_mapping_size;
+	struct_drtm_dl_args *a;
+	struct_drtm_dl_args args_buf;
+	int rc;
+
+	if (x1 % DRTM_PAGE_SIZE != 0) {
+		ERROR("DRTM: parameters structure is not "
+		      DRTM_PAGE_SIZE_STR "-aligned\n");
+		return INVALID_PARAMETERS;
+	}
+
+	va_mapping_size = ALIGNED_UP(sizeof(struct_drtm_dl_args), DRTM_PAGE_SIZE);
+
+	/* check DRTM parameters are within NS address region */
+	rc = plat_drtm_validate_ns_region(x1, va_mapping_size);
+	if (rc != 0) {
+		ERROR("DRTM: parameters lies within secure memory\n");
+		return INVALID_PARAMETERS;
+	}
+
+	rc = mmap_add_dynamic_region_alloc_va(x1, &va_mapping, va_mapping_size,
+					      MT_MEMORY | MT_NS | MT_RO |
+					      MT_SHAREABILITY_ISH);
+	if (rc != 0) {
+		WARN("DRTM: %s: mmap_add_dynamic_region() failed rc=%d\n",
+		      __func__, rc);
+		return INTERNAL_ERROR;
+	}
+	a = (struct_drtm_dl_args *)va_mapping;
+
+	/* Sanitize cache of data passed in args by the DCE Preamble. */
+	flush_dcache_range(va_mapping, va_mapping_size);
+
+	args_buf = *a;
+
+	rc = mmap_remove_dynamic_region(va_mapping, va_mapping_size);
+	if (rc) {
+		ERROR("%s(): mmap_remove_dynamic_region() failed unexpectedly"
+		      " rc=%d\n", __func__, rc);
+		panic();
+	}
+	a = &args_buf;
+
+	if (!((a->version >= ARM_DRTM_PARAMS_MIN_VERSION) &&
+	    (a->version <= ARM_DRTM_PARAMS_MAX_VERSION))) {
+		ERROR("DRTM: parameters structure version %u is unsupported\n",
+		      a->version);
+		return NOT_SUPPORTED;
+	}
+
+	if (!(a->dlme_img_off < a->dlme_size &&
+	      a->dlme_data_off < a->dlme_size)) {
+		ERROR("DRTM: argument offset is outside of the DLME region\n");
+		return INVALID_PARAMETERS;
+	}
+	dlme_start = a->dlme_paddr;
+	dlme_end = a->dlme_paddr + a->dlme_size;
+	dlme_img_start = a->dlme_paddr + a->dlme_img_off;
+	dlme_img_ep = dlme_img_start + a->dlme_img_ep_off;
+	dlme_img_end = dlme_img_start + a->dlme_img_size;
+	dlme_data_start = a->dlme_paddr + a->dlme_data_off;
+	dlme_data_end = dlme_end;
+
+	/* Check the DLME regions arguments. */
+	if ((dlme_start % DRTM_PAGE_SIZE) != 0) {
+		ERROR("DRTM: argument DLME region is not "
+		      DRTM_PAGE_SIZE_STR "-aligned\n");
+		return INVALID_PARAMETERS;
+	}
+
+	if (!(dlme_start < dlme_end &&
+	      dlme_start <= dlme_img_start && dlme_img_start < dlme_img_end &&
+	      dlme_start <= dlme_data_start && dlme_data_start < dlme_data_end)) {
+		ERROR("DRTM: argument DLME region is discontiguous\n");
+		return INVALID_PARAMETERS;
+	}
+
+	if (dlme_img_start < dlme_data_end && dlme_data_start < dlme_img_end) {
+		ERROR("DRTM: argument DLME regions overlap\n");
+		return INVALID_PARAMETERS;
+	}
+
+	/* Check the DLME image region arguments. */
+	if ((dlme_img_start % DRTM_PAGE_SIZE) != 0) {
+		ERROR("DRTM: argument DLME image region is not "
+		      DRTM_PAGE_SIZE_STR "-aligned\n");
+		return INVALID_PARAMETERS;
+	}
+
+	if (!(dlme_img_start <= dlme_img_ep && dlme_img_ep < dlme_img_end)) {
+		ERROR("DRTM: DLME entry point is outside of the DLME image region\n");
+		return INVALID_PARAMETERS;
+	}
+
+	if ((dlme_img_ep % 4) != 0) {
+		ERROR("DRTM: DLME image entry point is not 4-byte-aligned\n");
+		return INVALID_PARAMETERS;
+	}
+
+	/* Check the DLME data region arguments. */
+	if ((dlme_data_start % DRTM_PAGE_SIZE) != 0) {
+		ERROR("DRTM: argument DLME data region is not "
+		      DRTM_PAGE_SIZE_STR "-aligned\n");
+		return INVALID_PARAMETERS;
+	}
+
+	if (dlme_data_end - dlme_data_start < dlme_data_min_size) {
+		ERROR("DRTM: argument DLME data region is short of %lu bytes\n",
+		      dlme_data_min_size - (size_t)(dlme_data_end - dlme_data_start));
+		return INVALID_PARAMETERS;
+	}
+
+	/* check DLME region (paddr + size) is within a NS address region */
+	rc = plat_drtm_validate_ns_region(dlme_start, (size_t)a->dlme_size);
+	if (rc != 0) {
+		ERROR("DRTM: DLME region lies within secure memory\n");
+		return INVALID_PARAMETERS;
+	}
+
+	/* Check the Normal World DCE region arguments. */
+	if (a->dce_nwd_paddr != 0) {
+		uint32_t dce_nwd_start = a->dce_nwd_paddr;
+		uint32_t dce_nwd_end = dce_nwd_start + a->dce_nwd_size;
+
+		if (!(dce_nwd_start < dce_nwd_end)) {
+			ERROR("DRTM: argument Normal World DCE region is dicontiguous\n");
+			return INVALID_PARAMETERS;
+		}
+
+		if (dce_nwd_start < dlme_end && dlme_start < dce_nwd_end) {
+			ERROR("DRTM: argument Normal World DCE regions overlap\n");
+			return INVALID_PARAMETERS;
+		}
+	}
+
+	/*
+	 * Map and sanitize the cache of data range passed by DCE Preamble. This
+	 * is required to avoid / defend against racing with cache evictions
+	 */
+	va_mapping_size = ALIGNED_UP((dlme_end - dlme_start), DRTM_PAGE_SIZE);
+	rc = mmap_add_dynamic_region_alloc_va(dlme_img_start, &va_mapping, va_mapping_size,
+					      MT_MEMORY | MT_NS | MT_RO |
+					      MT_SHAREABILITY_ISH);
+	if (rc != 0) {
+		ERROR("DRTM: %s: mmap_add_dynamic_region_alloc_va() failed rc=%d\n",
+		      __func__, rc);
+		return INTERNAL_ERROR;
+	}
+	flush_dcache_range(va_mapping, va_mapping_size);
+
+	rc = mmap_remove_dynamic_region(va_mapping, va_mapping_size);
+	if (rc) {
+		ERROR("%s(): mmap_remove_dynamic_region() failed unexpectedly"
+		      " rc=%d\n", __func__, rc);
+		panic();
+	}
+
+	*a_out = *a;
+	return SUCCESS;
+}
+
+static void drtm_dl_reset_dlme_el_state(enum drtm_dlme_el dlme_el)
+{
+	uint64_t sctlr;
+
+	/*
+	 * TODO: Set PE state according to the PSCI's specification of the initial
+	 * state after CPU_ON, or to reset values if unspecified, where they exist,
+	 * or define sensible values otherwise.
+	 */
+
+	switch (dlme_el) {
+	case DLME_AT_EL1:
+		sctlr = read_sctlr_el1();
+		break;
+
+	case DLME_AT_EL2:
+		sctlr = read_sctlr_el2();
+		break;
+
+	default: /* Not reached */
+		ERROR("%s(): dlme_el has the unexpected value %d\n",
+		      __func__, dlme_el);
+		panic();
+	}
+
+	sctlr &= ~(/* Disable DLME's EL MMU, since the existing page-tables are untrusted. */
+		   SCTLR_M_BIT
+		   | SCTLR_EE_BIT               /* Little-endian data accesses. */
+		  );
+
+	sctlr |= SCTLR_C_BIT | SCTLR_I_BIT; /* Allow instruction and data caching. */
+
+	switch (dlme_el) {
+	case DLME_AT_EL1:
+		write_sctlr_el1(sctlr);
+		break;
+
+	case DLME_AT_EL2:
+		write_sctlr_el2(sctlr);
+		break;
+	}
+}
+
+static void drtm_dl_reset_dlme_context(enum drtm_dlme_el dlme_el)
+{
+	void *ns_ctx = cm_get_context(NON_SECURE);
+	gp_regs_t *gpregs = get_gpregs_ctx(ns_ctx);
+	uint64_t spsr_el3 = read_ctx_reg(get_el3state_ctx(ns_ctx), CTX_SPSR_EL3);
+
+	/* Reset all gpregs, including SP_EL0. */
+	memset(gpregs, 0, sizeof(*gpregs));
+
+	/* Reset SP_ELx. */
+	switch (dlme_el) {
+	case DLME_AT_EL1:
+		write_sp_el1(0);
+		break;
+
+	case DLME_AT_EL2:
+		write_sp_el2(0);
+		break;
+	}
+
+	/*
+	 * DLME's async exceptions are masked to avoid a NWd attacker's timed
+	 * interference with any state we established trust in or measured.
+	 */
+	spsr_el3 |= SPSR_DAIF_MASK << SPSR_DAIF_SHIFT;
+
+	write_ctx_reg(get_el3state_ctx(ns_ctx), CTX_SPSR_EL3, spsr_el3);
+}
+
+static void drtm_dl_prepare_eret_to_dlme(const struct_drtm_dl_args *args, enum drtm_dlme_el dlme_el)
+{
+	void *ctx = cm_get_context(NON_SECURE);
+	uint64_t dlme_ep = DL_ARGS_GET_DLME_ENTRY_POINT(args);
+	uint64_t spsr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SPSR_EL3);
+
+	/* Next ERET is to the DLME's EL. */
+	spsr_el3 &= ~(MODE_EL_MASK << MODE_EL_SHIFT);
+	switch (dlme_el) {
+	case DLME_AT_EL1:
+		spsr_el3 |= MODE_EL1 << MODE_EL_SHIFT;
+		break;
+
+	case DLME_AT_EL2:
+		spsr_el3 |= MODE_EL2 << MODE_EL_SHIFT;
+		break;
+	}
+
+	/* Next ERET is to the DLME entry point. */
+	cm_set_elr_spsr_el3(NON_SECURE, dlme_ep, spsr_el3);
+}
+
+static uint64_t drtm_dynamic_launch(uint64_t x1, void *handle)
+{
+	enum drtm_retc ret = SUCCESS;
+	enum drtm_retc dma_prot_ret;
+	struct_drtm_dl_args args;
+	/* DLME should be highest NS exception level */
+	enum drtm_dlme_el dlme_el = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
+
+	/* Ensure that only boot PE is powered on */
+	ret = drtm_dl_check_cores();
+	if (ret != SUCCESS) {
+		SMC_RET1(handle, ret);
+	}
+
+	/*
+	 * Ensure that execution state is AArch64 and the caller
+	 * is highest non-secure exception level
+	 */
+	ret = drtm_dl_check_caller_el(handle);
+	if (ret != SUCCESS) {
+		SMC_RET1(handle, ret);
+	}
+
+	ret = drtm_dl_check_args(x1, &args);
+	if (ret != SUCCESS) {
+		SMC_RET1(handle, ret);
+	}
+
+	/* Ensure that there are no SDEI event registered */
+#if SDEI_SUPPORT
+	if (sdei_get_registered_event_count() != 0) {
+		SMC_RET1(handle, DENIED);
+	}
+#endif /* SDEI_SUPPORT */
+
+	/*
+	 * Engage the DMA protections.  The launch cannot proceed without the DMA
+	 * protections due to potential TOC/TOU vulnerabilities w.r.t. the DLME
+	 * region (and to the NWd DCE region).
+	 */
+	ret = drtm_dma_prot_engage(&args.dma_prot_args,
+				   DL_ARGS_GET_DMA_PROT_TYPE(&args));
+	if (ret != SUCCESS) {
+		SMC_RET1(handle, ret);
+	}
+
+	/*
+	 * The DMA protection is now engaged.  Note that any failure mode that
+	 * returns an error to the DRTM-launch caller must now disengage DMA
+	 * protections before returning to the caller.
+	 */
+
+	ret = drtm_take_measurements(&args);
+	if (ret != SUCCESS) {
+		goto err_undo_dma_prot;
+	}
+
+	ret = drtm_dl_prepare_dlme_data(&args);
+	if (ret != SUCCESS) {
+		goto err_undo_dma_prot;
+	}
+
+	/*
+	 * Note that, at the time of writing, the DRTM spec allows a successful
+	 * launch from NS-EL1 to return to a DLME in NS-EL2.  The practical risk
+	 * of a privilege escalation, e.g. due to a compromised hypervisor, is
+	 * considered small enough not to warrant the specification of additional
+	 * DRTM conduits that would be necessary to maintain OSs' abstraction from
+	 * the presence of EL2 were the dynamic launch only be allowed from the
+	 * highest NS EL.
+	 */
+
+	dlme_el = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
+
+	drtm_dl_reset_dlme_el_state(dlme_el);
+	drtm_dl_reset_dlme_context(dlme_el);
+
+	drtm_dl_prepare_eret_to_dlme(&args, dlme_el);
+
+	/*
+	 * As per DRTM beta0 spec table #28 invalidate the instruction cache
+	 * before jumping to the DLME. This is required to defend against
+	 * potentially-malicious cache contents.
+	 */
+	invalidate_icache_all();
+
+	/* Return the DLME region's address in x0, and the DLME data offset in x1.*/
+	SMC_RET2(handle, args.dlme_paddr, args.dlme_data_off);
+
+err_undo_dma_prot:
+	dma_prot_ret = drtm_dma_prot_disengage();
+	if (dma_prot_ret != SUCCESS) {
+		ERROR("%s(): drtm_dma_prot_disengage() failed unexpectedly"
+		      " rc=%d\n", __func__, ret);
+		panic();
+	}
+
+	SMC_RET1(handle, ret);
+}
+
+uint64_t drtm_smc_handler(uint32_t smc_fid,
+			  uint64_t x1,
+			  uint64_t x2,
+			  uint64_t x3,
+			  uint64_t x4,
+			  void *cookie,
+			  void *handle,
+			  uint64_t flags)
+{
+	/* Check that the SMC call is from the Normal World. */
+	if (!is_caller_non_secure(flags)) {
+		SMC_RET1(handle, NOT_SUPPORTED);
+	}
+
+	switch (smc_fid) {
+	case ARM_DRTM_SVC_VERSION:
+		INFO("DRTM service handler: version\n");
+		/* Return the version of current implementation */
+		SMC_RET1(handle, ARM_DRTM_VERSION);
+		break;	/* not reached */
+
+	case ARM_DRTM_SVC_FEATURES:
+		if (((x1 >> ARM_DRTM_FUNC_SHIFT) & ARM_DRTM_FUNC_MASK) ==
+		    ARM_DRTM_FUNC_ID) {
+			/* Dispatch function-based queries. */
+			switch (x1 & FUNCID_MASK) {
+			case ARM_DRTM_SVC_VERSION:
+				SMC_RET1(handle, SUCCESS);
+				break;	/* not reached */
+
+			case ARM_DRTM_SVC_FEATURES:
+				SMC_RET1(handle, SUCCESS);
+				break;	/* not reached */
+
+			case ARM_DRTM_SVC_UNPROTECT_MEM:
+				SMC_RET1(handle, SUCCESS);
+				break;	/* not reached */
+
+			case ARM_DRTM_SVC_DYNAMIC_LAUNCH:
+				SMC_RET1(handle, SUCCESS);
+				break;	/* not reached */
+
+			case ARM_DRTM_SVC_CLOSE_LOCALITY:
+				WARN("ARM_DRTM_SVC_CLOSE_LOCALITY feature %s",
+				     "is not supported\n");
+				SMC_RET1(handle, NOT_SUPPORTED);
+				break;	/* not reached */
+
+			case ARM_DRTM_SVC_GET_ERROR:
+				SMC_RET1(handle, SUCCESS);
+				break;	/* not reached */
+
+			case ARM_DRTM_SVC_SET_ERROR:
+				SMC_RET1(handle, SUCCESS);
+				break;	/* not reached */
+
+			case ARM_DRTM_SVC_SET_TCB_HASH:
+				WARN("ARM_DRTM_SVC_TCB_HASH feature %s",
+				     "is not supported\n");
+				SMC_RET1(handle, NOT_SUPPORTED);
+				break;	/* not reached */
+
+			case ARM_DRTM_SVC_LOCK_TCB_HASH:
+				WARN("ARM_DRTM_SVC_LOCK_TCB_HASH feature %s",
+				     "is not supported\n");
+				SMC_RET1(handle, NOT_SUPPORTED);
+				break;	/* not reached */
+
+			default:
+				ERROR("Unknown DRTM service function\n");
+				SMC_RET1(handle, NOT_SUPPORTED);
+				break;	/* not reached */
+			}
+		} else {
+			/* Dispatch feature-based queries. */
+			switch (x1 & ARM_DRTM_FEAT_ID_MASK) {
+			case ARM_DRTM_FEATURES_TPM:
+				INFO("++ DRTM service handler: TPM features\n");
+				return drtm_features_tpm(handle);
+				break;	/* not reached */
+
+			case ARM_DRTM_FEATURES_MEM_REQ:
+				INFO("++ DRTM service handler: Min. mem."
+				     " requirement features\n");
+				return drtm_features_mem_req(handle);
+				break;	/* not reached */
+
+			case ARM_DRTM_FEATURES_DMA_PROT:
+				INFO("++ DRTM service handler: "
+				     "DMA protection features\n");
+				return drtm_features_dma_prot(handle);
+				break;	/* not reached */
+
+			case ARM_DRTM_FEATURES_BOOT_PE_ID:
+				INFO("++ DRTM service handler: "
+				     "Boot PE ID features\n");
+				return drtm_features_boot_pe_id(handle);
+				break;	/* not reached */
+
+			case ARM_DRTM_FEATURES_TCB_HASHES:
+				INFO("++ DRTM service handler: "
+				     "TCB-hashes features\n");
+				return drtm_features_tcb_hashes(handle);
+				break;	/* not reached */
+
+			default:
+				ERROR("Unknown ARM DRTM service feature\n");
+				SMC_RET1(handle, NOT_SUPPORTED);
+				break;	/* not reached */
+			}
+		}
+
+	case ARM_DRTM_SVC_UNPROTECT_MEM:
+		INFO("DRTM service handler: unprotect mem\n");
+		return drtm_unprotect_mem(handle);
+		break;	/* not reached */
+
+	case ARM_DRTM_SVC_DYNAMIC_LAUNCH:
+		INFO("DRTM service handler: dynamic launch\n");
+		return drtm_dynamic_launch(x1, handle);
+		break;	/* not reached */
+
+	case ARM_DRTM_SVC_CLOSE_LOCALITY:
+		WARN("DRTM service handler: close locality %s\n",
+		     "is not supported");
+		SMC_RET1(handle, NOT_SUPPORTED);
+		break;	/* not reached */
+
+	case ARM_DRTM_SVC_GET_ERROR:
+		INFO("DRTM service handler: get error\n");
+		drtm_get_error(handle);
+		break;	/* not reached */
+
+	case ARM_DRTM_SVC_SET_ERROR:
+		INFO("DRTM service handler: set error\n");
+		drtm_set_error(x1, handle);
+		break;	/* not reached */
+
+	case ARM_DRTM_SVC_SET_TCB_HASH:
+		WARN("DRTM service handler: set TCB hash %s\n",
+		     "is not supported");
+		SMC_RET1(handle, NOT_SUPPORTED);
+		break;  /* not reached */
+
+	case ARM_DRTM_SVC_LOCK_TCB_HASH:
+		WARN("DRTM service handler: lock TCB hash %s\n",
+		     "is not supported");
+		SMC_RET1(handle, NOT_SUPPORTED);
+		break;  /* not reached */
+
+	default:
+		ERROR("Unknown DRTM service function: 0x%x\n", smc_fid);
+		SMC_RET1(handle, SMC_UNK);
+		break;	/* not reached */
+	}
+
+	/* not reached */
+	SMC_RET1(handle, SMC_UNK);
+}

source/trusted-firmware/trusted-firmware-a-2.8/services/std_svc/drtm/drtm_main.h

@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ */
+#ifndef DRTM_MAIN_H
+#define DRTM_MAIN_H
+
+#include <stdint.h>
+
+#include <assert.h>
+#include <lib/smccc.h>
+
+#include "drtm_dma_prot.h"
+
+#define ALIGNED_UP(x, a) __extension__ ({ \
+	__typeof__(a) _a = (a); \
+	__typeof__(a) _one = 1; \
+	assert(IS_POWER_OF_TWO(_a)); \
+	((x) + (_a - _one)) & ~(_a - _one); \
+})
+
+#define ALIGNED_DOWN(x, a) __extension__ ({ \
+	__typeof__(a) _a = (a); \
+	__typeof__(a) _one = 1; \
+	assert(IS_POWER_OF_TWO(_a)); \
+	(x) & ~(_a - _one); \
+})
+
+#define DRTM_PAGE_SIZE		(4 * (1 << 10))
+#define DRTM_PAGE_SIZE_STR	"4-KiB"
+
+#define DL_ARGS_GET_DMA_PROT_TYPE(a)    (((a)->features >> 3) & 0x7U)
+#define DL_ARGS_GET_PCR_SCHEMA(a)	(((a)->features >> 1) & 0x3U)
+#define DL_ARGS_GET_DLME_ENTRY_POINT(a)	\
+		(((a)->dlme_paddr + (a)->dlme_img_off + (a)->dlme_img_ep_off))
+
+/*
+ * Range(Min/Max) of DRTM parameter structure versions supported
+ */
+#define ARM_DRTM_PARAMS_MIN_VERSION	U(1)
+#define ARM_DRTM_PARAMS_MAX_VERSION	U(1)
+
+enum drtm_dlme_el {
+	DLME_AT_EL1 = MODE_EL1,
+	DLME_AT_EL2 = MODE_EL2
+};
+
+enum drtm_retc {
+	SUCCESS = SMC_OK,
+	NOT_SUPPORTED = SMC_UNK,
+	INVALID_PARAMETERS = -2,
+	DENIED = -3,
+	NOT_FOUND = -4,
+	INTERNAL_ERROR = -5,
+	MEM_PROTECT_INVALID = -6,
+};
+
+typedef struct {
+	uint64_t tpm_features;
+	uint64_t minimum_memory_requirement;
+	uint64_t dma_prot_features;
+	uint64_t boot_pe_id;
+	uint64_t tcb_hash_features;
+} drtm_features_t;
+
+struct __packed drtm_dl_args_v1 {
+	uint16_t version;	/* Must be 1. */
+	uint8_t __res[2];
+	uint32_t features;
+	uint64_t dlme_paddr;
+	uint64_t dlme_size;
+	uint64_t dlme_img_off;
+	uint64_t dlme_img_ep_off;
+	uint64_t dlme_img_size;
+	uint64_t dlme_data_off;
+	uint64_t dce_nwd_paddr;
+	uint64_t dce_nwd_size;
+	drtm_dl_dma_prot_args_v1_t dma_prot_args;
+} __aligned(__alignof(uint16_t /* First member's type, `uint16_t version' */));
+
+struct __packed dlme_data_header_v1 {
+	uint16_t version;	/* Must be 1. */
+	uint16_t this_hdr_size;
+	uint8_t __res[4];
+	uint64_t dlme_data_size;
+	uint64_t dlme_prot_regions_size;
+	uint64_t dlme_addr_map_size;
+	uint64_t dlme_tpm_log_size;
+	uint64_t dlme_tcb_hashes_table_size;
+	uint64_t dlme_impdef_region_size;
+} __aligned(__alignof(uint16_t /* First member's type, `uint16_t version'. */));
+
+typedef struct dlme_data_header_v1 struct_dlme_data_header;
+
+drtm_memory_region_descriptor_table_t *drtm_build_address_map(void);
+uint64_t drtm_get_address_map_size(void);
+
+/*
+ * Version-independent type.  May be used to avoid excessive line of code
+ * changes when migrating to new struct versions.
+ */
+typedef struct drtm_dl_args_v1 struct_drtm_dl_args;
+
+#endif /* DRTM_MAIN_H */

source/trusted-firmware/trusted-firmware-a-2.8/services/std_svc/drtm/drtm_measurements.c

@@ -0,0 +1,214 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ * DRTM measurements into TPM PCRs.
+ *
+ * Authors:
+ *      Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
+ *
+ */
+#include <assert.h>
+
+#include <common/debug.h>
+#include <drivers/auth/crypto_mod.h>
+#include <drivers/measured_boot/event_log/event_log.h>
+#include "drtm_main.h"
+#include "drtm_measurements.h"
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+/* Event Log buffer */
+static uint8_t drtm_event_log[PLAT_DRTM_EVENT_LOG_MAX_SIZE];
+
+/*
+ * Calculate and write hash of various payloads as per DRTM specification
+ * to Event Log.
+ *
+ * @param[in] data_base         Address of data
+ * @param[in] data_size         Size of data
+ * @param[in] event_type        Type of Event
+ * @param[in] event_name        Name of the Event
+ * @return:
+ *      0 = success
+ *    < 0 = error
+ */
+static int drtm_event_log_measure_and_record(uintptr_t data_base,
+					     uint32_t data_size,
+					     uint32_t event_type,
+					     const char *event_name,
+					     unsigned int pcr)
+{
+	int rc;
+	unsigned char hash_data[CRYPTO_MD_MAX_SIZE];
+	event_log_metadata_t metadata = {0};
+
+	metadata.name = event_name;
+	metadata.pcr = pcr;
+
+	/*
+	 * Measure the payloads requested by D-CRTM and DCE commponents
+	 * Hash algorithm decided by the Event Log driver at build-time
+	 */
+	rc = event_log_measure(data_base, data_size, hash_data);
+	if (rc != 0) {
+		return rc;
+	}
+
+	/* Record the mesasurement in the EventLog buffer */
+	event_log_record(hash_data, event_type, &metadata);
+
+	return 0;
+}
+
+/*
+ * Initialise Event Log global variables, used during the recording
+ * of various payload measurements into the Event Log buffer
+ *
+ * @param[in] event_log_start           Base address of Event Log buffer
+ * @param[in] event_log_finish          End address of Event Log buffer,
+ *                                      it is a first byte past end of the
+ *                                      buffer
+ */
+static void drtm_event_log_init(uint8_t *event_log_start,
+				uint8_t *event_log_finish)
+{
+	event_log_buf_init(event_log_start, event_log_finish);
+	event_log_write_specid_event();
+}
+
+enum drtm_retc drtm_take_measurements(const struct_drtm_dl_args *a)
+{
+	int rc;
+	uintptr_t dlme_img_mapping;
+	uint64_t dlme_img_ep;
+	size_t dlme_img_mapping_bytes;
+	uint8_t drtm_null_data = 0U;
+	uint8_t pcr_schema = DL_ARGS_GET_PCR_SCHEMA(a);
+	const char *drtm_event_arm_sep_data = "ARM_DRTM";
+
+	/* Initialise the EventLog driver */
+	drtm_event_log_init(drtm_event_log, drtm_event_log +
+			    sizeof(drtm_event_log));
+
+	/**
+	 * Measurements extended into PCR-17.
+	 *
+	 * PCR-17: Measure the DCE image.  Extend digest of (char)0 into PCR-17
+	 * since the D-CRTM and the DCE are not separate.
+	 */
+	rc = drtm_event_log_measure_and_record((uintptr_t)&drtm_null_data,
+					       sizeof(drtm_null_data),
+					       DRTM_EVENT_ARM_DCE, NULL,
+					       PCR_17);
+	CHECK_RC(rc, drtm_event_log_measure_and_record(DRTM_EVENT_ARM_DCE));
+
+	/* PCR-17: Measure the PCR schema DRTM launch argument. */
+	rc = drtm_event_log_measure_and_record((uintptr_t)&pcr_schema,
+					       sizeof(pcr_schema),
+					       DRTM_EVENT_ARM_PCR_SCHEMA,
+					       NULL, PCR_17);
+	CHECK_RC(rc,
+		 drtm_event_log_measure_and_record(DRTM_EVENT_ARM_PCR_SCHEMA));
+
+	/* PCR-17: Measure the enable state of external-debug, and trace. */
+	/*
+	 * TODO: Measure the enable state of external-debug and trace.  This should
+	 * be returned through a platform-specific hook.
+	 */
+
+	/* PCR-17: Measure the security lifecycle state. */
+	/*
+	 * TODO: Measure the security lifecycle state.  This is an implementation-
+	 * defined value, retrieved through an implementation-defined mechanisms.
+	 */
+
+	/*
+	 * PCR-17: Optionally measure the NWd DCE.
+	 * It is expected that such subsequent DCE stages are signed and verified.
+	 * Whether they are measured in addition to signing is implementation
+	 * -defined.
+	 * Here the choice is to not measure any NWd DCE, in favour of PCR value
+	 * resilience to any NWd DCE updates.
+	 */
+
+	/* PCR-17: End of DCE measurements. */
+	rc = drtm_event_log_measure_and_record((uintptr_t)drtm_event_arm_sep_data,
+					       strlen(drtm_event_arm_sep_data),
+					       DRTM_EVENT_ARM_SEPARATOR, NULL,
+					       PCR_17);
+	CHECK_RC(rc, drtm_event_log_measure_and_record(DRTM_EVENT_ARM_SEPARATOR));
+
+	/**
+	 * Measurements extended into PCR-18.
+	 *
+	 * PCR-18: Measure the PCR schema DRTM launch argument.
+	 */
+	rc = drtm_event_log_measure_and_record((uintptr_t)&pcr_schema,
+					       sizeof(pcr_schema),
+					       DRTM_EVENT_ARM_PCR_SCHEMA,
+					       NULL, PCR_18);
+	CHECK_RC(rc,
+		 drtm_event_log_measure_and_record(DRTM_EVENT_ARM_PCR_SCHEMA));
+
+	/*
+	 * PCR-18: Measure the public key used to verify DCE image(s) signatures.
+	 * Extend digest of (char)0, since we do not expect the NWd DCE to be
+	 * present.
+	 */
+	assert(a->dce_nwd_size == 0);
+	rc = drtm_event_log_measure_and_record((uintptr_t)&drtm_null_data,
+					       sizeof(drtm_null_data),
+					       DRTM_EVENT_ARM_DCE_PUBKEY,
+					       NULL, PCR_18);
+	CHECK_RC(rc,
+		 drtm_event_log_measure_and_record(DRTM_EVENT_ARM_DCE_PUBKEY));
+
+	/* PCR-18: Measure the DLME image. */
+	dlme_img_mapping_bytes = page_align(a->dlme_img_size, UP);
+	rc = mmap_add_dynamic_region_alloc_va(a->dlme_paddr + a->dlme_img_off,
+					      &dlme_img_mapping,
+					      dlme_img_mapping_bytes, MT_RO_DATA | MT_NS);
+	if (rc) {
+		WARN("DRTM: %s: mmap_add_dynamic_region() failed rc=%d\n",
+		     __func__, rc);
+		return INTERNAL_ERROR;
+	}
+
+	rc = drtm_event_log_measure_and_record(dlme_img_mapping, a->dlme_img_size,
+					       DRTM_EVENT_ARM_DLME, NULL,
+					       PCR_18);
+	CHECK_RC(rc, drtm_event_log_measure_and_record(DRTM_EVENT_ARM_DLME));
+
+	rc = mmap_remove_dynamic_region(dlme_img_mapping, dlme_img_mapping_bytes);
+	CHECK_RC(rc, mmap_remove_dynamic_region);
+
+	/* PCR-18: Measure the DLME image entry point. */
+	dlme_img_ep = DL_ARGS_GET_DLME_ENTRY_POINT(a);
+	drtm_event_log_measure_and_record((uintptr_t)&dlme_img_ep,
+					  sizeof(dlme_img_ep),
+					  DRTM_EVENT_ARM_DLME_EP, NULL,
+					  PCR_18);
+	CHECK_RC(rc, drtm_event_log_measure_and_record(DRTM_EVENT_ARM_DLME_EP));
+
+	/* PCR-18: End of DCE measurements. */
+	rc = drtm_event_log_measure_and_record((uintptr_t)drtm_event_arm_sep_data,
+					       strlen(drtm_event_arm_sep_data),
+					       DRTM_EVENT_ARM_SEPARATOR, NULL,
+					       PCR_18);
+	CHECK_RC(rc,
+		 drtm_event_log_measure_and_record(DRTM_EVENT_ARM_SEPARATOR));
+	/*
+	 * If the DCE is unable to log a measurement because there is no available
+	 * space in the event log region, the DCE must extend a hash of the value
+	 * 0xFF (1 byte in size) into PCR[17] and PCR[18] and enter remediation.
+	 */
+
+	return SUCCESS;
+}
+
+void drtm_serialise_event_log(uint8_t *dst, size_t *event_log_size_out)
+{
+	*event_log_size_out = event_log_get_cur_size(drtm_event_log);
+	memcpy(dst, drtm_event_log, *event_log_size_out);
+}

source/trusted-firmware/trusted-firmware-a-2.8/services/std_svc/drtm/drtm_measurements.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ */
+#ifndef DRTM_MEASUREMENTS_H
+#define DRTM_MEASUREMENTS_H
+
+#include <stdint.h>
+
+#include "drtm_main.h"
+#include <platform_def.h>
+
+#define DRTM_EVENT_ARM_BASE		0x9000U
+#define DRTM_EVENT_TYPE(n)		(DRTM_EVENT_ARM_BASE + (unsigned int)(n))
+
+#define DRTM_EVENT_ARM_PCR_SCHEMA	DRTM_EVENT_TYPE(1)
+#define DRTM_EVENT_ARM_DCE		DRTM_EVENT_TYPE(2)
+#define DRTM_EVENT_ARM_DCE_PUBKEY	DRTM_EVENT_TYPE(3)
+#define DRTM_EVENT_ARM_DLME		DRTM_EVENT_TYPE(4)
+#define DRTM_EVENT_ARM_DLME_EP		DRTM_EVENT_TYPE(5)
+#define DRTM_EVENT_ARM_DEBUG_CONFIG	DRTM_EVENT_TYPE(6)
+#define DRTM_EVENT_ARM_NONSECURE_CONFIG	DRTM_EVENT_TYPE(7)
+#define DRTM_EVENT_ARM_DCE_SECONDARY	DRTM_EVENT_TYPE(8)
+#define DRTM_EVENT_ARM_TZFW		DRTM_EVENT_TYPE(9)
+#define DRTM_EVENT_ARM_SEPARATOR	DRTM_EVENT_TYPE(10)
+
+#define CHECK_RC(rc, func_call) { \
+	if (rc != 0) { \
+		ERROR("%s(): " #func_call "failed unexpectedly rc=%d\n",  \
+		      __func__, rc);  \
+		panic();  \
+	}  \
+}
+
+enum drtm_retc drtm_take_measurements(const struct_drtm_dl_args *a);
+void drtm_serialise_event_log(uint8_t *dst, size_t *event_log_size_out);
+
+#endif /* DRTM_MEASUREMENTS_H */

source/trusted-firmware/trusted-firmware-a-2.8/services/std_svc/drtm/drtm_remediation.c

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ * DRTM support for DRTM error remediation.
+ *
+ */
+#include <inttypes.h>
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include "drtm_main.h"
+#include <plat/common/platform.h>
+
+uint64_t drtm_set_error(uint64_t x1, void *ctx)
+{
+	int rc;
+
+	rc = plat_set_drtm_error(x1);
+
+	if (rc != 0) {
+		SMC_RET1(ctx, INTERNAL_ERROR);
+	}
+
+	SMC_RET1(ctx, SUCCESS);
+}
+
+uint64_t drtm_get_error(void *ctx)
+{
+	uint64_t error_code;
+	int rc;
+
+	rc = plat_get_drtm_error(&error_code);
+
+	if (rc != 0) {
+		SMC_RET1(ctx, INTERNAL_ERROR);
+	}
+
+	SMC_RET2(ctx, SUCCESS, error_code);
+}
+
+void drtm_enter_remediation(uint64_t err_code, const char *err_str)
+{
+	int rc = plat_set_drtm_error(err_code);
+
+	if (rc != 0) {
+		ERROR("%s(): drtm_error_set() failed unexpectedly rc=%d\n",
+		      __func__, rc);
+		panic();
+	}
+
+	ERROR("DRTM: entering remediation of error:\n%" PRIu64 "\t\'%s\'\n",
+	       err_code, err_str);
+
+	ERROR("%s(): system reset is not yet supported\n", __func__);
+	plat_system_reset();
+}

source/trusted-firmware/trusted-firmware-a-2.8/services/std_svc/drtm/drtm_remediation.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ */
+#ifndef DRTM_REMEDIATION_H
+#define DRTM_REMEDIATION_H
+
+uint64_t drtm_set_error(uint64_t x1, void *ctx);
+uint64_t drtm_get_error(void *ctx);
+
+void drtm_enter_remediation(uint64_t error_code, const char *error_str);
+
+#endif /* DRTM_REMEDIATION_H */

source/trusted-firmware/trusted-firmware-a-2.8/services/std_svc/drtm/drtm_res_address_map.c

@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <plat/common/platform.h>
+#include <services/drtm_svc.h>
+#include <platform_def.h>
+
+/* Address map revision generated by this code. */
+#define DRTM_ADDRESS_MAP_REVISION	U(0x0001)
+
+/* Amount of space needed for address map based on PLAT_DRTM_MMAP_ENTRIES */
+#define DRTM_ADDRESS_MAP_SIZE (sizeof(drtm_memory_region_descriptor_table_t) + \
+			       (sizeof(drtm_mem_region_t) * \
+				PLAT_DRTM_MMAP_ENTRIES))
+
+/* Allocate space for DRTM-formatted address map to be constructed. */
+static uint8_t drtm_address_map[DRTM_ADDRESS_MAP_SIZE];
+
+static uint64_t drtm_address_map_size;
+
+drtm_memory_region_descriptor_table_t *drtm_build_address_map(void)
+{
+	/* Set up pointer to DRTM memory map. */
+	drtm_memory_region_descriptor_table_t *map =
+		(drtm_memory_region_descriptor_table_t *)drtm_address_map;
+
+	/* Get the platform memory map. */
+	const mmap_region_t *mmap = plat_get_addr_mmap();
+	unsigned int i;
+
+	/* Set up header for address map structure. */
+	map->revision = DRTM_ADDRESS_MAP_REVISION;
+	map->reserved = 0x0000;
+
+	/* Iterate through mmap and generate DRTM address map. */
+	for (i = 0U; mmap[i].base_pa != 0UL; i++) {
+		/* Set PA of region. */
+		map->region[i].region_address = mmap[i].base_pa;
+
+		/* Set size of region (in 4kb chunks). */
+		map->region[i].region_size_type = 0;
+		ARM_DRTM_REGION_SIZE_TYPE_SET_4K_PAGE_NUM(
+			map->region[i].region_size_type,
+			mmap[i].size / PAGE_SIZE_4KB);
+
+		/* Set type and cacheability. */
+		switch (MT_TYPE(mmap[i].attr)) {
+		case MT_DEVICE:
+			ARM_DRTM_REGION_SIZE_TYPE_SET_REGION_TYPE(
+				map->region[i].region_size_type,
+				ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_DEVICE);
+			break;
+		case MT_NON_CACHEABLE:
+			ARM_DRTM_REGION_SIZE_TYPE_SET_REGION_TYPE(
+				map->region[i].region_size_type,
+				ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NCAR);
+			ARM_DRTM_REGION_SIZE_TYPE_SET_CACHEABILITY(
+				map->region[i].region_size_type,
+				ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_NC);
+			break;
+		case MT_MEMORY:
+			ARM_DRTM_REGION_SIZE_TYPE_SET_REGION_TYPE(
+				map->region[i].region_size_type,
+				ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NORMAL);
+			break;
+		default:
+			return NULL;
+		}
+	}
+
+	map->num_regions = i;
+
+	/* Store total size of address map. */
+	drtm_address_map_size = sizeof(drtm_memory_region_descriptor_table_t);
+	drtm_address_map_size += (i * sizeof(drtm_mem_region_t));
+
+	return map;
+}
+
+uint64_t drtm_get_address_map_size(void)
+{
+	return drtm_address_map_size;
+}