GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <inttypes.h>
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#include <stdint.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <arch_features.h>
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#include <bl31/bl31.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <context.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/el3_runtime/pubsub.h>
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#include <lib/gpt_rme/gpt_rme.h>
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#include <lib/spinlock.h>
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#include <lib/utils.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/common_def.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include <services/rmmd_svc.h>
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#include <smccc_helpers.h>
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#include <lib/extensions/sve.h>
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#include "rmmd_initial_context.h"
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#include "rmmd_private.h"
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/*******************************************************************************
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* RMM boot failure flag
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******************************************************************************/
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static bool rmm_boot_failed;
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/*******************************************************************************
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* RMM context information.
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******************************************************************************/
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rmmd_rmm_context_t rmm_context[PLATFORM_CORE_COUNT];
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/*******************************************************************************
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* RMM entry point information. Discovered on the primary core and reused
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* on secondary cores.
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******************************************************************************/
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static entry_point_info_t *rmm_ep_info;
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/*******************************************************************************
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* Static function declaration.
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******************************************************************************/
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static int32_t rmm_init(void);
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/*******************************************************************************
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* This function takes an RMM context pointer and performs a synchronous entry
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* into it.
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******************************************************************************/
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uint64_t rmmd_rmm_sync_entry(rmmd_rmm_context_t *rmm_ctx)
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{
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uint64_t rc;
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assert(rmm_ctx != NULL);
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cm_set_context(&(rmm_ctx->cpu_ctx), REALM);
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/* Restore the realm context assigned above */
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cm_el1_sysregs_context_restore(REALM);
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cm_el2_sysregs_context_restore(REALM);
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cm_set_next_eret_context(REALM);
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/* Enter RMM */
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rc = rmmd_rmm_enter(&rmm_ctx->c_rt_ctx);
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/*
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* Save realm context. EL1 and EL2 Non-secure
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* contexts will be restored before exiting to
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* Non-secure world, therefore there is no need
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* to clear EL1 and EL2 context registers.
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*/
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cm_el1_sysregs_context_save(REALM);
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cm_el2_sysregs_context_save(REALM);
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return rc;
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}
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/*******************************************************************************
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* This function returns to the place where rmmd_rmm_sync_entry() was
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* called originally.
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******************************************************************************/
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__dead2 void rmmd_rmm_sync_exit(uint64_t rc)
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{
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rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()];
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/* Get context of the RMM in use by this CPU. */
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assert(cm_get_context(REALM) == &(ctx->cpu_ctx));
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/*
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* The RMMD must have initiated the original request through a
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* synchronous entry into RMM. Jump back to the original C runtime
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* context with the value of rc in x0;
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*/
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rmmd_rmm_exit(ctx->c_rt_ctx, rc);
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panic();
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}
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static void rmm_el2_context_init(el2_sysregs_t *regs)
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{
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regs->ctx_regs[CTX_SPSR_EL2 >> 3] = REALM_SPSR_EL2;
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regs->ctx_regs[CTX_SCTLR_EL2 >> 3] = SCTLR_EL2_RES1;
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}
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/*******************************************************************************
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* Enable architecture extensions on first entry to Realm world.
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******************************************************************************/
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static void manage_extensions_realm(cpu_context_t *ctx)
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{
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#if ENABLE_SVE_FOR_NS
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/*
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* Enable SVE and FPU in realm context when it is enabled for NS.
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* Realm manager must ensure that the SVE and FPU register
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* contexts are properly managed.
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*/
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sve_enable(ctx);
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#else
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/*
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* Disable SVE and FPU in realm context when it is disabled for NS.
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*/
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sve_disable(ctx);
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#endif /* ENABLE_SVE_FOR_NS */
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}
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/*******************************************************************************
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* Jump to the RMM for the first time.
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******************************************************************************/
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static int32_t rmm_init(void)
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{
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long rc;
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rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()];
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INFO("RMM init start.\n");
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/* Enable architecture extensions */
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manage_extensions_realm(&ctx->cpu_ctx);
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/* Initialize RMM EL2 context. */
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rmm_el2_context_init(&ctx->cpu_ctx.el2_sysregs_ctx);
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rc = rmmd_rmm_sync_entry(ctx);
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if (rc != E_RMM_BOOT_SUCCESS) {
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ERROR("RMM init failed: %ld\n", rc);
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/* Mark the boot as failed for all the CPUs */
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rmm_boot_failed = true;
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return 0;
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}
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INFO("RMM init end.\n");
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return 1;
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}
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/*******************************************************************************
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* Load and read RMM manifest, setup RMM.
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******************************************************************************/
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int rmmd_setup(void)
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{
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size_t shared_buf_size __unused;
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uintptr_t shared_buf_base;
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uint32_t ep_attr;
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unsigned int linear_id = plat_my_core_pos();
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rmmd_rmm_context_t *rmm_ctx = &rmm_context[linear_id];
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rmm_manifest_t *manifest;
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int rc;
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/* Make sure RME is supported. */
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assert(get_armv9_2_feat_rme_support() != 0U);
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rmm_ep_info = bl31_plat_get_next_image_ep_info(REALM);
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if (rmm_ep_info == NULL) {
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WARN("No RMM image provided by BL2 boot loader, Booting "
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"device without RMM initialization. SMCs destined for "
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"RMM will return SMC_UNK\n");
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return -ENOENT;
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}
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/* Under no circumstances will this parameter be 0 */
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assert(rmm_ep_info->pc == RMM_BASE);
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/* Initialise an entrypoint to set up the CPU context */
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ep_attr = EP_REALM;
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if ((read_sctlr_el3() & SCTLR_EE_BIT) != 0U) {
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ep_attr |= EP_EE_BIG;
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}
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SET_PARAM_HEAD(rmm_ep_info, PARAM_EP, VERSION_1, ep_attr);
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rmm_ep_info->spsr = SPSR_64(MODE_EL2,
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MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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shared_buf_size =
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plat_rmmd_get_el3_rmm_shared_mem(&shared_buf_base);
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assert((shared_buf_size == SZ_4K) &&
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((void *)shared_buf_base != NULL));
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/* Load the boot manifest at the beginning of the shared area */
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manifest = (rmm_manifest_t *)shared_buf_base;
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rc = plat_rmmd_load_manifest(manifest);
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if (rc != 0) {
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ERROR("Error loading RMM Boot Manifest (%i)\n", rc);
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return rc;
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}
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flush_dcache_range((uintptr_t)shared_buf_base, shared_buf_size);
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/*
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* Prepare coldboot arguments for RMM:
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* arg0: This CPUID (primary processor).
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* arg1: Version for this Boot Interface.
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* arg2: PLATFORM_CORE_COUNT.
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* arg3: Base address for the EL3 <-> RMM shared area. The boot
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* manifest will be stored at the beginning of this area.
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*/
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rmm_ep_info->args.arg0 = linear_id;
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rmm_ep_info->args.arg1 = RMM_EL3_INTERFACE_VERSION;
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rmm_ep_info->args.arg2 = PLATFORM_CORE_COUNT;
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rmm_ep_info->args.arg3 = shared_buf_base;
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/* Initialise RMM context with this entry point information */
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cm_setup_context(&rmm_ctx->cpu_ctx, rmm_ep_info);
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INFO("RMM setup done.\n");
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/* Register init function for deferred init. */
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bl31_register_rmm_init(&rmm_init);
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return 0;
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}
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/*******************************************************************************
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* Forward SMC to the other security state
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******************************************************************************/
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static uint64_t rmmd_smc_forward(uint32_t src_sec_state,
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uint32_t dst_sec_state, uint64_t x0,
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uint64_t x1, uint64_t x2, uint64_t x3,
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uint64_t x4, void *handle)
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{
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cpu_context_t *ctx = cm_get_context(dst_sec_state);
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/* Save incoming security state */
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cm_el1_sysregs_context_save(src_sec_state);
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cm_el2_sysregs_context_save(src_sec_state);
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/* Restore outgoing security state */
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cm_el1_sysregs_context_restore(dst_sec_state);
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cm_el2_sysregs_context_restore(dst_sec_state);
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cm_set_next_eret_context(dst_sec_state);
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/*
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* As per SMCCCv1.2, we need to preserve x4 to x7 unless
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* being used as return args. Hence we differentiate the
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* onward and backward path. Support upto 8 args in the
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* onward path and 4 args in return path.
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* Register x4 will be preserved by RMM in case it is not
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* used in return path.
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*/
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if (src_sec_state == NON_SECURE) {
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SMC_RET8(ctx, x0, x1, x2, x3, x4,
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SMC_GET_GP(handle, CTX_GPREG_X5),
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SMC_GET_GP(handle, CTX_GPREG_X6),
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SMC_GET_GP(handle, CTX_GPREG_X7));
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}
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SMC_RET5(ctx, x0, x1, x2, x3, x4);
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}
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/*******************************************************************************
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* This function handles all SMCs in the range reserved for RMI. Each call is
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* either forwarded to the other security state or handled by the RMM dispatcher
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******************************************************************************/
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uint64_t rmmd_rmi_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
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uint64_t x3, uint64_t x4, void *cookie,
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void *handle, uint64_t flags)
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{
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uint32_t src_sec_state;
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/* If RMM failed to boot, treat any RMI SMC as unknown */
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if (rmm_boot_failed) {
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WARN("RMMD: Failed to boot up RMM. Ignoring RMI call\n");
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SMC_RET1(handle, SMC_UNK);
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}
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/* Determine which security state this SMC originated from */
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src_sec_state = caller_sec_state(flags);
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/* RMI must not be invoked by the Secure world */
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if (src_sec_state == SMC_FROM_SECURE) {
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WARN("RMMD: RMI invoked by secure world.\n");
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SMC_RET1(handle, SMC_UNK);
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}
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/*
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* Forward an RMI call from the Normal world to the Realm world as it
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* is.
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*/
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if (src_sec_state == SMC_FROM_NON_SECURE) {
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VERBOSE("RMMD: RMI call from non-secure world.\n");
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return rmmd_smc_forward(NON_SECURE, REALM, smc_fid,
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x1, x2, x3, x4, handle);
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}
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if (src_sec_state != SMC_FROM_REALM) {
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SMC_RET1(handle, SMC_UNK);
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}
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switch (smc_fid) {
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case RMM_RMI_REQ_COMPLETE: {
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uint64_t x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
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return rmmd_smc_forward(REALM, NON_SECURE, x1,
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x2, x3, x4, x5, handle);
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}
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default:
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WARN("RMMD: Unsupported RMM call 0x%08x\n", smc_fid);
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SMC_RET1(handle, SMC_UNK);
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}
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}
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/*******************************************************************************
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* This cpu has been turned on. Enter RMM to initialise R-EL2. Entry into RMM
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* is done after initialising minimal architectural state that guarantees safe
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* execution.
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******************************************************************************/
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static void *rmmd_cpu_on_finish_handler(const void *arg)
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{
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long rc;
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uint32_t linear_id = plat_my_core_pos();
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rmmd_rmm_context_t *ctx = &rmm_context[linear_id];
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if (rmm_boot_failed) {
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/* RMM Boot failed on a previous CPU. Abort. */
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ERROR("RMM Failed to initialize. Ignoring for CPU%d\n",
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linear_id);
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return NULL;
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}
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/*
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* Prepare warmboot arguments for RMM:
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* arg0: This CPUID.
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* arg1 to arg3: Not used.
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*/
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rmm_ep_info->args.arg0 = linear_id;
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rmm_ep_info->args.arg1 = 0ULL;
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rmm_ep_info->args.arg2 = 0ULL;
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rmm_ep_info->args.arg3 = 0ULL;
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/* Initialise RMM context with this entry point information */
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cm_setup_context(&ctx->cpu_ctx, rmm_ep_info);
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/* Enable architecture extensions */
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manage_extensions_realm(&ctx->cpu_ctx);
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/* Initialize RMM EL2 context. */
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rmm_el2_context_init(&ctx->cpu_ctx.el2_sysregs_ctx);
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rc = rmmd_rmm_sync_entry(ctx);
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if (rc != E_RMM_BOOT_SUCCESS) {
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ERROR("RMM init failed on CPU%d: %ld\n", linear_id, rc);
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/* Mark the boot as failed for any other booting CPU */
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rmm_boot_failed = true;
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}
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return NULL;
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}
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/* Subscribe to PSCI CPU on to initialize RMM on secondary */
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SUBSCRIBE_TO_EVENT(psci_cpu_on_finish, rmmd_cpu_on_finish_handler);
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/* Convert GPT lib error to RMMD GTS error */
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static int gpt_to_gts_error(int error, uint32_t smc_fid, uint64_t address)
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{
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int ret;
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if (error == 0) {
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return E_RMM_OK;
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}
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if (error == -EINVAL) {
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ret = E_RMM_BAD_ADDR;
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} else {
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/* This is the only other error code we expect */
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assert(error == -EPERM);
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ret = E_RMM_BAD_PAS;
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}
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ERROR("RMMD: PAS Transition failed. GPT ret = %d, PA: 0x%"PRIx64 ", FID = 0x%x\n",
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error, address, smc_fid);
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return ret;
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}
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/*******************************************************************************
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* This function handles RMM-EL3 interface SMCs
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******************************************************************************/
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uint64_t rmmd_rmm_el3_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
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uint64_t x3, uint64_t x4, void *cookie,
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void *handle, uint64_t flags)
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{
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uint32_t src_sec_state;
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int ret;
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/* If RMM failed to boot, treat any RMM-EL3 interface SMC as unknown */
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if (rmm_boot_failed) {
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WARN("RMMD: Failed to boot up RMM. Ignoring RMM-EL3 call\n");
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SMC_RET1(handle, SMC_UNK);
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}
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/* Determine which security state this SMC originated from */
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src_sec_state = caller_sec_state(flags);
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if (src_sec_state != SMC_FROM_REALM) {
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WARN("RMMD: RMM-EL3 call originated from secure or normal world\n");
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SMC_RET1(handle, SMC_UNK);
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}
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switch (smc_fid) {
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case RMM_GTSI_DELEGATE:
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ret = gpt_delegate_pas(x1, PAGE_SIZE_4KB, SMC_FROM_REALM);
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SMC_RET1(handle, gpt_to_gts_error(ret, smc_fid, x1));
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case RMM_GTSI_UNDELEGATE:
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ret = gpt_undelegate_pas(x1, PAGE_SIZE_4KB, SMC_FROM_REALM);
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SMC_RET1(handle, gpt_to_gts_error(ret, smc_fid, x1));
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case RMM_ATTEST_GET_PLAT_TOKEN:
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ret = rmmd_attest_get_platform_token(x1, &x2, x3);
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SMC_RET2(handle, ret, x2);
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case RMM_ATTEST_GET_REALM_KEY:
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ret = rmmd_attest_get_signing_key(x1, &x2, x3);
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SMC_RET2(handle, ret, x2);
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case RMM_BOOT_COMPLETE:
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VERBOSE("RMMD: running rmmd_rmm_sync_exit\n");
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rmmd_rmm_sync_exit(x1);
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default:
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WARN("RMMD: Unsupported RMM-EL3 call 0x%08x\n", smc_fid);
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SMC_RET1(handle, SMC_UNK);
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}
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}
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