#ifndef __OS04A10_H__
#define __OS04A10_H__

#include "sns_comm.h"

#ifdef __cplusplus
extern "C" {
#endif

#ifdef FPGA
#define OS04A10_VMAX_4M_LINEAR 0xA58
#define OS04A10_VMAX_4M_WDR    0x958
#else
#define OS04A10_VMAX_4M_LINEAR 0x658
#define OS04A10_VMAX_4M_WDR    0x658
#endif

#define OS04A10_REG_ADDR_EXP_H   0x3501
#define OS04A10_REG_ADDR_EXP_L   0x3502
#define OS04A10_REG_ADDR_AGAIN_H 0x3508
#define OS04A10_REG_ADDR_AGAIN_L 0x3509
#define OS04A10_REG_ADDR_DGAIN_H 0x350a
#define OS04A10_REG_ADDR_DGAIN_M 0x350b
#define OS04A10_REG_ADDR_DGAIN_L 0x350c
#define OS04A10_REG_ADDR_HMAX_H  0x380C
#define OS04A10_REG_ADDR_HMAX_L  0x380D
#define OS04A10_REG_ADDR_VMAX_H  0x380E
#define OS04A10_REG_ADDR_VMAX_L  0x380F
#define OS04A10_REG_ADDR_DCG_SWITCH 0x376C
#define OS04A10_REG_ADDR_S_EXP_H 0x3541
#define OS04A10_REG_ADDR_S_EXP_L 0x3542
#define OS04A10_REG_ADDR_S_AGC_H 0x3548
#define OS04A10_REG_ADDR_S_AGC_L 0x3549
#define OS04A10_REG_ADDR_S_DGC_H 0x354A
#define OS04A10_REG_ADDR_S_DGC_M 0x354B
#define OS04A10_REG_ADDR_S_DGC_L 0x354C
#define OS04A10_REG_ADDR_GROUP1  0x320d
#define OS04A10_REG_ADDR_GROUP2  0x3208
#define OS04A10_REG_ADDR_GROUP3  0x3208
#define OS04A10_REG_ADDR_GROUP4  0x320d
#define OS04A10_REG_ADDR_GROUP5  0x320a
#define OS04A10_REG_ADDR_GROUP6  0x320e
#define OS04A10_EXP_OFFSET 8

typedef enum {
    OS04A10_REG_EXP_H = 0,
    OS04A10_REG_EXP_L,
    OS04A10_REG_DGC_H,
    OS04A10_REG_DGC_M,
    OS04A10_REG_DGC_L,
    OS04A10_REG_AGC_H,
    OS04A10_REG_AGC_L,
    OS04A10_REG_VMAX_H,
    OS04A10_REG_VMAX_L,
    OS04A10_REG_DCG_SWITCH,
    OS04A10_REG_L_MAX_NUM,

    // short frame reg info from here
    OS04A10_REG_S_EXP_H = OS04A10_REG_L_MAX_NUM,
    OS04A10_REG_S_EXP_L,
    OS04A10_REG_S_DGC_H,
    OS04A10_REG_S_DGC_M,
    OS04A10_REG_S_DGC_L,
    OS04A10_REG_S_AGC_H,
    OS04A10_REG_S_AGC_L,
    OS04A10_REG_MAX_NUM
} os04a10_reg_info;

#define OS04A10_FULL_LINES_MAX 0xBE50 // 1.0 fps

#ifdef __cplusplus
}
#endif

#endif // __OS04A10_H__