#ifndef H_DRV_PM_DDR_H
#define H_DRV_PM_DDR_H

#define HASH_SIZE_PER_BYTE			32
#define DDR_CALIB_SIZE				832
struct lpds_param {
	uint8_t lpds_hash[HASH_SIZE_PER_BYTE];
	uint8_t ddr_hash[HASH_SIZE_PER_BYTE];
	uint32_t data_start;
	uint32_t data_size;
	uint32_t hash_flag;
	uint32_t str_flag;
	uint32_t resume_addr;
	uint32_t resume_addr_backup;
	uint8_t reserve0[24];
	uint8_t scrambling_key[16];
	uint8_t ddr_calib[DDR_CALIB_SIZE];
	uint32_t ddr_size;
	uint32_t hpm_state;
	uint32_t power_state;
	uint8_t reserve1[20];
	uint32_t ddr_suspend_crc;
	uint32_t ddr_resume_crc;
};

struct ddr_calib_data {
	uint32_t calib_data_saved;

	uint32_t gate_dqs0_result;
	uint32_t gate_dqs1_result;

	uint32_t rx_dqs0_result;
	uint32_t rx_dqsb0_result;
	uint32_t rx_dqs1_result;
	uint32_t rx_dqsb1_result;

	uint32_t rx_dm0_result;
	uint32_t rx_dm1_result;

	uint32_t rx_dq_result[16];

	uint32_t tx_dqs0_result;
	uint32_t tx_dqsb0_result;
	uint32_t tx_dqs1_result;
	uint32_t tx_dqsb1_result;

	uint32_t tx_dm0_result;
	uint32_t tx_dm1_result;

	uint32_t tx_dq_result[16];
};

int pm_ddr_param_get(struct lpds_param *p_lpds_param);

#endif