#ifndef __SC485SL_H__ #define __SC485SL_H__ #include "sns_comm.h" #ifdef __cplusplus extern "C" { #endif #define SC485SL_REG_ADDR_EXP_HIGHER 0x3E20 #define SC485SL_REG_ADDR_EXP_H 0x3E00 #define SC485SL_REG_ADDR_EXP_M 0x3E01 #define SC485SL_REG_ADDR_EXP_L 0x3E02 #define SC485SL_REG_ADDR_DGAIN_H 0x3E06 #define SC485SL_REG_ADDR_DGAIN_L 0x3E07 #define SC485SL_REG_ADDR_AGAIN_H 0x3E08 #define SC485SL_REG_ADDR_AGAIN_L 0x3E09 #define SC485SL_REG_ADDR_VMAX_H 0x326D #define SC485SL_REG_ADDR_VMAX_M 0x320E #define SC485SL_REG_ADDR_VMAX_L 0x320F #define SC485SL_REG_ADDR_S_EXP_HIGHER 0x3E21 #define SC485SL_REG_ADDR_S_EXP_H 0x3E22 #define SC485SL_REG_ADDR_S_EXP_M 0x3E04 #define SC485SL_REG_ADDR_S_EXP_L 0x3E05 #define SC485SL_REG_ADDR_S_AGAIN_H 0x3E12 #define SC485SL_REG_ADDR_S_AGAIN_L 0x3E13 #define SC485SL_REG_ADDR_S_DGAIN_H 0x3E10 #define SC485SL_REG_ADDR_S_DGAIN_L 0x3E11 #define SC485SL_SEXP_MAX_ADDR_H 0x3E33 #define SC485SL_SEXP_MAX_ADDR_M 0x3E23 #define SC485SL_SEXP_MAX_ADDR_L 0x3E24 #define SC485SL_FRAME_RATE_MIN 0x3DB8 //Min:3fps #define EXP_OFFSET_LINEAR 8 #define EXP_OFFSET_WDR 13 #define SC485SL_EXP_MAX_DEFAULT 196 typedef enum { SC485SL_REG_EXP_HIGHER = 0, SC485SL_REG_EXP_H, SC485SL_REG_EXP_M, SC485SL_REG_EXP_L, SC485SL_REG_DGC_H, SC485SL_REG_DGC_L, SC485SL_REG_AGC_H, SC485SL_REG_AGC_L, SC485SL_REG_VMAX_HIGHER, SC485SL_REG_VMAX_H, SC485SL_REG_VMAX_L, SC485SL_REG_L_MAX_NUM, // short frame reg info from here SC485SL_REG_S_EXP_HIGHER = SC485SL_REG_L_MAX_NUM, SC485SL_REG_S_EXP_H, SC485SL_REG_S_EXP_M, SC485SL_REG_S_EXP_L, SC485SL_REG_S_DGAIN_H, SC485SL_REG_S_DGAIN_L, SC485SL_REG_S_AGAIN_H, SC485SL_REG_S_AGAIN_L, SC485SL_REG_S_EXP_MAX_H, SC485SL_REG_S_EXP_MAX_M, SC485SL_REG_S_EXP_MAX_L, SC485SL_REG_MAX_NUM } SC485SL_REG_info; #define SC485SL_VMAX_2688_1520_4LANE_LINEAR 0x62c #define SC485SL_VMAX_2560_1440_4LANE_LINEAR 0x640 #define SC485SL_VMAX_2560_1440_2LANE_LINEAR 0x708 #define SC485SL_VMAX_2560_1440_4LANE_WDR 0xc80 #define SC485SL_FULL_LINES_MAX 0xFFFFF #ifdef __cplusplus } #endif #endif // __SC485SL_H__