#ifndef H_PM_DDR_H
#define H_PM_DDR_H

#define HASH_SIZE_PER_BYTE			32
#define DDR_CALIB_SIZE				832

#define DDR_PARAM_UPDATE_CYCLE		(7 * 24 * 60 * 60)

struct lpds_param {
	xmedia_u8 lpds_hash[HASH_SIZE_PER_BYTE];
	xmedia_u8 ddr_hash[HASH_SIZE_PER_BYTE];
	xmedia_u32 data_start;
	xmedia_u32 data_size;
	xmedia_u32 hash_flag;
	xmedia_u32 str_flag;
	xmedia_u32 resume_addr;
	xmedia_u32 resume_addr_backup;
	xmedia_u8 reserve0[24];
	xmedia_u8 scrambling_key[16];
	xmedia_u8 ddr_calib[DDR_CALIB_SIZE];
	xmedia_u32 ddr_size;
	xmedia_u32 hpm_state;
	xmedia_u32 power_state;
	xmedia_u8 reserve1[20];
	xmedia_u32 ddr_suspend_crc;
	xmedia_u32 ddr_resume_crc;
};

struct ddr_calib_data {
	xmedia_u32 checksum;

	xmedia_u32 gate_dqs0_result;
	xmedia_u32 gate_dqs1_result;

	xmedia_u32 rx_dqs0_result;
	xmedia_u32 rx_dqsb0_result;
	xmedia_u32 rx_dqs1_result;
	xmedia_u32 rx_dqsb1_result;

	xmedia_u32 rx_dm0_result;
	xmedia_u32 rx_dm1_result;

	xmedia_u32 rx_dq_result[16];

	xmedia_u32 tx_dqs0_result;
	xmedia_u32 tx_dqsb0_result;
	xmedia_u32 tx_dqs1_result;
	xmedia_u32 tx_dqsb1_result;

	xmedia_u32 tx_dm0_result;
	xmedia_u32 tx_dm1_result;

	xmedia_u32 tx_dq_result[16];
	xmedia_u32 time_sec;
};

xmedia_bool is_ram_off_str(void);

xmedia_s32 ddr_param_check_and_save(void);

xmedia_s32 xmedia_pm_get_ddr_param(struct lpds_param *p_lpds_param);

#endif