678 lines
16 KiB
C
678 lines
16 KiB
C
/*
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* Copyright (c) LOTUS. All rights reserved.
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*/
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//#define DEBUG
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <wait_bit.h>
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#include <linux/io.h>
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#include <linux/mii.h>
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#include <linux/iopoll.h>
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#include <cpu_func.h>
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#include <miiphy.h>
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#include <hexdump.h>
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#include "ftgmac030.h"
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#include "marvell_phy.h"
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#include "realtek_phy.h"
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#include "sys.h"
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#define ETH_ZLEN 60
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/* Receive Buffer Size Register - HW default is 0x640 */
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#define FTGMAC030_RBSR_DEFAULT_VALUE 0x640
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/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
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#define FTGMAC030_PKTBUFSTX 4 /* must be power of 2 */
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#define FTGMAC030_PKTBUFSRX PKTBUFSRX /* must be power of 2 */
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/* Timeout for transmit */
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#define FTGMAC030_TX_TIMEOUT_MS 1000
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/* Timeout for a mdio read/write operation */
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#define FTGMAC030_MDIO_TIMEOUT_USEC 10000
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#define MAC_LEN 6
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struct ftgmac030_data {
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struct ftgmac030_txdes txdes[FTGMAC030_PKTBUFSTX] __attribute__((aligned(ARCH_DMA_MINALIGN)));
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struct ftgmac030_rxdes rxdes[FTGMAC030_PKTBUFSRX] __attribute__((aligned(ARCH_DMA_MINALIGN)));
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int rsvd1 __attribute__((aligned(ARCH_DMA_MINALIGN)));
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int tx_index;
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int rx_index;
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int phy_addr;
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enum ftgmac030_if_mode phy_intf;
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};
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/*
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* struct mdio functions
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*/
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int ftgmac030_mdio_read(struct eth_device *dev, int phy_addr,
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int regnum)
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{
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struct ftgmac030 *ftgmac030 = (struct ftgmac030 *)dev->iobase;
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int phycr;
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int data;
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int ret;
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phycr = readl(&ftgmac030->phycr);
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/* preserve MDC cycle threshold */
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phycr &= FTGMAC030_PHYCR_MDC_CYCTHR_MASK;
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phycr |= FTGMAC030_PHYCR_PHYAD(phy_addr)
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| FTGMAC030_PHYCR_REGAD(regnum)
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| FTGMAC030_PHYCR_OP(FTGMAC030_MDIO_OP_RD)
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| FTGMAC030_PHYCR_SOF(FTGMAC030_MDIO_SOF)
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| FTGMAC030_PHYCR_PHYRD;
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writel(phycr, &ftgmac030->phycr);
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ret = readl_poll_timeout(&ftgmac030->phycr, phycr,
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!(phycr & FTGMAC030_PHYCR_PHYRD),
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FTGMAC030_MDIO_TIMEOUT_USEC);
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if (ret) {
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pr_err("mdio read failed (phy:%d reg:%x)\n", phy_addr, regnum);
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return ret;
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}
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data = readl(&ftgmac030->phydata);
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return FTGMAC030_PHYDATA_MIIRDATA(data);
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}
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int ftgmac030_mdio_write(struct eth_device *dev, int phy_addr,
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int regnum, u16 value)
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{
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struct ftgmac030 *ftgmac030 = (struct ftgmac030 *)dev->iobase;
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int phycr;
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int data;
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int ret;
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phycr = readl(&ftgmac030->phycr);
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/* preserve MDC cycle threshold */
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phycr &= FTGMAC030_PHYCR_MDC_CYCTHR_MASK;
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phycr |= FTGMAC030_PHYCR_PHYAD(phy_addr)
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| FTGMAC030_PHYCR_REGAD(regnum)
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| FTGMAC030_PHYCR_OP(FTGMAC030_MDIO_OP_WR)
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| FTGMAC030_PHYCR_SOF(FTGMAC030_MDIO_SOF)
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| FTGMAC030_PHYCR_PHYWR;
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data = FTGMAC030_PHYDATA_MIIWDATA(value);
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writel(data, &ftgmac030->phydata);
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writel(phycr, &ftgmac030->phycr);
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ret = readl_poll_timeout(&ftgmac030->phycr, phycr,
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!(phycr & FTGMAC030_PHYCR_PHYWR),
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FTGMAC030_MDIO_TIMEOUT_USEC);
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if (ret) {
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pr_err("mdio write failed (phy:%d reg:%x)\n", phy_addr, regnum);
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}
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return ret;
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}
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/* MDIO Bus Interface */
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static int ftgmac030_mdiobus_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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struct eth_device *dev = (struct eth_device *)bus->priv;
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return ftgmac030_mdio_read(dev, addr, reg);
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}
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static int ftgmac030_mdiobus_write(struct mii_dev *bus, int addr, int devad,
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int reg, u16 value)
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{
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struct eth_device *dev = (struct eth_device *)bus->priv;
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return ftgmac030_mdio_write(dev, addr, reg, value);
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}
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/*
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* Init MIDO MDC CYCTHR
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*/
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static void ftgmac030_mdc_cycthr(struct eth_device *dev, unsigned int mdc_cycthr)
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{
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struct ftgmac030 *ftgmac030 = (struct ftgmac030 *)dev->iobase;
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int phycr;
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phycr = readl(&ftgmac030->phycr);
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phycr &= ~FTGMAC030_PHYCR_MDC_CYCTHR_MASK;
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phycr |= FTGMAC030_PHYCR_MDC_CYCTHR(mdc_cycthr);
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writel(phycr, &ftgmac030->phycr);
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}
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static void ftgmac030_set_phy_intf(struct eth_device *dev)
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{
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struct ftgmac030 *ftgmac030 = (struct ftgmac030 *)dev->iobase;
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struct ftgmac030_data *priv = dev->priv;
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priv->phy_intf = (bspeth_get_phy_intf() ? FTGMAC030_MODE_RGMII : FTGMAC030_MODE_RMII);
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printf("%s (%s)\n", __func__, (FTGMAC030_MODE_RMII == priv->phy_intf) ? "rmii" : "rgmii");
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writel(priv->phy_intf, &ftgmac030->gisr);
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/* set the mdc cycthr */
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/* set the mdc cycthr sys_clk=200M*/
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ftgmac030_mdc_cycthr(dev, 0xc8);
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}
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int ftgmac030_mdiobus_init(struct eth_device *dev)
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{
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate MDIO bus\n");
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return -ENOMEM;
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}
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bus->priv = dev;
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bus->read = ftgmac030_mdiobus_read;
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bus->write = ftgmac030_mdiobus_write;
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snprintf(bus->name, sizeof(bus->name), dev->name);
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if (mdio_register(bus)) {
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mdio_free(bus);
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return -1;
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}
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miiphy_set_current_dev(dev->name);
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#endif
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return 0;
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}
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static int ftgmac030_phy_reset(struct eth_device *dev)
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{
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struct ftgmac030_data *priv = dev->priv;
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int i;
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u16 status, adv;
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adv = ADVERTISE_CSMA | ADVERTISE_ALL;
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ftgmac030_mdio_write(dev, priv->phy_addr, MII_ADVERTISE, adv);
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printf("%s: Starting autonegotiation...\n", dev->name);
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ftgmac030_mdio_write(dev, priv->phy_addr,
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MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
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for (i = 0; i < 10000; i++) {
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status = ftgmac030_mdio_read(dev, priv->phy_addr, MII_BMSR);
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if (status & BMSR_ANEGCOMPLETE)
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break;
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mdelay(1);
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}
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if (status & BMSR_ANEGCOMPLETE) {
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printf("%s: Autonegotiation complete\n", dev->name);
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} else {
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printf("%s: Autonegotiation timed out (status=0x%04x)\n",
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dev->name, status);
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return 0;
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}
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return 1;
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}
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static int ftgmac030_phy_init(struct eth_device *dev)
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{
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struct ftgmac030_data *priv = dev->priv;
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int phy_addr;
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u16 phy_id, status, adv, lpa;
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u16 stat_ge;
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int media, speed, duplex;
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int i;
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/* Check if the PHY is up to snuff... */
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for (phy_addr = 0; phy_addr < 32; phy_addr++) {
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phy_id = ftgmac030_mdio_read(dev, phy_addr, MII_PHYSID1);
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/*
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* When it is unable to found PHY,
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* the interface usually return 0xffff or 0x0000
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*/
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if (phy_id != 0xffff && phy_id != 0x0) {
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printf("%s: found PHY(0x%x) at 0x%02x\n",
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dev->name, phy_id, phy_addr);
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priv->phy_addr = phy_addr;
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break;
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}
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}
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if (phy_id == 0xffff || phy_id == 0x0) {
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printf("%s: no PHY present\n", dev->name);
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return 0;
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}
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if (phy_id == PHY_MARVELL)
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marvell_phy_init(dev, phy_addr);
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if (phy_id == PHY_REALTEK)
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realtek_phy_init(dev, phy_addr);
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status = ftgmac030_mdio_read(dev, priv->phy_addr, MII_BMSR);
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if (!(status & BMSR_LSTATUS)) {
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/* Try to re-negotiate if we don't have link already. */
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ftgmac030_phy_reset(dev);
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for (i = 0; i < 100000 / 100; i++) {
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status = ftgmac030_mdio_read(dev, priv->phy_addr, MII_BMSR);
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if (status & BMSR_LSTATUS)
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break;
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udelay(100);
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}
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}
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if (!(status & BMSR_LSTATUS)) {
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printf("%s: link down\n", dev->name);
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return 0;
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}
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if (FTGMAC030_MODE_RGMII == priv->phy_intf) {
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/* 1000 Base-T Status Register */
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stat_ge = ftgmac030_mdio_read(dev, priv->phy_addr, MII_STAT1000);
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speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF)
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? 1 : 0);
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duplex = ((stat_ge & LPA_1000FULL)
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? 1 : 0);
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if (speed) { /* Speed is 1000 */
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printf("%s: link up, 1000bps %s-duplex\n",
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dev->name, duplex ? "full" : "half");
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return 1;
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}
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}
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adv = ftgmac030_mdio_read(dev, priv->phy_addr, MII_ADVERTISE);
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lpa = ftgmac030_mdio_read(dev, priv->phy_addr, MII_LPA);
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media = mii_nway_result(lpa & adv);
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speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0);
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duplex = (media & ADVERTISE_FULL) ? 1 : 0;
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printf("%s: link up, %sMbps %s-duplex\n",
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dev->name, speed ? "100" : "10", duplex ? "full" : "half");
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return 1;
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}
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static int ftgmac030_update_link_speed(struct eth_device *dev)
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{
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struct ftgmac030 *ftgmac030 = (struct ftgmac030 *)dev->iobase;
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struct ftgmac030_data *priv = dev->priv;
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unsigned short stat_fe;
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unsigned short stat_ge = 0 ;
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unsigned int maccr;
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if (FTGMAC030_MODE_RGMII == priv->phy_intf) {
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/* 1000 Base-T Status Register */
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stat_ge = ftgmac030_mdio_read(dev, priv->phy_addr, MII_STAT1000);
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}
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stat_fe = ftgmac030_mdio_read(dev, priv->phy_addr, MII_BMSR);
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if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */
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return 0;
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/* read MAC control register and clear related bits */
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maccr = readl(&ftgmac030->maccr) &
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~(FTGMAC030_MACCR_SPEED_1000 |
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FTGMAC030_MACCR_SPEED_100 |
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FTGMAC030_MACCR_FULLDUP);
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if (FTGMAC030_MODE_RGMII == priv->phy_intf) {
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if (stat_ge & LPA_1000FULL) {
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/* set gmac for 1000BaseTX and Full Duplex */
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maccr |= FTGMAC030_MACCR_SPEED_1000 | FTGMAC030_MACCR_FULLDUP;
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}
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if (stat_ge & LPA_1000HALF) {
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/* set gmac for 1000BaseTX and Half Duplex */
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maccr |= FTGMAC030_MACCR_SPEED_1000;
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}
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}
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if (!(maccr & FTGMAC030_MACCR_SPEED_1000)) {
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if (stat_fe & BMSR_100FULL) {
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/* set MII for 100BaseTX and Full Duplex */
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maccr |= FTGMAC030_MACCR_SPEED_100 | FTGMAC030_MACCR_FULLDUP;
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}
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if (stat_fe & BMSR_10FULL) {
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/* set MII for 10BaseT and Full Duplex */
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maccr |= FTGMAC030_MACCR_FULLDUP;
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}
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if (stat_fe & BMSR_100HALF) {
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/* set MII for 100BaseTX and Half Duplex */
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maccr |= FTGMAC030_MACCR_SPEED_100;
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}
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if (stat_fe & BMSR_10HALF) {
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/* set MII for 10BaseT and Half Duplex */
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/* we have already clear these bits, do nothing */
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;
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}
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}
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/* update MII config into maccr */
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writel(maccr, &ftgmac030->maccr);
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return 1;
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}
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/*
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* Reset MAC
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*/
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static void ftgmac030_reset(struct eth_device *dev)
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{
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struct ftgmac030 *ftgmac030 = (struct ftgmac030 *)dev->iobase;
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debug("%s()\n", __func__);
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writel(FTGMAC030_MACCR_SW_RST, &ftgmac030->maccr);
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while (readl(&ftgmac030->maccr) & FTGMAC030_MACCR_SW_RST)
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;
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}
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/*
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* Set MAC address
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*/
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static void ftgmac030_set_mac(struct eth_device *dev,
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const unsigned char *mac)
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{
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struct ftgmac030 *ftgmac030 = (struct ftgmac030 *)dev->iobase;
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unsigned int maddr = mac[0] << 8 | mac[1];
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unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
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debug("%s(%x %x)\n", __func__, maddr, laddr);
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writel(maddr, &ftgmac030->mac_madr);
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writel(laddr, &ftgmac030->mac_ladr);
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}
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static void ftgmac030_set_mac_from_env(struct eth_device *dev)
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{
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unsigned char mac[MAC_LEN];
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memset(mac, 0, sizeof(mac));
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if (!eth_env_get_enetaddr("ethaddr", mac)) {
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printf("MAC address invalid!\n");
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#ifdef CONFIG_NET_RANDOM_ETHADDR
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net_random_ethaddr(mac);
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printf("Set Random MAC address!\n");
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eth_env_set_enetaddr("ethaddr", mac);
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#endif
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}
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memcpy(dev->enetaddr, mac, MAC_LEN);
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ftgmac030_set_mac(dev, dev->enetaddr);
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}
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/*
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* disable transmitter, receiver
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*/
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static void ftgmac030_halt(struct eth_device *dev)
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{
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struct ftgmac030 *ftgmac030 = (struct ftgmac030 *)dev->iobase;
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debug("%s()\n", __func__);
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writel(0, &ftgmac030->maccr);
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bspeth_sys_exit();
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}
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static int ftgmac030_init(struct eth_device *dev, bd_t *bd)
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{
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struct ftgmac030 *ftgmac030 = (struct ftgmac030 *)dev->iobase;
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struct ftgmac030_data *priv = dev->priv;
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unsigned int maccr;
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ulong start, end;
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int i;
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debug("%s()\n", __func__);
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/* sys-func-sel */
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bspeth_sys_init();
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ftgmac030_reset(dev);
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/* set the MII interface */
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ftgmac030_set_phy_intf(dev);
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/* set the ethernet address */
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ftgmac030_set_mac_from_env(dev);
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/* disable all interrupts */
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writel(0, &ftgmac030->ier);
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/* initialize descriptors */
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priv->tx_index = 0;
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priv->rx_index = 0;
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for (i = 0; i < FTGMAC030_PKTBUFSTX; i++) {
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/* TXBUF_BADR */
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priv->txdes[i].txdes3 = 0;
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priv->txdes[i].txdes0 = 0;
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}
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priv->txdes[FTGMAC030_PKTBUFSTX - 1].txdes0 = FTGMAC030_TXDES0_EDOTR;
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start = ((ulong)&priv->txdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
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end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
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flush_dcache_range(start, end);
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for (i = 0; i < FTGMAC030_PKTBUFSRX; i++) {
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/* RXBUF_BADR */
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priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
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priv->rxdes[i].rxdes0 = 0;
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}
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priv->rxdes[FTGMAC030_PKTBUFSRX - 1].rxdes0 = FTGMAC030_RXDES0_EDORR;
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start = ((ulong)&priv->rxdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
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end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
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flush_dcache_range(start, end);
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/* transmit ring */
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writel((unsigned int)priv->txdes, &ftgmac030->nptxdesc_addr);
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/* receive ring */
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writel((unsigned int)priv->rxdes, &ftgmac030->rxdesc_addr);
|
|
|
|
/* poll receive descriptor automatically */
|
|
writel(FTGMAC030_APTC_DEFAULT, &ftgmac030->aptc);
|
|
|
|
/* config receive buffer size register */
|
|
writel(FTGMAC030_RBSR_RXBUF_SIZE(FTGMAC030_RBSR_DEFAULT_VALUE), &ftgmac030->rbsr);
|
|
|
|
/* enable transmitter, receiver */
|
|
maccr = FTGMAC030_MACCR_DEFAULT;
|
|
writel(maccr, &ftgmac030->maccr);
|
|
|
|
if (ftgmac030_phy_init(dev)) {
|
|
if (!ftgmac030_update_link_speed(dev))
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Get a data block via Ethernet
|
|
*/
|
|
static int ftgmac030_recv(struct eth_device *dev)
|
|
{
|
|
struct ftgmac030_data *priv = dev->priv;
|
|
struct ftgmac030_rxdes *curr_des = &priv->rxdes[priv->rx_index];
|
|
unsigned short rxlen;
|
|
ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
|
|
ulong des_end = des_start +
|
|
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
|
|
ulong data_start = curr_des->rxdes3;
|
|
ulong data_end;
|
|
|
|
invalidate_dcache_range(des_start, des_end);
|
|
|
|
if (!(curr_des->rxdes0 & FTGMAC030_RXDES0_RXPKT_RDY))
|
|
return -EAGAIN;
|
|
|
|
if (curr_des->rxdes0 & (FTGMAC030_RXDES0_RX_ERR |
|
|
FTGMAC030_RXDES0_CRC_ERR |
|
|
FTGMAC030_RXDES0_FTL |
|
|
FTGMAC030_RXDES0_RUNT |
|
|
FTGMAC030_RXDES0_RX_ODD_NB)) {
|
|
return -EAGAIN;
|
|
}
|
|
|
|
rxlen = FTGMAC030_RXDES0_VDBC(curr_des->rxdes0);
|
|
|
|
debug("%s(): RX buffer %d, %x received\n",
|
|
__func__, priv->rx_index, rxlen);
|
|
|
|
/* Invalidate received data */
|
|
data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN);
|
|
invalidate_dcache_range(data_start, data_end);
|
|
|
|
/* pass the packet up to the protocol layers. */
|
|
net_process_received_packet((void *)curr_des->rxdes3, rxlen);
|
|
|
|
/* Release buffer to DMA and flush descriptor */
|
|
curr_des->rxdes0 &= FTGMAC030_RXDES0_EDORR;
|
|
curr_des->rxdes1 = 0x0;
|
|
flush_dcache_range(des_start, des_end);
|
|
|
|
/* Move to next descriptor */
|
|
priv->rx_index = (priv->rx_index + 1) % FTGMAC030_PKTBUFSRX;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static u32 ftgmac030_read_txdesc(const void *desc)
|
|
{
|
|
const struct ftgmac030_txdes *txdes = desc;
|
|
ulong des_start = ((ulong)txdes) & ~(ARCH_DMA_MINALIGN - 1);
|
|
ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN);
|
|
|
|
invalidate_dcache_range(des_start, des_end);
|
|
|
|
return txdes->txdes0;
|
|
}
|
|
|
|
BUILD_WAIT_FOR_BIT(ftgmac030_txdone, u32, ftgmac030_read_txdesc)
|
|
|
|
/*
|
|
* Send a data block via Ethernet
|
|
*/
|
|
static int ftgmac030_send(struct eth_device *dev, void *packet, int length)
|
|
{
|
|
struct ftgmac030_data *priv = dev->priv;
|
|
struct ftgmac030 *ftgmac030 = (struct ftgmac030 *)dev->iobase;
|
|
struct ftgmac030_txdes *curr_des = &priv->txdes[priv->tx_index];
|
|
ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
|
|
ulong des_end = des_start +
|
|
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
|
|
ulong data_start;
|
|
ulong data_end;
|
|
int rc;
|
|
|
|
invalidate_dcache_range(des_start, des_end);
|
|
|
|
if (curr_des->txdes0 & FTGMAC030_TXDES0_TXDMA_OWN) {
|
|
debug("%s(): no TX descriptor available\n", __func__);
|
|
return -1;
|
|
}
|
|
|
|
debug("%s(%x, %x)\n", __func__, (int)packet, length);
|
|
|
|
length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
|
|
|
|
/* initiate a transmit sequence */
|
|
curr_des->txdes3 = (unsigned int)packet; /* TXBUF_BADR */
|
|
|
|
/* Flush data to be sent */
|
|
data_start = curr_des->txdes3;
|
|
data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
|
|
flush_dcache_range(data_start, data_end);
|
|
|
|
/* only one descriptor on TXBUF */
|
|
curr_des->txdes0 &= FTGMAC030_TXDES0_EDOTR;
|
|
curr_des->txdes0 |= FTGMAC030_TXDES0_FTS |
|
|
FTGMAC030_TXDES0_LTS |
|
|
FTGMAC030_TXDES0_BUF_SIZE(length) |
|
|
FTGMAC030_TXDES0_TXDMA_OWN ;
|
|
|
|
/* Flush modified buffer descriptor */
|
|
flush_dcache_range(des_start, des_end);
|
|
|
|
/* start transmit */
|
|
writel(1, &ftgmac030->nptxpd);
|
|
|
|
/* wait for transfer to succeed */
|
|
rc = wait_for_bit_ftgmac030_txdone(curr_des,
|
|
FTGMAC030_TXDES0_TXDMA_OWN, false,
|
|
FTGMAC030_TX_TIMEOUT_MS, true);
|
|
if (rc)
|
|
return rc;
|
|
|
|
debug("%s(): packet sent\n", __func__);
|
|
|
|
/* Move to next descriptor */
|
|
priv->tx_index = (priv->tx_index + 1) % FTGMAC030_PKTBUFSTX;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ftgmac030_initialize(bd_t *bd)
|
|
{
|
|
struct eth_device *dev;
|
|
struct ftgmac030_data *priv;
|
|
|
|
dev = malloc(sizeof *dev);
|
|
if (!dev) {
|
|
printf("%s(): failed to allocate dev\n", __func__);
|
|
goto out;
|
|
}
|
|
|
|
/* Transmit and receive descriptors should align to 16 bytes */
|
|
priv = memalign(ARCH_DMA_MINALIGN, sizeof(struct ftgmac030_data));
|
|
if (!priv) {
|
|
printf("%s(): failed to allocate priv\n", __func__);
|
|
goto free_dev;
|
|
}
|
|
|
|
memset(dev, 0, sizeof(*dev));
|
|
memset(priv, 0, sizeof(*priv));
|
|
|
|
sprintf(dev->name, "FTGMAC030");
|
|
dev->iobase = GMAC_REG_BASE;
|
|
dev->init = ftgmac030_init;
|
|
dev->halt = ftgmac030_halt;
|
|
dev->send = ftgmac030_send;
|
|
dev->recv = ftgmac030_recv;
|
|
dev->priv = priv;
|
|
|
|
ftgmac030_mdiobus_init(dev);
|
|
|
|
eth_register(dev);
|
|
|
|
return 1;
|
|
|
|
free_dev:
|
|
free(dev);
|
|
out:
|
|
return 0;
|
|
}
|