460 lines
17 KiB
C
460 lines
17 KiB
C
/*
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* Copyright (c) LOTUS. All rights reserved.
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*/
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#ifndef __FTGMAC030_H
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#define __FTGMAC030_H
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/* The registers offset table of ftgmac030 */
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struct ftgmac030 {
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volatile unsigned int isr; /* 0x00 */
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volatile unsigned int ier; /* 0x04 */
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volatile unsigned int mac_madr; /* 0x08 */
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volatile unsigned int mac_ladr; /* 0x0C */
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volatile unsigned int maht0; /* 0x10 */
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volatile unsigned int maht1; /* 0x14 */
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volatile unsigned int nptxpd; /* 0x18 */
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volatile unsigned int rxpd; /*0x1C */
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volatile unsigned int nptxdesc_addr; /* 0x20 */
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volatile unsigned int rxdesc_addr; /* 0x24 */
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volatile unsigned int hptxpd; /* 0x28 */
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volatile unsigned int hptxdesc_addr; /*0x2C */
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volatile unsigned int txitc; /* 0x30 */
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volatile unsigned int rxitc; /* 0x34 */
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volatile unsigned int aptc; /* 0x38 */
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volatile unsigned int dblac; /* 0x3C */
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volatile unsigned int dmafifos; /* 0x40 */
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volatile unsigned int rsvd1; /* 0x44 */
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volatile unsigned int tfafcr; /* 0x48 */
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volatile unsigned int rbsr; /* 0x4C */
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volatile unsigned int maccr; /* 0x50 */
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volatile unsigned int macsr; /* 0x54 */
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volatile unsigned int tm; /* 0x58 */
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volatile unsigned int rsvd2; /* 0x5C */
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volatile unsigned int phycr; /* 0x60 */
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volatile unsigned int phydata;/* 0x64 */
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volatile unsigned int flow_cntrl; /* 0x68 */
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volatile unsigned int back_pressure; /* 0x6C */
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volatile unsigned int wakeOnLan_cntrl; /* 0x70 */
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volatile unsigned int wakeOnLan_sts; /* 0x74 */
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volatile unsigned int wfc_crc; /* 0x78 */
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volatile unsigned int rsvd3; /* 0x7C */
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volatile unsigned int wfbm1; /* 0x80 */
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volatile unsigned int wfbm2; /* 0x84 */
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volatile unsigned int wfbm3; /* 0x88 */
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volatile unsigned int wfbm4; /* 0x8C */
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volatile unsigned int nptxr_ptr; /* 0x90 */
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volatile unsigned int hptxr_prt; /* 0x94 */
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volatile unsigned int rxr_ptr; /* 0x98 */
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volatile unsigned int rsvd4; /* 0x9C */
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volatile unsigned int tpkt_cnt; /* 0xA0 */
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volatile unsigned int tx_m_s_col; /* 0xA4 */
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volatile unsigned int tx_e_f_cnt; /* 0xA8 */
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volatile unsigned int tx_l_u_cnt; /* 0xAC */
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volatile unsigned int rpkt_cnt; /* 0xB0 */
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volatile unsigned int bropkt_cnt; /* 0xB4 */
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volatile unsigned int mulpkt_cnt; /* 0xB8 */
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volatile unsigned int rpf_aep_cnt; /* 0xBC */
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volatile unsigned int runt; /* 0xC0 */
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volatile unsigned int crcer_ftl_cnt; /* 0xC4 */
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volatile unsigned int rcol_rlost_cnt; /* 0xC8 */
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volatile unsigned int bistr; /* 0xCC */
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volatile unsigned int bmrcr; /* 0xD0 */
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volatile unsigned int rsvd5[4]; /* 0xD4 ~ 0xE3 */
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volatile unsigned int acir; /* 0xE4 AXI additional Control Information */
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volatile unsigned int gisr; /* 0xE8 GMAC Interface Selection */
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volatile unsigned int rsvd6;/* 0xEC */
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volatile unsigned int eee; /* 0xF0 */
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volatile unsigned int revr; /* 0xF4 */
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volatile unsigned int fear; /* 0xF8 */
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volatile unsigned int rsvd7[1]; /* 0xFC */
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volatile unsigned int ptp_rx_addr; /* 0x100 PTP Destination Unicast IP Address on Rx path */
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volatile unsigned int ptp_tx_addr; /* 0x104 PTP Destination Unicast IP Address on Tx path */
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volatile unsigned int rsvd8[2]; /* 0x108 ~ 0x10C*/
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volatile unsigned int ptp_tx_sec; /* 0x110 PTP TX Event Frame Time-stamp for seconds */
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volatile unsigned int ptp_tx_nsec; /* 0x114 PTP TX Event Frame Time-stamp for nanoseconds */
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volatile unsigned int ptp_rx_sec; /* 0x118 PTP RX Event Frame Time-stamp for seconds */
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volatile unsigned int ptp_rx_nsec; /* 0x11C PTP RX Event Frame Time-stamp for nanoseconds */
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volatile unsigned int ptp_tx_p_sec; /* 0x120 PTP TX Peer Frame Time-stamp for seconds */
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volatile unsigned int ptp_tx_p_nsec; /* 0x124 PTP TX Peer Frame Time-stamp for nanoseconds */
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volatile unsigned int ptp_rx_p_sec; /* 0x128 PTP RX Peer Frame Time-stamp for seconds */
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volatile unsigned int ptp_rx_p_nsec; /* 0x12C PTP RX Peer Frame Time-stamp for nanoseconds */
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volatile unsigned int ptp_nnsec_tmr; /* 0x130 PTP Timer Nano-nansecond */
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volatile unsigned int ptp_nsec_tmr; /* 0x134 PTP Timer nanosecond */
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volatile unsigned int ptp_sec_tmr; /* 0x138 PTP Second */
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volatile unsigned int ptp_ns_period; /* 0x13C PTP period increment, max is 255 ns */
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volatile unsigned int ptp_nns_period; /* 0x140 PTP period increment, max is 0.999999999 ns */
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volatile unsigned int ptp_offset; /* 0x144 PTP period offset increment */
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volatile unsigned int ptp_tmr_adj; /* 0x148 PTP Timer Adjustment */
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};
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/*
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* Interrupt Status Register 0x00 and 0x04
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*/
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#define FTGMAC030_INT_PDELAY_RESP_OUT (1 << 24)
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#define FTGMAC030_INT_PDELAY_RESP_IN (1 << 23)
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#define FTGMAC030_INT_PDELAY_REQ_OUT (1 << 22)
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#define FTGMAC030_INT_PDELAY_REQ_IN (1 << 21)
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#define FTGMAC030_INT_DELAY_REQ_OUT (1 << 20)
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#define FTGMAC030_INT_DELAY_REQ_IN (1 << 19)
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#define FTGMAC030_INT_SYNC_OUT (1 << 18)
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#define FTGMAC030_INT_SYNC_IN (1 << 17)
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#define FTGMAC030_INT_TSU_SEC_INC (1 << 16)
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#define FTGMAC030_INT_RX_LPI_IN (1 << 12)
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#define FTGMAC030_INT_RX_LPI_EXIT (1 << 11)
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#define FTGMAC030_INT_HPTXBUF_UNAVA (1 << 10)
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#define FTGMAC030_INT_PHYSTS_CHG (1 << 9)
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#define FTGMAC030_INT_AHB_ERR (1 << 8)
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#define FTGMAC030_INT_TPKT_LOST (1 << 7)
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#define FTGMAC030_INT_NPTXBUF_UNAVA (1 << 6)
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#define FTGMAC030_INT_TPKT2F (1 << 5)
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#define FTGMAC030_INT_TPKT2E (1 << 4)
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#define FTGMAC030_INT_RPKT_LOST (1 << 3)
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#define FTGMAC030_INT_RXBUF_UNAVA (1 << 2)
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#define FTGMAC030_INT_RPKT2F (1 << 1)
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#define FTGMAC030_INT_RPKT2B (1 << 0)
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#define FTGMAC030_INT_DEFAULT ( \
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FTGMAC030_INT_RPKT2B | \
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FTGMAC030_INT_RXBUF_UNAVA | \
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FTGMAC030_INT_RPKT_LOST | \
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FTGMAC030_INT_TPKT2E | \
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FTGMAC030_INT_TPKT2F | \
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FTGMAC030_INT_TPKT_LOST | \
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FTGMAC030_INT_AHB_ERR | \
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FTGMAC030_INT_PHYSTS_CHG \
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)
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#define FTGMAC030_INT_ALL ( \
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FTGMAC030_INT_RPKT2B | \
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FTGMAC030_INT_RPKT2F | \
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FTGMAC030_INT_RXBUF_UNAVA | \
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FTGMAC030_INT_RPKT_LOST | \
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FTGMAC030_INT_TPKT2E | \
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FTGMAC030_INT_TPKT2F | \
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FTGMAC030_INT_NPTXBUF_UNAVA | \
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FTGMAC030_INT_TPKT_LOST | \
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FTGMAC030_INT_AHB_ERR | \
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FTGMAC030_INT_PHYSTS_CHG | \
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FTGMAC030_INT_HPTXBUF_UNAVA \
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)
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/*
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* MAC Most Significant Address Register 0x08
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*/
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#define FTGMAC030_MADR(x) ((x & 0xffff) << 0)
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/*
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* MAC Least Siginificant Address Register 0x0C
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*/
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#define FTGMAC030_LADR(x) ((x & 0xffffffff) << 0)
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/*
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* TX Interrupt Timer Control Register 0x30
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*/
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#define FTGMAC030_TXITC_TIME_SEL (1 << 16)
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#define FTGMAC030_TXITC_CYL(x) ((x & 0xff) << 8)
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#define FTGMAC030_TXITC_THR(x) ((x & 0x7) << 4)
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#define FTGMAC030_TXITC_THR_UNIT(x) ((x & 0x3) << 0)
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#define FTGMAC030_TXITC_DEFAULT FTGMAC030_TXITC_THR(1)
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/*
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* RX Interrupt Timer Control Register 0x34
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*/
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#define FTGMAC030_RXITC_RST(x) ((x & 0xff) << 16)
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#define FTGMAC030_RXITC_TIME_SEL (1 << 16)
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#define FTGMAC030_RXITC_CYL(x) ((x & 0xff) << 8)
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#define FTGMAC030_RXITC_THR(x) ((x & 0x7) << 4)
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#define FTGMAC030_RXITC_THR_UNIT(x) ((x & 0x3) << 0)
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#define FTGMAC030_RXITC_DEFAULT FTGMAC030_RXITC_THR(1)
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/*
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* Automatic Polling Timer Control Register 0x34
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*/
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#define FTGMAC030_APTC_TX_TIME (1 << 12)
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#define FTGMAC030_APTC_TX_CNT(x) ((x & 0xf) << 8)
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#define FTGMAC030_APTC_RX_TIME (1 << 4)
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#define FTGMAC030_APTC_RX_CNT(x) ((x & 0xf) << 0)
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#define FTGMAC030_APTC_DEFAULT FTGMAC030_APTC_RX_CNT(1)
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/*
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* DMA Burst Length and Arbitration Control Register 0x38
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*/
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#define FTGMAC030_DBLAC_IFG_INC (1 << 23)
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#define FTGMAC030_DBLAC_IFG_CNT(x) ((x & 0x7) << 20)
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#define FTGMAC030_DBLAC_TXDES_SIZE(x) ((x & 0xf) << 16)
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#define FTGMAC030_DBLAC_RXDES_SIZE(x) ((x & 0xf) << 12)
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#define FTGMAC030_DBLAC_TXBST_SIZE(x) ((x & 0x3) << 10)
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#define FTGMAC030_DBLAC_RXBST_SIZE(x) ((x & 0x3) << 8)
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#define FTGMAC030_DBLAC_RX_THR_EN (1 << 6)
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#define FTGMAC030_DBLAC_RXFIFO_HTHR(x) ((x & 0x7) << 3)
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#define FTGMAC030_DBLAC_RXFIFO_LTHR(x) ((x & 0x7) << 0)
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#define FTGMAC030_DBLAC_DEFAULT FTGMAC030_DBLAC_RXFIFO_LTHR(2) | \
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FTGMAC030_DBLAC_RXFIFO_HTHR(6) | \
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FTGMAC030_DBLAC_RX_THR_EN | \
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FTGMAC030_DBLAC_RXBST_SIZE(3) | \
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FTGMAC030_DBLAC_TXBST_SIZE(3)
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/*
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* DMA/FIFO State Register 0x3c
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*/
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#define FTGMAC030_DMAFIFOS_TXD_REQ (1 << 31)
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#define FTGMAC030_DMAFIFOS_RXD_REQ (1 << 30)
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#define FTGMAC030_DMAFIFOS_DARB_TXGNT (1 << 29)
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#define FTGMAC030_DMAFIFOS_DARB_RXGNT (1 << 28)
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#define FTGMAC030_DMAFIFOS_TXFIFO_EMPTY (1 << 27)
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#define FTGMAC030_DMAFIFOS_RXFIFO_EMPTY (1 << 26)
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#define FTGMAC030_DMAFIFOS_TXDMA3_SM(x) ((x & 0xf) << 18)
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#define FTGMAC030_DMAFIFOS_TXDMA2_SM(x) ((x & 0xf) << 16)
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#define FTGMAC030_DMAFIFOS_TXDMA1_SM(x) ((x & 0xf) << 12)
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#define FTGMAC030_DMAFIFOS_RXDMA3_SM(x) ((x & 0xf) << 8)
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#define FTGMAC030_DMAFIFOS_RXDMA2_SM(x) ((x & 0xf) << 4)
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#define FTGMAC030_DMAFIFOS_RXDMA1_SM(x) ((x & 0xf) << 0)
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/*
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* Revision Register 0x40
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*/
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#define FTGMAC030_REV_B1(x) ((x >> 16) & 0xff)
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#define FTGMAC030_REV_B2(x) ((x >> 8) & 0xff)
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#define FTGMAC030_REV_B3(x) (x & 0xff)
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/*
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* Feature Register 0xF8
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*/
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#define FTGMAC030_FEAR_TFIFO_RSIZE(x) ((x & 0x7) >> 4)
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#define FTGMAC030_FEAR_RFIFO_RSIZE(x) ((x & 0x7) >> 0)
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/*
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* Transmit Priority Arbitration and FIFO Control Register 0x48
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*/
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#define FTGMAC030_TPAFCR_TFIFO_SIZE(x) ((x & 0x7) << 27)
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#define FTGMAC030_TPAFCR_RFIFO_SIZE(x) ((x & 0x7) << 24)
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#define FTGMAC030_TPAFCR_EARLY_TXTHR(x) ((x & 0xff) << 16)
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#define FTGMAC030_TPAFCR_EARLY_RXTHR(x) ((x & 0xff) << 8)
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#define FTGMAC030_TPAFCR_HPKT_THR(x) ((x & 0xf) << 4)
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#define FTGMAC030_TPAFCR_NPKT_THR(x) ((x & 0xf) << 0)
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/*
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* Receive Buffer Size Register 0x4c
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*/
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#define FTGMAC030_RBSR_RXBUF_SIZE(x) ((x & 0x3fff) << 0)
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/*
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* MAC Control Register 0x50
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*/
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#define FTGMAC030_MACCR_SW_RST (1 << 31)
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#define FTGMAC030_MACCR_FULLDUP (1 << 26)
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#define FTGMAC030_MACCR_SPEED_MASK (0x3 << 24)
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#define FTGMAC030_MACCR_SPEED_1000 (2 << 24)
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#define FTGMAC030_MACCR_SPEED_100 (1 << 24)
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#define FTGMAC030_MACCR_SPEED_10 (0 << 24)
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#define FTGMAC030_MACCR_HPTXR (1 << 22)
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#define FTGMAC030_MACCR_LOOPBACK (1 << 21)
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#define FTGMAC030_MACCR_PTP_EN (1 << 20)
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#define FTGMAC030_MACCR_REMOVE_VLAN (1 << 18)
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#define FTGMAC030_MACCR_CRC_APD (1 << 17)
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#define FTGMAC030_MACCR_DROP_CRC_ERR (1 << 16)
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#define FTGMAC030_MACCR_ENRX_IN_HALFTX (1 << 14)
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#define FTGMAC030_MACCR_JUMBO_LF (1 << 13)
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#define FTGMAC030_MACCR_RX_RUNT (1 << 12)
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#define FTGMAC030_MACCR_BROADPKT (1 << 11)
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#define FTGMAC030_MACCR_MULTIPKT (1 << 10)
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#define FTGMAC030_MACCR_HT_EN (1 << 9)
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#define FTGMAC030_MACCR_ALLADDR (1 << 8)
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#define FTGMAC030_MACCR_RXMAC (1 << 3)
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#define FTGMAC030_MACCR_TXMAC (1 << 2)
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#define FTGMAC030_MACCR_RXDMA (1 << 1)
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#define FTGMAC030_MACCR_TXDMA (1 << 0)
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#define FTGMAC030_MACCR_DEFAULT ( \
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FTGMAC030_MACCR_RX_RUNT | \
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FTGMAC030_MACCR_CRC_APD | \
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FTGMAC030_MACCR_FULLDUP | \
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FTGMAC030_MACCR_TXDMA | \
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FTGMAC030_MACCR_RXMAC | \
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FTGMAC030_MACCR_RXDMA | \
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FTGMAC030_MACCR_TXMAC)
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/*
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* MAC Status Register 0x54
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*/
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#define FTGMAC030_MACSR_COL_EXCEED
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#define FTGMAC030_MACSR_LATE_COL
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#define FTGMAC030_MACSR_XPKT_LOST
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#define FTGMAC030_MACSR_XPKT_OK
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#define FTGMAC030_MACSR_RUNT
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#define FTGMAC030_MACSR_FTL
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#define FTGMAC030_MACSR_CRC_ERR
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#define FTGMAC030_MACSR_RPKT_LOST
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#define FTGMAC030_MACSR_RPKT_SAVE
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#define FTGMAC030_MACSR_COL
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#define FTGMAC030_MACSR_BROADCAST
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#define FTGMAC030_MACSR_MULTICAST
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/*
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* Test Mode Register 0x58
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*/
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#define FTGMAC030_TM_PTIMER_TEST (1 << 20)
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#define FTGMAC030_TM_ITIMER_TEST (1 << 19)
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#define FTGMAC030_TM_TEST_COL (1 << 15)
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#define FTGMAC030_TM_TEST_BKOFF(x) ((x & 0x3ff) << 5)
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#define FTGMAC030_TM_TEST_EXSTHR(x) ((x & 0x1f) << 0)
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/*
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* PHY Control Register 0x60
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*/
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#define FTGMAC030_MDIO_SOF 1
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#define FTGMAC030_MDIO_EXT_SOF 0
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#define FTGMAC030_MDIO_OP_RD 2
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#define FTGMAC030_MDIO_OP_WR 1
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#define FTGMAC030_PHYCR_PHYWR (1 << 27)
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#define FTGMAC030_PHYCR_PHYRD (1 << 26)
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#define FTGMAC030_PHYCR_REGAD(x) ((x & 0x1f) << 21)
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#define FTGMAC030_PHYCR_PHYAD(x) ((x & 0x1f) << 16)
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#define FTGMAC030_PHYCR_OP(x) ((x & 0x3) << 14)
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#define FTGMAC030_PHYCR_SOF(x) ((x & 0x3) << 12)
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#define FTGMAC030_PHYCR_MDC_CYCTHR(x) ((x) & 0xff)
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#define FTGMAC030_PHYCR_MDC_CYCTHR_MASK 0xff
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/*
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* PHY Data Register 0x64
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*/
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#define FTGMAC030_PHYDATA_MIIRDATA(x) ((x & 0xffff0000) >> 16)
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#define FTGMAC030_PHYDATA_MIIWDATA(x) ((x & 0xffff) >> 0)
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/*
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* Flow Control Register 0x68
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*/
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#define FTGMAC030_FCR_PAUSE_TIME(x) ((x & 0xffff) << 16)
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#define FTGMAC030_FCR_FC_H_L(x) ((x & 0x7f) << 9)
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#define FTGMAC030_FCR_HTHR (1 << 8)
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#define FTGMAC030_FCR_RX_PAUSE (1 << 4)
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#define FTGMAC030_FCR_TXPAUSED (1 << 3)
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#define FTGMAC030_FCR_FCTHR_EN (1 << 2)
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#define FTGMAC030_FCR_TX_PAUSE (1 << 1)
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#define FTGMAC030_FCR_FC_EN (1 << 0)
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/*
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* Back Pressure Register 0x6c
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*/
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#define ftgmac030_BPR_BK_LOW(x) ((x & 0x7f) << 8)
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#define ftgmac030_BPR_BKJAM_LEN(x) ((x & 0xf) << 4)
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#define ftgmac030_BPR_BKADR_MODE (1 << 1)
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#define ftgmac030_BPR_BKEN (1 << 0)
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/*
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* Wake-On-LAN Control Register 0x70
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*/
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#define FTGMAC030_WOLCR_WOL_TYPE(x) ((x & 0x3) << 24)
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#define FTGMAC030_WOLCR_SW_PDNPHY (1 << 18)
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#define FTGMAC030_WOLCR_WAKEUP_SEL(x) ((x & 0x3) << 16)
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#define FTGMAC030_WOLCR_WAKEUP4 (1 << 6)
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#define FTGMAC030_WOLCR_WAKEUP3 (1 << 5)
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#define FTGMAC030_WOLCR_WAKEUP2 (1 << 4)
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#define FTGMAC030_WOLCR_WAKEUP1 (1 << 3)
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#define FTGMAC030_WOLCR_MAGICPKT (1 << 2)
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#define FTGMAC030_WOLCR_LINKCHG1 (1 << 1)
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#define FTGMAC030_WOLCR_LINKCHG0 (1 << 0)
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/*
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* Wake-On-LAN Status Register 0x74
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*/
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#define FTGMAC030_WOLSR_WAKEUP4 (1 << 6)
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#define FTGMAC030_WOLSR_WAKEUP3 (1 << 5)
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#define FTGMAC030_WOLSR_WAKEUP2 (1 << 4)
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#define FTGMAC030_WOLSR_WAKEUP1 (1 << 3)
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#define FTGMAC030_WOLSR_MAGICPKT (1 << 2)
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#define FTGMAC030_WOLSR_LINKCHG1 (1 << 1)
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#define FTGMAC030_WOLSR_LINKCHG0 (1 << 0)
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/*
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* Transmit descriptor, aligned to 16 bytes
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*/
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struct ftgmac030_txdes {
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volatile unsigned int txdes0;
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volatile unsigned int txdes1;
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volatile unsigned int txdes2; /* not used by HW */
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volatile unsigned int txdes3; /* TXBUF_BADR */
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} __attribute__ ((aligned(16)));
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#define FTGMAC030_TXDES0_TXDMA_OWN (1 << 31)
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#define FTGMAC030_TXDES0_FTS (1 << 29)
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#define FTGMAC030_TXDES0_LTS (1 << 28)
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#define FTGMAC030_TXDES0_CRC_ERR (1 << 19)
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#define FTGMAC030_TXDES0_EDOTR (1 << 15)
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#define FTGMAC030_TXDES0_BUF_SIZE(x) ((x & 0x3fff) << 0)
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#define FTGMAC030_TXDES1_TXIC (1 << 31)
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#define FTGMAC030_TXDES1_TX2FIC (1 << 30)
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#define FTGMAC030_TXDES1_LLC_PKT (1 << 22)
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#define FTGMAC030_TXDES1_IPV6_PKT (1 << 20)
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#define FTGMAC030_TXDES1_OTHER_PKT (2 << 20)
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#define FTGMAC030_TXDES1_IPCS_EN (1 << 19)
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#define FTGMAC030_TXDES1_UDPCS_EN (1 << 18)
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#define FTGMAC030_TXDES1_TCPCS_EN (1 << 17)
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#define FTGMAC030_TXDES1_INS_VLAN (1 << 16)
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#define FTGMAC030_TXDES1_VLAN_TAGC(x) ((x & 0xffff) << 0)
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#define FTGMAC030_TXDES1_DEFAULT (FTGMAC030_TXDES1_TXIC | FTGMAC030_TXDES1_TX2FIC)
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/*
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* Receive descriptor, aligned to 16 bytes
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*/
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struct ftgmac030_rxdes {
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volatile unsigned int rxdes0;
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volatile unsigned int rxdes1;
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volatile unsigned int rxdes2; /* not used by HW */
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volatile unsigned int rxdes3; /* RXBUF_BADR */
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} __attribute__ ((aligned(16)));
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#define FTGMAC030_RXDES0_RXPKT_RDY (1 << 31)
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#define FTGMAC030_RXDES0_FRS (1 << 29)
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#define FTGMAC030_RXDES0_LRS (1 << 28)
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#define FTGMAC030_RXDES0_PAUSE_FRAME (1 << 25)
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#define FTGMAC030_RXDES0_PAUSE_OPCODE (1 << 24)
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#define FTGMAC030_RXDES0_FIFO_FULL (1 << 23)
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#define FTGMAC030_RXDES0_RX_ODD_NB (1 << 22)
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#define FTGMAC030_RXDES0_RUNT (1 << 21)
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#define FTGMAC030_RXDES0_FTL (1 << 20)
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#define FTGMAC030_RXDES0_CRC_ERR (1 << 19)
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#define FTGMAC030_RXDES0_RX_ERR (1 << 18)
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#define FTGMAC030_RXDES0_BROADCAST (1 << 17)
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#define FTGMAC030_RXDES0_MULTICAST (1 << 16)
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#define FTGMAC030_RXDES0_EDORR (1 << 15)
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#define FTGMAC030_RXDES0_VDBC(x) ((x & 0x3fff) << 0)
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#define FTGMAC030_RXDES1_IPCS_FAIL (1 << 27)
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#define FTGMAC030_RXDES1_UDPCS_FAIL (1 << 26)
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#define FTGMAC030_RXDES1_TCPCS_FAIL (1 << 25)
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#define FTGMAC030_RXDES1_VLAN_AVA (1 << 24)
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#define FTGMAC030_RXDES1_DF (1 << 23)
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#define FTGMAC030_RXDES1_LLC_PKT (1 << 22)
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#define FTGMAC030_RXDES1_PROTL_TYPE(x) ((x >> 20) & 0x3)
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#define FTGMAC030_RXDES1_IP6_TYPE(x) ((x >> 19) & 0x1)
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#define FTGMAC030_RXDES1_VLAN_PRIO(x) ((x & 7) << 13)
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#define FTGMAC030_RXDES1_VLAN_CFI(x) ((x & 1) << 12)
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#define FTGMAC030_RXDES1_VLAN_VID(x) (x & 0x0fff)
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#define FTGMAC030_RXDES1_VLAN_TAGC(x) (x & 0xffff)
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#define FTGMAC030_RXDES1_PROT_MASK (0x3 << 20)
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#define FTGMAC030_RXDES1_PROTL_NOTIP 0
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#define FTGMAC030_RXDES1_PROTL_IP4 1
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#define FTGMAC030_RXDES1_PROTL_TCPIP 2
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#define FTGMAC030_RXDES1_PROTL_UDPIP 3
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/* 0:MII or GMII,(don't suport) 1:RMII, 2: RGMII */
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enum ftgmac030_if_mode {
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FTGMAC030_MODE_MII_GMII,
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FTGMAC030_MODE_RMII,
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FTGMAC030_MODE_RGMII,
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};
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int ftgmac030_mdio_read(struct eth_device *dev, int phy_addr, int regnum);
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int ftgmac030_mdio_write(struct eth_device *dev, int phy_addr, int regnum, u16 value);
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#endif /* __FTGMAC030_H */
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