175 lines
2.8 KiB
C
Executable File
175 lines
2.8 KiB
C
Executable File
// SPDX-License-Identifier: GPL-2.0+
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#include <config.h>
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#include "bspeth.h"
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#include "sys.h"
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#include "ftgmac030.h"
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static void bspeth_reset(int rst)
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{
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u32 val;
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val = _readl(BSPETH_MAC_CRG_REG);
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if (rst)
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val |= ETH_SOFT_RESET;
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else
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val &= ~ETH_SOFT_RESET;
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_writel(val, BSPETH_MAC_CRG_REG);
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udelay(100); /* delay 100us */
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}
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static inline void bspeth_clk_ena(void)
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{
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}
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static inline void bspeth_clk_dis(void)
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{
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}
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static void bspeth_reset_internal_phy(void)
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{
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}
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static void bspeth_reset_external_phy_by_crg(void)
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{
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u32 v;
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u32 phy_reset_n;
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/* bit[1]*/
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phy_reset_n = readl(BSPETH_CFG_CRG_REG);
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phy_reset_n &= ETH_PHY_RST_N;
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/************************************************/
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/* reset external phy with default reset pin */
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v = readl(BSPETH_PHY_CRG_REG);
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if (phy_reset_n)
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v |= ETH_EXTERNAL_PHY_RESET;
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else
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v &= ~ETH_EXTERNAL_PHY_RESET;
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writel(v, BSPETH_PHY_CRG_REG);
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mdelay(10); /* delay 10ms */
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/* then, cancel reset, and should delay some time */
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v = readl(BSPETH_PHY_CRG_REG);
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if (phy_reset_n)
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v &= ~ETH_EXTERNAL_PHY_RESET;
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else
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v |= ETH_EXTERNAL_PHY_RESET;
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writel(v, BSPETH_PHY_CRG_REG);
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mdelay(20); /* delay 20ms */
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/* then, cancel reset, and should delay some time */
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v = readl(BSPETH_PHY_CRG_REG);
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if (phy_reset_n)
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v |= ETH_EXTERNAL_PHY_RESET;
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else
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v &= ~ETH_EXTERNAL_PHY_RESET;
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writel(v, BSPETH_PHY_CRG_REG);
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mdelay(150); /* delay 150ms */
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}
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static void bspeth_reset_external_phy_by_gpio(void)
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{
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}
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static void bspeth_phy_reset(void)
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{
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bspeth_reset_internal_phy();
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bspeth_reset_external_phy_by_crg();
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bspeth_reset_external_phy_by_gpio();
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}
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static void bspeth_funsel_config(void)
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{
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}
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static void bspeth_funsel_restore(void)
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{
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}
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///**************************************************/
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//void bspeth_sys_startup(void)
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//{
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// bspeth_clk_ena();
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// /* undo reset */
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// bspeth_reset(0);
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//}
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void bspeth_sys_allstop(void)
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{
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}
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u32 bspeth_get_phy_intf(void)
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{
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u32 phy_intf;
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/* bit[0]: 0 -- rmii，1 -- rgmii bit[3]:1 --mii or gmii*/
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phy_intf = readl(BSPETH_CFG_CRG_REG);
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phy_intf &= ETH_PHY_INTF;
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if (phy_intf & bit(3))
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return FTGMAC030_MODE_MII_GMII;
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else if (phy_intf & bit(0))
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return FTGMAC030_MODE_RGMII;
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else
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return FTGMAC030_MODE_RMII;
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}
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/* Set rgmii tx delay for 2ns */
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void bspeth_set_tx_delay(void)
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{
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u32 regval;
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u32 timeout = 100;//1ms
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regval = readl(BSPETH_DLY_CRG_REG);
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if(!(regval & ETH_DLY_SEL)) {
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writel(regval | ETH_DLY_SEL, BSPETH_DLY_CRG_REG);
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do {
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udelay(10);
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regval = readl(BSPETH_DLY_STAT_REG);
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--timeout;
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} while ((!(regval & ETH_DLY_STAT) && timeout));
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}
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if(!timeout)
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printf("Error: bspeth_set_tx_delay timeout!\n");
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}
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void bspeth_sys_init(void)
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{
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bspeth_funsel_config();
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bspeth_sys_allstop();
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bspeth_clk_ena();
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bspeth_reset(1);
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bspeth_reset(0);
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bspeth_phy_reset();
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}
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void bspeth_sys_exit(void)
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{
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bspeth_funsel_restore();
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bspeth_sys_allstop();
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}
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