423 lines
11 KiB
ArmAsm
Executable File
423 lines
11 KiB
ArmAsm
Executable File
/*
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* Copyright (c) LOTUS. All rights reserved.
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/system.h>
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#include <linux/linkage.h>
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#include <asm/armv7.h>
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#include <linux/lotus/step.h>
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.globl _start
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_start:
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/***** Key Area ****/
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.=CONFIG_ROOT_RSA_PUB_KEY_N_POS
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b _checked_area_start
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.fill CONFIG_ROOT_RSA_PUB_KEY_N_LEN - 4, 1, 0
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.=CONFIG_ROOT_RSA_PUB_KEY_E_POS
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.fill CONFIG_ROOT_RSA_PUB_KEY_E_ZERO_LEN, 1, 0
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.=(CONFIG_ROOT_RSA_PUB_KEY_E_POS + CONFIG_ROOT_RSA_PUB_KEY_E_ZERO_LEN)
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.word CONFIG_ROOT_RSA_PUB_KEY_E_V
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/***** Params Area ****/
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.=CONFIG_AUXCODE_AREA_LEN_POS
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.word CONFIG_AUXAREA_LEN
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.=CONFIG_BOOT_CODE_AREA_LEN_POS
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.word _checked_area_end - _checked_area_start
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.=CONFIG_TOTAL_BOOT_AREA_LEN_POS
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.word (_checked_area_end - _checked_area_start + 0x200)
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.=CONFIG_PARAMS_FORM_LEN_POS
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.word CONFIG_PARAMS_FORM_LEN
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.=CONFIG_BOOT_ENC_FLAG_POS
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.word CONFIG_BOOT_ENC_FLAG
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.=CONFIG_BOOT_ENTRY_PIONT_POS
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.word CONFIG_BOOT_ENTRY_PIONT
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.=CONFIG_AUXCODE_AES_IV_POS
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.fill 16, 1, 0
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.=CONFIG_BOOT_AES_IV_POS
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.fill 16, 1, 0
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.=CONFIG_PARAMS_FORM_POS
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_default_boot_reg_pos:
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.incbin CONFIG_BOOTREG_DEFAULT /* reg */
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_default_boot_reg_end:
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.=CONFIG_LOAD_MCU_FW_FLAG_POS
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.word CONFIG_LOAD_MCU_FW_FLAG
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.=CONFIG_MCU_FW_AREA_LEN_POS
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.word CONFIG_MCU_FW_AREA_LEN
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.=CONFIG_MCU_FW_BUF_ADDR_POS
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.word CONFIG_MCU_FW_BUF_ADDR
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.=CONFIG_DDR_PARAM_OFFSET_POS
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.word CONFIG_DDR_PARAM_OFFSET
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.=CONFIG_DDR_PARAM_SIZE_POS
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.word CONFIG_DDR_PARAM_SIZE
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.=CONFIG_AUXCODE_WATCHDOG_POS
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.word CONFIG_AUXCODE_WATCHDOG
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.=CONFIG_AUXCODE_WDT_TIMEOUT_MSECS_POS
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.word CONFIG_AUXCODE_WDT_TIMEOUT_MSECS
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.=CONFIG_RESERVED0_POS
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.fill CONFIG_RESERVED0_LEN, 1, 0
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.=CONFIG_SIG_PARAMS_POS
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.fill CONFIG_SIG_PARAMS_LEN, 1, 0
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/**** Uncheck Area ****/
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.=CONFIG_SCS_SIMULATE_FLAG_POS
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.word CONFIG_SCS_SIMULATE_FLAG
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.=CONFIG_BOOT_STORE_ADDR_POS
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.word CONFIG_BOOT_STORE_ADDR
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.=CONFIG_FLASH_EMPYT_FLAG_POS
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.word CONFIG_FLASH_EMPYT_FLAG
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.=CONFIG_AUXCODE_LOG_CTRL_POS
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.word CONFIG_AUXCODE_LOG_CTRL
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.=CONFIG_AUXCODE_SVB_CTRL_POS
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.word CONFIG_AUXCODE_SVB_CTRL
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.=CONFIG_RESERVED1_POS
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.fill CONFIG_RESERVED1_LEN, 1, 0
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/**** Auxcode Area *****/
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.=CONFIG_IMAGE_INFO_POS
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.incbin CONFIG_AUXIMAGE
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/* mcu fw */
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#if (CONFIG_MCU_FW_AREA_LEN > 0)
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.=CONFIG_MCU_FW_AREA_POS
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.incbin CONFIG_MCU_FW_IMAGE
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#endif
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/**** Boot Code Area *****/
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.=CONFIG_BOOT_CODE_AREA_POS
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.align 4
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_checked_area_start:
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b reset
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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ldr pc, _data_abort
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ldr pc, _not_used
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ldr pc, _irq
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ldr pc, _fiq
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.balignl 64,0xdeadbeef
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_undefined_instruction: .word irq_undefined_instruction
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_software_interrupt: .word irq_software_interrupt
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_prefetch_abort: .word irq_prefetch_abort
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_data_abort: .word irq_data_abort
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_not_used: .word irq_not_used
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_irq: .word irq_irq
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_fiq: .word irq_firq
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.globl reset
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.globl save_boot_params_ret
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/* fix text_base,real code position */
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.globl _TEXT_BASE
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_TEXT_BASE:
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.word TEXT_BASE + CONFIG_KEY_AREA_LEN + CONFIG_AUXAREA_LEN
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_start_armboot:
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.word start_armboot
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_bss_start:
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.word __bss_start
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_bss_end:
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.word __bss_end
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.globl __checked_area_start
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__checked_area_start:
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.word _checked_area_start
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reset:
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step_no_stack 30, r11, r12
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/* Allow the board to save important registers */
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b save_boot_params
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save_boot_params_ret:
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/*
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* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
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* except if in HYP mode already
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*/
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mrs r0, cpsr
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and r1, r0, #0x1f @ mask mode bits
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teq r1, #0x1a @ test for HYP mode
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bicne r0, r0, #0x1f @ clear all mode bits
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orrne r0, r0, #0x13 @ set SVC mode
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orr r0, r0, #0xc0 @ disable FIQ and IRQ
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msr cpsr,r0
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/* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
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mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
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bic r0, #CR_V @ V = 0
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mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
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/* Set vector address in CP15 VBAR register */
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adrl r0, _checked_area_start
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mcr p15, 0, r0, c12, c0, 0 @Set VBAR
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_cp15
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#endif
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normal_start_flow:
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/* Early init */
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ldr sp, =CONFIG_SYS_INIT_SP_ADDR
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step 31
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bl timer_init
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bl timestamp_init
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bl uart_early_init
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bl msg_main_cpu_startup
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#ifndef CONFIG_SYS_ICACHE_OFF
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@enable I-Cache now
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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mcr p15, 0, r0, c1, c0, 0
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#endif
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step 32
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#ifndef CONFIG_LOTUS_GZIP_BOOT
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/* move uboot to final text base */
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ldr r1, =CONFIG_SYS_TEXT_BASE
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ldr r0, =input_data
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ldr r3, =input_data_end
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sub r2, r3, r0
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/* memcpy(r1, r0, r2) */
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bl memcpy
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#endif
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step 33
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clear_bss:
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/* clean .bss section */
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ldr r0, _bss_start
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ldr r1, _bss_end
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mov r2, #0x0
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next_bss:
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str r2, [r0] @ clear BSS location
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cmp r0, r1 @ are we at the end yet
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add r0, r0, #4 @ increment clear index pointer
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bne next_bss @ keep clearing till at end
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step 34
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relocate:
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ldr r0, =_start_armboot
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ldr pc, [r0]
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bug:
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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b . /* bug here */
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@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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@
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@ void memcpy(r1, r0, r2);
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@
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.align 2
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memcpy:
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add r2, r0, r2
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memcpy_loop:
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ldmia r0!, {r3 - r10}
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stmia r1!, {r3 - r10}
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cmp r0, r2
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ble memcpy_loop
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mov pc, lr
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@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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.align 2
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msg_main_cpu_startup:
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mov r5, lr
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add r0, pc, #4
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bl uart_early_puts
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mov pc, r5
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L10:
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.ascii "\r\n\r\nSystem startup\r\n\0"
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/*------------------------------------------------------------------------------*/
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ENTRY(c_runtime_cpu_setup)
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/*
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* If I-cache is enabled invalidate it
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*/
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#ifndef CONFIG_SYS_ICACHE_OFF
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mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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#endif
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bx lr
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ENDPROC(c_runtime_cpu_setup)
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/*************************************************************************
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*
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* void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
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* __attribute__((weak));
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*
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* Stack pointer is not yet initialized at this moment
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* Don't save anything to stack even if compiled with -O0
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*
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*************************************************************************/
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ENTRY(save_boot_params)
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b save_boot_params_ret @ back to my caller
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ENDPROC(save_boot_params)
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.weak save_boot_params
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/*************************************************************************
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*
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* cpu_init_cp15
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*
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* Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
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* CONFIG_SYS_ICACHE_OFF is defined.
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*
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*************************************************************************/
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ENTRY(cpu_init_cp15)
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/*
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* Invalidate L1 I/D
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*/
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mov r0, #0 @ set up for MCR
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mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
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bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
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orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
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orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
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#ifdef CONFIG_SYS_ICACHE_OFF
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bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
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#else
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
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#endif
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mcr p15, 0, r0, c1, c0, 0
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#ifdef CONFIG_ARM_ERRATA_716044
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mrc p15, 0, r0, c1, c0, 0 @ read system control register
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orr r0, r0, #1 << 11 @ set bit #11
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mcr p15, 0, r0, c1, c0, 0 @ write system control register
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#endif
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#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 4 @ set bit #4
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_743622
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 6 @ set bit #6
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_751472
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 11 @ set bit #11
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_761320
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 21 @ set bit #21
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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mov r5, lr @ Store my Caller
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mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
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mov r3, r1, lsr #20 @ get variant field
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and r3, r3, #0xf @ r3 has CPU variant
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and r4, r1, #0xf @ r4 has CPU revision
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mov r2, r3, lsl #4 @ shift variant field for combined value
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orr r2, r4, r2 @ r2 has combined CPU variant + revision
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#ifdef CONFIG_ARM_ERRATA_798870
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cmp r2, #0x30 @ Applies to lower than R3p0
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bge skip_errata_798870 @ skip if not affected rev
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cmp r2, #0x20 @ Applies to including and above R2p0
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blt skip_errata_798870 @ skip if not affected rev
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mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg
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orr r0, r0, #1 << 7 @ Enable hazard-detect timeout
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push {r1-r5} @ Save the cpu info registers
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bl v7_arch_cp15_set_l2aux_ctrl
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isb @ Recommended ISB after l2actlr update
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pop {r1-r5} @ Restore the cpu info - fall through
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skip_errata_798870:
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#endif
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#ifdef CONFIG_ARM_ERRATA_801819
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cmp r2, #0x24 @ Applies to lt including R2p4
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bgt skip_errata_801819 @ skip if not affected rev
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cmp r2, #0x20 @ Applies to including and above R2p0
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blt skip_errata_801819 @ skip if not affected rev
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mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg
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and r0, r0, #1 << 3 @ check REVIDR[3]
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cmp r0, #1 << 3
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beq skip_errata_801819 @ skip erratum if REVIDR[3] is set
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mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
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orr r0, r0, #3 << 27 @ Disables streaming. All write-allocate
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@ lines allocate in the L1 or L2 cache.
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orr r0, r0, #3 << 25 @ Disables streaming. All write-allocate
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@ lines allocate in the L1 cache.
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push {r1-r5} @ Save the cpu info registers
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bl v7_arch_cp15_set_acr
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pop {r1-r5} @ Restore the cpu info - fall through
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skip_errata_801819:
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#endif
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#ifdef CONFIG_ARM_ERRATA_454179
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cmp r2, #0x21 @ Only on < r2p1
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bge skip_errata_454179
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mrc p15, 0, r0, c1, c0, 1 @ Read ACR
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orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
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push {r1-r5} @ Save the cpu info registers
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bl v7_arch_cp15_set_acr
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pop {r1-r5} @ Restore the cpu info - fall through
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skip_errata_454179:
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#endif
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#ifdef CONFIG_ARM_ERRATA_430973
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cmp r2, #0x21 @ Only on < r2p1
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bge skip_errata_430973
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mrc p15, 0, r0, c1, c0, 1 @ Read ACR
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orr r0, r0, #(0x1 << 6) @ Set IBE bit
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push {r1-r5} @ Save the cpu info registers
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bl v7_arch_cp15_set_acr
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pop {r1-r5} @ Restore the cpu info - fall through
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skip_errata_430973:
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#endif
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#ifdef CONFIG_ARM_ERRATA_621766
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cmp r2, #0x21 @ Only on < r2p1
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bge skip_errata_621766
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mrc p15, 0, r0, c1, c0, 1 @ Read ACR
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orr r0, r0, #(0x1 << 5) @ Set L1NEON bit
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push {r1-r5} @ Save the cpu info registers
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bl v7_arch_cp15_set_acr
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pop {r1-r5} @ Restore the cpu info - fall through
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skip_errata_621766:
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#endif
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mov pc, r5 @ back to my caller
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ENDPROC(cpu_init_cp15)
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