171 lines
4.9 KiB
C
Executable File
171 lines
4.9 KiB
C
Executable File
#ifndef __OX03F10_H__
|
|
#define __OX03F10_H__
|
|
|
|
#include "sns_comm.h"
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
#define OX03F10_BIT_WIDTH_14
|
|
|
|
// HCG/LCG/SPD DO NOT set to 1 at the same time.
|
|
#define OX03F10_HCG 0
|
|
#define OX03F10_LCG 1
|
|
#define OX03F10_SPD 0
|
|
|
|
#define OX03F10_FULL_LINES_MAX 0xffff
|
|
|
|
#ifdef FPGA
|
|
#define OX03F10_VMAX_1M_BUILT_IN 1200
|
|
#define OX03F10_VMAX_2M_BUILT_IN 0 // Not support
|
|
#else
|
|
#define OX03F10_VMAX_1M_BUILT_IN 0x2ae
|
|
#define OX03F10_VMAX_2M_BUILT_IN 0x2ae
|
|
#define OX03F10_VMAX_3M_BUILT_IN 823
|
|
#define OX03F10_VMAX_3M_LINEAR OX03F10_VMAX_3M_BUILT_IN
|
|
#endif
|
|
|
|
#define OX03F10_EXP_OFFSET 4
|
|
|
|
// OX03F10 Register Address
|
|
#define OX03F10_VMAX_H_ADDR 0x380e
|
|
#define OX03F10_VMAX_L_ADDR 0x380f
|
|
|
|
#define OX03F10_REG_ADDR_HCG_EXP_H 0x3501
|
|
#define OX03F10_REG_ADDR_HCG_EXP_L 0x3502
|
|
#define OX03F10_REG_ADDR_HCG_AGC_H 0x3508
|
|
#define OX03F10_REG_ADDR_HCG_AGC_L 0x3509
|
|
#define OX03F10_REG_ADDR_HCG_DGC_H 0x350a
|
|
#define OX03F10_REG_ADDR_HCG_DGC_M 0x350b
|
|
#define OX03F10_REG_ADDR_HCG_DGC_L 0x350c
|
|
#define OX03F10_REG_ADDR_LCG_AGC_H 0x3588
|
|
#define OX03F10_REG_ADDR_LCG_AGC_L 0x3589
|
|
#define OX03F10_REG_ADDR_LCG_DGC_H 0x358a
|
|
#define OX03F10_REG_ADDR_LCG_DGC_M 0x358b
|
|
#define OX03F10_REG_ADDR_LCG_DGC_L 0x358c
|
|
|
|
#define OX03F10_REG_ADDR_SPD_EXP_H 0x3541
|
|
#define OX03F10_REG_ADDR_SPD_EXP_L 0x3542
|
|
#define OX03F10_REG_ADDR_SPD_AGC_H 0x3548
|
|
#define OX03F10_REG_ADDR_SPD_AGC_L 0x3549
|
|
#define OX03F10_REG_ADDR_SPD_DGC_H 0x354a
|
|
#define OX03F10_REG_ADDR_SPD_DGC_M 0x354b
|
|
#define OX03F10_REG_ADDR_SPD_DGC_L 0x354c
|
|
|
|
#define OX03F10_REG_ADDR_VS_EXP_H 0x35c1
|
|
#define OX03F10_REG_ADDR_VS_EXP_L 0x35c2
|
|
#define OX03F10_REG_ADDR_VS_AGC_H 0x35c8
|
|
#define OX03F10_REG_ADDR_VS_AGC_L 0x35c9
|
|
#define OX03F10_REG_ADDR_VS_DGC_H 0x35ca
|
|
#define OX03F10_REG_ADDR_VS_DGC_M 0x35cb
|
|
#define OX03F10_REG_ADDR_VS_DGC_L 0x35cc
|
|
|
|
#define OX03F10_REG_ADDR_HCG_WB_R_H 0x5286
|
|
#define OX03F10_REG_ADDR_HCG_WB_R_L 0x5287
|
|
#define OX03F10_REG_ADDR_HCG_WB_GR_H 0x5284
|
|
#define OX03F10_REG_ADDR_HCG_WB_GR_L 0x5285
|
|
#define OX03F10_REG_ADDR_HCG_WB_B_H 0x5280
|
|
#define OX03F10_REG_ADDR_HCG_WB_B_L 0x5281
|
|
#define OX03F10_REG_ADDR_HCG_WB_GB_H 0x5282
|
|
#define OX03F10_REG_ADDR_HCG_WB_GB_L 0x5283
|
|
|
|
#define OX03F10_REG_ADDR_LCG_WB_R_H 0x5486
|
|
#define OX03F10_REG_ADDR_LCG_WB_R_L 0x5487
|
|
#define OX03F10_REG_ADDR_LCG_WB_GR_H 0x5484
|
|
#define OX03F10_REG_ADDR_LCG_WB_GR_L 0x5485
|
|
#define OX03F10_REG_ADDR_LCG_WB_B_H 0x5480
|
|
#define OX03F10_REG_ADDR_LCG_WB_B_L 0x5481
|
|
#define OX03F10_REG_ADDR_LCG_WB_GB_H 0x5482
|
|
#define OX03F10_REG_ADDR_LCG_WB_GB_L 0x5483
|
|
|
|
#define OX03F10_REG_ADDR_SPD_WB_R_H 0x5686
|
|
#define OX03F10_REG_ADDR_SPD_WB_R_L 0x5687
|
|
#define OX03F10_REG_ADDR_SPD_WB_GR_H 0x5684
|
|
#define OX03F10_REG_ADDR_SPD_WB_GR_L 0x5685
|
|
#define OX03F10_REG_ADDR_SPD_WB_B_H 0x5680
|
|
#define OX03F10_REG_ADDR_SPD_WB_B_L 0x5681
|
|
#define OX03F10_REG_ADDR_SPD_WB_GB_H 0x5682
|
|
#define OX03F10_REG_ADDR_SPD_WB_GB_L 0x5683
|
|
|
|
#define OX03F10_REG_ADDR_VS_WB_R_H 0x5886
|
|
#define OX03F10_REG_ADDR_VS_WB_R_L 0x5887
|
|
#define OX03F10_REG_ADDR_VS_WB_GR_H 0x5884
|
|
#define OX03F10_REG_ADDR_VS_WB_GR_L 0x5885
|
|
#define OX03F10_REG_ADDR_VS_WB_B_H 0x5880
|
|
#define OX03F10_REG_ADDR_VS_WB_B_L 0x5881
|
|
#define OX03F10_REG_ADDR_VS_WB_GB_H 0x5882
|
|
#define OX03F10_REG_ADDR_VS_WB_GB_L 0x5883
|
|
|
|
typedef enum {
|
|
OX03F10_REG_VMAX_H = 0,
|
|
OX03F10_REG_VMAX_L,
|
|
OX03F10_REG_HCG_EXP_H,
|
|
OX03F10_REG_HCG_EXP_L,
|
|
OX03F10_REG_HCG_AGC_L,
|
|
OX03F10_REG_HCG_AGC_H,
|
|
OX03F10_REG_HCG_DGC_L,
|
|
OX03F10_REG_HCG_DGC_M,
|
|
OX03F10_REG_HCG_DGC_H,
|
|
OX03F10_REG_LCG_AGC_L,
|
|
OX03F10_REG_LCG_AGC_H,
|
|
OX03F10_REG_LCG_DGC_L,
|
|
OX03F10_REG_LCG_DGC_M,
|
|
OX03F10_REG_LCG_DGC_H,
|
|
OX03F10_REG_SPD_EXP_L,
|
|
OX03F10_REG_SPD_EXP_H,
|
|
OX03F10_REG_SPD_AGC_L,
|
|
OX03F10_REG_SPD_AGC_H,
|
|
OX03F10_REG_SPD_DGC_L,
|
|
OX03F10_REG_SPD_DGC_M,
|
|
OX03F10_REG_SPD_DGC_H,
|
|
OX03F10_REG_VS_EXP_H,
|
|
OX03F10_REG_VS_EXP_L,
|
|
OX03F10_REG_VS_AGC_L,
|
|
OX03F10_REG_VS_AGC_H,
|
|
OX03F10_REG_VS_DGC_L,
|
|
OX03F10_REG_VS_DGC_M,
|
|
OX03F10_REG_VS_DGC_H,
|
|
|
|
OX03F10_REG_HCG_WB_R_H,
|
|
OX03F10_REG_HCG_WB_R_L,
|
|
OX03F10_REG_HCG_WB_GR_H,
|
|
OX03F10_REG_HCG_WB_GR_L,
|
|
OX03F10_REG_HCG_WB_B_H,
|
|
OX03F10_REG_HCG_WB_B_L,
|
|
OX03F10_REG_HCG_WB_GB_H,
|
|
OX03F10_REG_HCG_WB_GB_L,
|
|
OX03F10_REG_LCG_WB_R_H,
|
|
OX03F10_REG_LCG_WB_R_L,
|
|
OX03F10_REG_LCG_WB_GR_H,
|
|
OX03F10_REG_LCG_WB_GR_L,
|
|
OX03F10_REG_LCG_WB_B_H,
|
|
OX03F10_REG_LCG_WB_B_L,
|
|
OX03F10_REG_LCG_WB_GB_H,
|
|
OX03F10_REG_LCG_WB_GB_L,
|
|
OX03F10_REG_SPD_WB_R_H,
|
|
OX03F10_REG_SPD_WB_R_L,
|
|
OX03F10_REG_SPD_WB_GR_H,
|
|
OX03F10_REG_SPD_WB_GR_L,
|
|
OX03F10_REG_SPD_WB_B_H,
|
|
OX03F10_REG_SPD_WB_B_L,
|
|
OX03F10_REG_SPD_WB_GB_H,
|
|
OX03F10_REG_SPD_WB_GB_L,
|
|
OX03F10_REG_VS_WB_R_H,
|
|
OX03F10_REG_VS_WB_R_L,
|
|
OX03F10_REG_VS_WB_GR_H,
|
|
OX03F10_REG_VS_WB_GR_L,
|
|
OX03F10_REG_VS_WB_B_H,
|
|
OX03F10_REG_VS_WB_B_L,
|
|
OX03F10_REG_VS_WB_GB_H,
|
|
OX03F10_REG_VS_WB_GB_L,
|
|
|
|
OX03F10_REG_MAX_NUM,
|
|
} ox03f10_reg_index;
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif // __OX03F10_H__
|