64 lines
2.3 KiB
C
64 lines
2.3 KiB
C
/*
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* Copyright (c) 2019, ARM Limited. All rights reserved.
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* Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef GIC600_MULTICHIP_H
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#define GIC600_MULTICHIP_H
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#include <stdint.h>
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/*
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* GIC-600 microarchitecture supports coherent multichip environments containing
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* up to 16 chips.
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*/
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#define GIC600_MAX_MULTICHIP 16
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typedef struct multichip_spi_ids_desc {
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uintptr_t gicd_base;
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uint32_t spi_id_min;
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uint32_t spi_id_max;
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} multichip_spi_ids_desc_t;
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/*******************************************************************************
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* GIC-600 multichip data structure describes platform specific attributes
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* related to GIC-600 multichip. Platform port is expected to define these
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* attributes to initialize the multichip related registers and create
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* successful connections between the GIC-600s in a multichip system.
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*
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* The 'rt_owner_base' field contains the base address of the GIC Distributor
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* which owns the routing table.
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*
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* The 'rt_owner' field contains the chip number which owns the routing table.
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* Chip number or chip_id starts from 0.
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*
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* The 'chip_count' field contains the total number of chips in a multichip
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* system. This should match the number of entries in 'chip_addrs' and 'spi_ids'
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* fields.
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*
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* The 'chip_addrs' field contains array of chip addresses. These addresses are
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* implementation specific values.
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*
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* The 'multichip_spi_ids_desc_t' field contains array of descriptors used to
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* provide minimum and maximum SPI interrupt ids that each chip owns and the
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* corresponding chip base address. Note that SPI interrupt ids can range from
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* 32 to 960 and it should be group of 32 (i.e., SPI minimum and (SPI maximum +
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* 1) should be a multiple of 32). If a chip doesn't own any SPI interrupts a
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* value of {0, 0, 0} should be passed.
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******************************************************************************/
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struct gic600_multichip_data {
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uintptr_t rt_owner_base;
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unsigned int rt_owner;
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unsigned int chip_count;
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uint64_t chip_addrs[GIC600_MAX_MULTICHIP];
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multichip_spi_ids_desc_t spi_ids[GIC600_MAX_MULTICHIP];
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};
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uintptr_t gic600_multichip_gicd_base_for_spi(uint32_t spi_id);
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void gic600_multichip_init(struct gic600_multichip_data *multichip_data);
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bool gic600_multichip_is_initialized(void);
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#endif /* GIC600_MULTICHIP_H */
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