27 lines
919 B
C
27 lines
919 B
C
/*
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NEOVERSE_V2_H
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#define NEOVERSE_V2_H
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#define NEOVERSE_V2_MIDR U(0x410FD4F0)
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/* Neoverse V2 loop count for CVE-2022-23960 mitigation */
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#define NEOVERSE_V2_BHB_LOOP_COUNT U(132)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#endif /* NEOVERSE_V2_H */
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