214 lines
5.7 KiB
ArmAsm
Executable File
214 lines
5.7 KiB
ArmAsm
Executable File
/*
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* Copyright (c) Lotus. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cpu_macros.S>
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#include <cortex_a55.h>
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#include <platform_def.h>
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/* Global functions */
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_get_my_entrypoint
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.globl plat_secondary_cold_boot_setup
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.globl platform_mem_init
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl plat_reset_handler
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/* Global variables */
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.globl lotus_sec_entry_point
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.globl ns_image_entrypoint
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.globl lotus_bl31_phys_base
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/* ---------------------
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* Common CPU init code
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* ---------------------
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*/
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.macro cpu_init_common
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/* --------------------------------
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* Enable the cycle count register
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* --------------------------------
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*/
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mrs x0, pmcr_el0
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ubfx x0, x0, #11, #5 // read PMCR.N field
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mov x1, #1
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lsl x0, x1, x0
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sub x0, x0, #1 // mask of event counters
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orr x0, x0, #0x80000000 // disable overflow intrs
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msr pmintenclr_el1, x0
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msr pmuserenr_el0, x1 // enable user mode access
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/* ----------------------------------------------------------------
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* Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count
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* register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ
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* registers from EL0.
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* ----------------------------------------------------------------
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*/
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mrs x0, cntkctl_el1
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orr x0, x0, #EL0VCTEN_BIT
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msr cntkctl_el1, x0
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.endm
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary(void);
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*
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* This function checks if this is the Primary CPU
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #PLAT_LOTUS_PRIMARY_CPU
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cset x0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void);
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*
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* result: CorePos = CoreId + (ClusterId << 2)
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #8
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ret
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned long plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between
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* a cold and warm boot. If the tegra_sec_entry_point for
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* this CPU is present, then it's a warm boot.
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*
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* -----------------------------------------------------
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*/
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func plat_get_my_entrypoint
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adr x1, lotus_sec_entry_point
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ldr x0, [x1]
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ret
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset. Right
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* now this is a stub function.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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mov x0, #0
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ret
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0 - x4
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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mov_imm x0, PLAT_LOTUS_UART_BASE
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mov_imm x1, PLAT_LOTUS_UART_CLOCK_IN_HZ
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mov_imm x2, PLAT_LOTUS_UART_BAUDRATE
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b console_pl011_core_init
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(int c)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, PLAT_LOTUS_UART_BASE
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b console_pl011_core_putc
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endfunc plat_crash_console_putc
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/* ---------------------------------------------
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* void plat_crash_console_flush()
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* Function to force a write of all buffered
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* data that hasn't been output.
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* Out : void.
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* Clobber list : r0
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* ---------------------------------------------
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*/
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func plat_crash_console_flush
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mov_imm x0, PLAT_LOTUS_UART_BASE
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b console_pl011_core_flush
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endfunc plat_crash_console_flush
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/* --------------------------------------------------------
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* void platform_mem_init (void);
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*
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* Any memory init, relocation to be done before the
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* platform boots. Called very early in the boot process.
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* --------------------------------------------------------
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*/
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func platform_mem_init
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mov x0, #0
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ret
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endfunc platform_mem_init
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/* ---------------------------------------------------
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* Function to handle a platform reset and store
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* input parameters passed by BL2.
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* ---------------------------------------------------
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*/
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func plat_reset_handler
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/* -----------------------------------
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* derive and save the phys_base addr
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* -----------------------------------
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*/
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#if 0
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adr x17, lotus_bl31_phys_base
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ldr x18, [x17]
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cbnz x18, 1f
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adr x18, bl31_entrypoint
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str x18, [x17]
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1: cpu_init_common
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#endif
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ret
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endfunc plat_reset_handler
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.data
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.align 3
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/* --------------------------------------------------
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* CPU Secure entry point - resume from suspend
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* --------------------------------------------------
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*/
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lotus_sec_entry_point:
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.quad 0
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/* --------------------------------------------------
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* NS world's cold boot entry point
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* --------------------------------------------------
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*/
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ns_image_entrypoint:
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.quad 0
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/* --------------------------------------------------
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* BL31's physical base address
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* --------------------------------------------------
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*/
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lotus_bl31_phys_base:
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.quad 0
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