123 lines
2.8 KiB
C
123 lines
2.8 KiB
C
/*
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* Copyright (c) 2022, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#if MTK_PUBEVENT_ENABLE
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#include <lib/pm/mtk_pm.h>
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#endif
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#include <ptp3_plat.h>
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#define PTP3_CORE_OFT(core) (0x800 * (core))
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static void ptp3_init(unsigned int core)
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{
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unsigned int i, addr, value;
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if (core < PTP3_CFG_CPU_START_ID_B) {
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mmio_clrsetbits_32(ptp3_cfg1[0][PTP3_CFG_ADDR], PTP3_CFG1_MASK,
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ptp3_cfg1[0][PTP3_CFG_VALUE]);
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} else {
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mmio_clrsetbits_32(ptp3_cfg1[1][PTP3_CFG_ADDR], PTP3_CFG1_MASK,
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ptp3_cfg1[1][PTP3_CFG_VALUE]);
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}
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if (core < PTP3_CFG_CPU_START_ID_B) {
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for (i = 0; i < NR_PTP3_CFG2_DATA; i++) {
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addr = ptp3_cfg2[i][PTP3_CFG_ADDR] + PTP3_CORE_OFT(core);
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value = ptp3_cfg2[i][PTP3_CFG_VALUE];
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mmio_write_32(addr, value);
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}
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} else {
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for (i = 0; i < NR_PTP3_CFG2_DATA; i++) {
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addr = ptp3_cfg2[i][PTP3_CFG_ADDR] + PTP3_CORE_OFT(core);
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if (i == 2) {
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value = ptp3_cfg2[i][PTP3_CFG_VALUE] + 0x5E0;
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} else {
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value = ptp3_cfg2[i][PTP3_CFG_VALUE];
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}
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mmio_write_32(addr, value);
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}
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}
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if (core < PTP3_CFG_CPU_START_ID_B) {
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addr = ptp3_cfg3[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core);
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value = ptp3_cfg3[PTP3_CFG_VALUE];
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} else {
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addr = ptp3_cfg3_ext[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core);
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value = ptp3_cfg3_ext[PTP3_CFG_VALUE];
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}
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mmio_write_32(addr, value & PTP3_CFG3_MASK1);
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mmio_write_32(addr, value & PTP3_CFG3_MASK2);
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mmio_write_32(addr, value & PTP3_CFG3_MASK3);
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}
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static void pdp_proc_arm_write(unsigned int pdp_n)
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{
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unsigned long v = 0;
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dsb();
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__asm__ volatile ("mrs %0, S3_6_C15_C2_0" : "=r" (v));
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v |= (UL(0x0) << 52);
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v |= (UL(0x1) << 53);
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v |= (UL(0x0) << 54);
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v |= (UL(0x0) << 48);
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v |= (UL(0x1) << 49);
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__asm__ volatile ("msr S3_6_C15_C2_0, %0" : : "r" (v));
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dsb();
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}
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static void pdp_init(unsigned int pdp_cpu)
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{
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if ((pdp_cpu >= PTP3_CFG_CPU_START_ID_B) && (pdp_cpu < NR_PTP3_CFG_CPU)) {
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pdp_proc_arm_write(pdp_cpu);
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}
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}
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void ptp3_core_init(unsigned int core)
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{
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ptp3_init(core);
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pdp_init(core);
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}
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void ptp3_core_deinit(unsigned int core)
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{
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/* TBD */
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}
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#if MTK_PUBEVENT_ENABLE
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/* Handle for power on domain */
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void *ptp3_handle_pwr_on_event(const void *arg)
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{
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if (arg != NULL) {
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struct mt_cpupm_event_data *data = (struct mt_cpupm_event_data *)arg;
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if ((data->pwr_domain & MT_CPUPM_PWR_DOMAIN_CORE) > 0) {
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ptp3_core_init(data->cpuid);
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}
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}
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return (void *)arg;
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}
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MT_CPUPM_SUBCRIBE_EVENT_PWR_ON(ptp3_handle_pwr_on_event);
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/* Handle for power off domain */
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void *ptp3_handle_pwr_off_event(const void *arg)
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{
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if (arg != NULL) {
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struct mt_cpupm_event_data *data = (struct mt_cpupm_event_data *)arg;
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if ((data->pwr_domain & MT_CPUPM_PWR_DOMAIN_CORE) > 0) {
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ptp3_core_deinit(data->cpuid);
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}
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}
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return (void *)arg;
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}
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MT_CPUPM_SUBCRIBE_EVENT_PWR_OFF(ptp3_handle_pwr_off_event);
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#else
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#pragma message "PSCI hint not enable"
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#endif
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