385 lines
9.5 KiB
C
385 lines
9.5 KiB
C
/*
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* Copyright (c) LOTUS. All rights reserved.
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*/
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#include <asm/arch/platform.h>
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#include <linux/lotus/chip.h>
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#include <common.h>
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#include <malloc.h>
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#include <sdhci.h>
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#include "mmc_private.h"
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#define MIN_FREQ 400000
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#define NOT_FOUND (-1)
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#ifdef CONFIG_LOTUS_FPGA
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#define PHASE_SCALE 8
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#define EDGE_TUNING_PHASE_STEP 1
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#else
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#define PHASE_SCALE 32
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#define EDGE_TUNING_PHASE_STEP 4
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#endif
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#define SDIO_DRV_DLL_SRST_REQ (0x1 << 29)
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#define SDIO_CLK_EN (0x1 << 28)
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#define SDIO_SRST_REQ (0x1 << 27)
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#define SDIO_CLK_SEL (0x7 << 24)
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#define SDIO_CLK_SEL_400K (0x1 << 24)
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#define REG_EMMC_DRV_DLL_STATUS (CRG_REG_BASE + 0x210)
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#define REG_SDIO0_DRV_DLL_STATUS (CRG_REG_BASE + 0x228)
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#define REG_SDIO1_DRV_DLL_STATUS (CRG_REG_BASE + 0x23c)
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#define SDIO_DRV_DLL_LOCK BIT(15)
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#define SDIO_DRV_DLL_READY BIT(14)
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#define REG_EMMC_SAMPL_DLL_STATUS (CRG_REG_BASE + 0x208)
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#define REG_SDIO0_SAMPL_DLL_STATUS (CRG_REG_BASE + 0x224)
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#define REG_SDIO1_SAMPL_DLL_STATUS (CRG_REG_BASE + 0x238)
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#define SDIO_SAMPL_DLL_SLAVE_READY BIT(0)
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#define REG_EMMC_SAMPL_DLL_CTRL (CRG_REG_BASE + 0x1f4)
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#define REG_SDIO0_SAMPL_DLL_CTRL (CRG_REG_BASE + 0x22c)
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#define REG_SDIO1_SAMPL_DLL_CTRL (CRG_REG_BASE + 0x240)
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#define SDIO_SAMPL_DLL_SLAVE_EN BIT(16)
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#define REG_EMMC_SAMPLB_DLL_CTRL (CRG_REG_BASE + 0x1f8)
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#define EMMC_SAMPLB_DLL_CLK_MASK (0x1f << 0)
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#define emmc_samplb_sel(phase) ((phase) << 0)
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#define REG_SDIO0_SAMPLB_DLL_CTRL (CRG_REG_BASE + 0x21c)
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#define REG_SDIO1_SAMPLB_DLL_CTRL (CRG_REG_BASE + 0x230)
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#define SDIO_SAMPLB_DLL_CLK_MASK (0x1f << 24)
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#define sdio_samplb_sel(phase) ((phase) << 24)
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#define REG_EMMC_DRV_DLL_CTRL (CRG_REG_BASE + 0x1fc)
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#define REG_SDIO0_DRV_DLL_CTRL (CRG_REG_BASE + 0x220)
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#define REG_SDIO1_DRV_DLL_CTRL (CRG_REG_BASE + 0x234)
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#define SDIO_DRV_PHASE_SEL_MASK (0x1f << 24)
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#define sdio_drv_sel(phase) ((phase) << 24)
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#define REG_EMMC_DS_DLL_CTRL (CRG_REG_BASE + 0x200)
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#define EMMC_DS_DLL_MODE_SSEL BIT(13)
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#define EMMC_DS_DLL_SSEL_MASK 0x7f
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#define REG_EMMC_DS180_DLL_CTRL (CRG_REG_BASE + 0x204)
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#define EMMC_DS180_DLL_BYPASS BIT(15)
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#define REG_EMMC_DS180_DLL_STATUS (CRG_REG_BASE + 0x218)
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#define EMMC_DS180_DLL_READY BIT(0)
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#define CLK_100K 100000
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#define CLK_400K 400000
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#define CLK_25M 25000000
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#define CLK_50M 50000000
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#define CLK_90M 90000000
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static void enable_sample(struct sdhci_host *host);
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static void set_drv_phase(struct sdhci_host *host, unsigned int phase);
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static void set_sampl_phase(struct sdhci_host *host, unsigned int phase);
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static void wait_sampl_dll_slave_ready(struct sdhci_host *host);
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static void enable_card_clk(struct sdhci_host *host);
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static void enable_internal_clk(struct sdhci_host *host);
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static void disable_internal_clk(struct sdhci_host *host);
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static void dll_reset_assert(struct sdhci_host *host)
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{
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uintptr_t crg_addr;
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unsigned int reg;
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crg_addr = (host->type == MMC_TYPE_MMC) ?
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REG_EMMC_CRG : REG_SDIO0_CRG;
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reg = readl(crg_addr);
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reg |= SDIO_DRV_DLL_SRST_REQ;
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writel(reg, crg_addr);
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}
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static void dll_reset_deassert(struct sdhci_host *host)
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{
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uintptr_t crg_addr;
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unsigned int reg;
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crg_addr = (host->type == MMC_TYPE_MMC) ?
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REG_EMMC_CRG : REG_SDIO0_CRG;
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reg = readl(crg_addr);
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reg &= ~SDIO_DRV_DLL_SRST_REQ;
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writel(reg, crg_addr);
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}
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static void set_crg(struct sdhci_host *host, unsigned int clk)
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{
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uintptr_t crg_addr;
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unsigned int sel, reg;
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unsigned int clk_mux[] = {
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CLK_100K, CLK_400K, CLK_25M, CLK_50M, CLK_90M,
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};
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crg_addr = (host->type == MMC_TYPE_MMC) ?
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REG_EMMC_CRG : REG_SDIO0_CRG;
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reg = readl(crg_addr);
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reg &= ~MMC_CLK_SEL_MASK;
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if (clk <= MIN_FREQ) {
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sel = 1;
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} else {
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for (sel = 0x4; sel > 0; sel--) {
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if (clk >= clk_mux[sel])
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break;
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}
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}
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reg |= mmc_clk_sel(sel);
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writel(reg, crg_addr);
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}
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static void wait_ds180_dll_ready(void)
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{
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unsigned int reg;
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unsigned int timeout = 20;
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do {
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reg = readl(REG_EMMC_DS180_DLL_STATUS);
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if (reg & EMMC_DS180_DLL_READY)
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return;
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udelay(1000); /* delay 1000us */
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timeout--;
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} while (timeout > 0);
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printf("DS180 DLL master not ready.\n");
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}
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static void lotus_mmc_priv_init(struct sdhci_host *host)
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{
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unsigned short ctrl;
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unsigned int reg;
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ctrl = sdhci_readw(host, SDHCI_MSHC_CTRL);
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ctrl &= ~SDHCI_CMD_CONFLIT_CHECK;
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sdhci_writew(host, ctrl, SDHCI_MSHC_CTRL);
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reg = sdhci_readl(host, SDHCI_AXI_MBIIU_CTRL);
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reg |= SDHCI_GM_WR_OSRC_LMT | SDHCI_GM_RD_OSRC_LMT;
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reg &= ~SDHCI_UNDEFL_INCR_EN;
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sdhci_writel(host, reg, SDHCI_AXI_MBIIU_CTRL);
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reg = sdhci_readl(host, SDHCI_MULTI_CYCLE);
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reg &= ~SDHCI_CMD_DLY_EN;
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reg |= SDHCI_EDGE_DETECT_EN | SDHCI_DATA_DLY_EN;
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sdhci_writel(host, reg, SDHCI_MULTI_CYCLE);
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if (host->type == MMC_TYPE_MMC) {
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/*add opt emmc reset gpio*/
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reg = sdhci_readl(host, SDHCI_GP_OUT_R);
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reg &= ~SDHCI_MMC_RESET_N;
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sdhci_writel(host, reg, SDHCI_GP_OUT_R);
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mdelay(1);
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reg |= SDHCI_MMC_RESET_N;
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sdhci_writel(host, reg, SDHCI_GP_OUT_R);
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mdelay(1);
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}
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}
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static int sd_hardware_init(void)
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{
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unsigned int reg;
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/* clk enable */
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reg = readl(REG_SDIO0_CRG);
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reg |= SDIO_CLK_EN;
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writel(reg, REG_SDIO0_CRG);
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/* reset assert */
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reg = readl(REG_SDIO0_CRG);
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reg |= SDIO_SRST_REQ | SDIO_DRV_DLL_SRST_REQ;
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writel(reg, REG_SDIO0_CRG);
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udelay(25); /* delay 25us */
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/* reset deassert */
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reg &= ~SDIO_SRST_REQ;
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writel(reg, REG_SDIO0_CRG);
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udelay(1); /* delay 1us */
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udelay(5000); /* delay 5000us */
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return 0;
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}
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static int emmc_hardware_init(void)
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{
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unsigned int reg;
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/* eMMC clk enable */
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reg = readl(REG_EMMC_CRG);
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reg |= SDIO_CLK_EN;
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writel(reg, REG_EMMC_CRG);
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/* eMMC reset assert */
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reg = readl(REG_EMMC_CRG);
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reg |= SDIO_SRST_REQ | SDIO_DRV_DLL_SRST_REQ;
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writel(reg, REG_EMMC_CRG);
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udelay(25); /* delay 25us */
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/* select 400K clk */
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reg = readl(REG_EMMC_CRG);
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reg &= ~SDIO_CLK_SEL;
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reg |= SDIO_CLK_SEL_400K;
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writel(reg, REG_EMMC_CRG);
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udelay(25); /* delay 25us */
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/* eMMC reset deassert */
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reg = readl(REG_EMMC_CRG);
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reg &= ~SDIO_SRST_REQ;
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writel(reg, REG_EMMC_CRG);
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udelay(1); /* delay 1us */
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return 0;
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}
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static void lotus_mmc_set_ioconfig(struct sdhci_host *host)
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{
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unsigned int reg;
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if (host->type == MMC_TYPE_MMC) {
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reg = sdhci_readw(host, SDHCI_EMMC_CTRL);
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reg |= SDHCI_CARD_IS_EMMC;
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sdhci_writew(host, reg, SDHCI_EMMC_CTRL);
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if (host->mmc->selected_mode == MMC_DDR_52) {
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reg = sdhci_readw(host, SDHCI_MULTI_CYCLE);
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reg &= ~SDHCI_DATA_DLY_EN;
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sdhci_writew(host, reg, SDHCI_MULTI_CYCLE);
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}
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}
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sdhci_set_uhs_timing(host);
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}
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static void set_phase(struct sdhci_host *host)
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{
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unsigned int drv_phase, sample_phase;
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#ifdef CONFIG_LOTUS_FPGA
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unsigned int fix_num = 4;
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#else
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unsigned int fix_num = 1;
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#endif
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if (host->mmc->selected_mode == MMC_HS_400_ES ||
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host->mmc->selected_mode == MMC_HS_400) {
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drv_phase = 8/fix_num; /* 8 for 90 degree */
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sample_phase = host->tuning_phase/fix_num;
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} else if (host->mmc->selected_mode == MMC_HS_200 ||
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host->mmc->selected_mode == UHS_SDR104) {
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drv_phase = 20/fix_num; /* 20 for 225 degree */
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sample_phase = host->tuning_phase/fix_num;
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} else if (host->mmc->selected_mode == UHS_SDR50) {
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drv_phase = 16/fix_num; /* 16 for 180 degree */
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sample_phase = host->tuning_phase/fix_num;
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} else if (host->mmc->selected_mode == MMC_DDR_52 ||
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host->mmc->selected_mode == UHS_DDR50) {
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drv_phase = 8/fix_num; /* 8 for 90 degree */
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sample_phase = 4/fix_num; /* 4 for 45 degree */
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} else if (host->mmc->selected_mode == MMC_HS ||
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host->mmc->selected_mode == MMC_HS_52) {
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drv_phase = 16/fix_num; /* 16 for 180 degree */
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sample_phase = 4/fix_num; /* 4 for 45 degree */
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} else if (host->mmc->selected_mode == UHS_SDR25 ||
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host->mmc->selected_mode == SD_HS) {
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drv_phase = 16/fix_num; /* 16 for 180 degree */
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sample_phase = 4/fix_num; /* 4 for 45 degree */
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} else {
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drv_phase = 16/fix_num; /* 16 for 180 degree */
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sample_phase = 0; /* 0 for 0 degree */
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}
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set_drv_phase(host, drv_phase);
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enable_sample(host);
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set_sampl_phase(host, sample_phase);
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udelay(25); /* delay 25us */
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}
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static void wait_drv_dll_lock(const struct sdhci_host *host)
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{
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unsigned int timeout = 20;
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unsigned int reg;
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uintptr_t reg_addr;
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reg_addr = (host->type == MMC_TYPE_MMC) ?
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REG_EMMC_DRV_DLL_STATUS : REG_SDIO0_DRV_DLL_STATUS;
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do {
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reg = readl(reg_addr);
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if (reg & SDIO_DRV_DLL_LOCK)
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return;
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udelay(1000); /* delay 1000us */
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timeout--;
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} while (timeout > 0);
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printf("sdhci: DRV DLL master not locked.\n");
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}
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static void enable_sampl_dll_slave(struct sdhci_host *host)
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{
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unsigned int reg;
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uintptr_t reg_addr;
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reg_addr = (host->type == MMC_TYPE_MMC) ?
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REG_EMMC_SAMPL_DLL_CTRL : REG_SDIO0_SAMPL_DLL_CTRL;
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reg = readl(reg_addr);
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reg |= SDIO_SAMPL_DLL_SLAVE_EN;
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writel(reg, reg_addr);
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}
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static int lotus_mmc_set_clk(struct sdhci_host *host, unsigned int clk)
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{
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dll_reset_assert(host);
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udelay(25); /* delay 25us */
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set_crg(host, clk);
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set_phase(host);
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udelay(25); /* delay 25us */
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if (clk > MMC_HIGH_52_MAX_DTR) {
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enable_sampl_dll_slave(host);
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dll_reset_deassert(host);
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}
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enable_internal_clk(host);
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if (clk > MMC_HIGH_52_MAX_DTR) {
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wait_drv_dll_lock(host);
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wait_sampl_dll_slave_ready(host);
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wait_ds180_dll_ready();
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}
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enable_card_clk(host);
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udelay(100); /* delay 100us */
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return 0;
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}
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static int lotus_set_io_cfg(struct sdhci_host *host, unsigned int cfg)
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{
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unsigned int reg;
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if (host->type != MMC_TYPE_MMC) {//only sd card
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if (cfg) {
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reg = readl(0x11980040);
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reg &= ~(0xf);
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reg |= (0x01);
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writel(reg, 0x11980040);
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} else {
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reg = readl(0x11980040);
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reg &= ~(0xf);
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reg |= (0x00);
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writel(reg, 0x11980040);
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//gpio3_0
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writel(0x01, 0x120b3400);
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writel(0x00, 0x120b3004);
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}
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}
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return 0;
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}
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#include "lotus_sdhci.c"
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