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提交海思SDK源码及驱动配置

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xu
2026-09-07 20:06:04 +08:00
parent a11e57a97e
commit 879184b6f1
3614 changed files with 92981 additions and 206204 deletions
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mpp/sample/it66021/bin/IT66021_MEGAWIN_V101_140911.hex
+2546 -2546
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File diff suppressed because it is too large Load Diff
mpp/sample/it66021/it66021_megawin.Uv2
+151 -151
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@@ -1,151 +1,151 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (MEGAWINE), 0x0000 // Tools: 'MCS-51'
Group (Source Group 1)
File 1,1,<.\src\IO.c><IO.c> 0x0
File 1,1,<.\src\Utility.c><Utility.c> 0x0
File 1,1,<.\src\Main.c><Main.c> 0x0
File 1,1,<.\src\Remote.c><Remote.c> 0x0
File 1,1,<.\src\it6602.c><it6602.c> 0x0
File 1,1,<.\src\it6602_cec.c><it6602_cec.c> 0x0
Options 1,0,0 // Target 'MEGAWINE'
Device (MPC82E52A)
Vendor (Megawin)
Cpu (IRAM(0 - 0xFF) IROM(0 - 0x1FFF) CLOCK(45000000))
FlashUt ()
StupF ("LIB\STARTUP.A51" ("Standard 8051 Startup Code"))
FlashDR ()
DevID ()
Rgf (REG89xx.H)
Mem ()
C ()
A ()
RL ()
OH ()
DBC_IFX ()
DBC_CMS ()
DBC_AMS ()
DBC_LMS ()
UseEnv=0
EnvBin ()
EnvInc ()
EnvLib ()
EnvReg (ÿMegawin\)
OrgReg (ÿMegawin\)
TgStat=16
OutDir (.\bin\)
OutName (IT66021_MEGAWIN_V101_140911)
GenApp=1
GenLib=0
GenHex=1
Debug=1
Browse=1
LstDir (.\lst\)
HexSel=0
MG32K=0
TGMORE=0
RunUsr 0 0 <>
RunUsr 1 0 <>
BrunUsr 0 0 <>
BrunUsr 1 0 <>
SVCSID <>
MODEL5=2
RTOS5=0
ROMSZ5=2
DHOLD5=0
XHOLD5=0
T51FL=80
XT51FL=0
CBANKS5=0
XBANKS5=0
RCB51 { 0,0,0,0,0,255,255,0,0 }
RXB51 { 0,0,0,0,0,0,0,0,0 }
OCM51 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
OCR51 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
IRO51 { 1,0,0,0,0,0,32,0,0 }
IRA51 { 0,0,0,0,0,0,1,0,0 }
XRA51 { 0,0,0,0,0,0,0,0,0 }
XRA512 { 0,0,0,0,0,0,0,0,0 }
IROM512 { 0,0,0,0,0,0,0,0,0 }
C51FL=21630224
C51VA=0
C51MSC ()
C51DEF ( _IT66021_ _MCU_ _MCU8051_)
C51UDF ()
INCC5 ()
AX51FL=4
AX51MSC ()
AX51SET ()
AX51RST ()
INCA5 ()
PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
IncBld=1
AlwaysBuild=0
GenAsm=0
AsmAsm=0
PublicsOnly=0
StopCode=3
CustArgs ()
LibMods ()
BankNo=65535
LX51FL=292
LX51OVL ()
LX51MSC ()
LX51DWN (16)
LX51LFI ()
LX51ASN ()
LX51RES ()
LX51CCL ()
LX51UCL ()
LX51CSC ()
LX51UCS ()
LX51COB ()
LX51XDB ()
LX51PDB ()
LX51BIB ()
LX51DAB ()
LX51IDB ()
LX51PRC ()
LX51STK ()
LX51COS ()
LX51XDS ()
LX51BIS ()
LX51DAS ()
LX51IDS ()
OPTDL (S8051.DLL)()(DP51.DLL)(-p52)(S8051.DLL)()(TP51.DLL)(-p52)
OPTDBG 48117,-1,()()()()()()()()()() ()()()()
FLASH1 { 1,0,0,0,0,0,0,0,255,255,255,255,0,0,0,0,0,0,0,0 }
FLASH2 ()
FLASH3 ()
FLASH4 ()
EndOpt
Options 1,1,0 // Group 'Source Group 1'
PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
IncBld=2
AlwaysBuild=2
GenAsm=2
AsmAsm=2
PublicsOnly=2
StopCode=11
CustArgs ()
LibMods ()
BankNo=65535
C51FL=177119914
C51VA=0
C51MSC ()
C51DEF ()
C51UDF ()
INCC5 ()
AX51FL=170
AX51MSC ()
AX51SET ()
AX51RST ()
INCA5 ()
EndOpt
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (MEGAWINE), 0x0000 // Tools: 'MCS-51'
Group (Source Group 1)
File 1,1,<.\src\IO.c><IO.c> 0x0
File 1,1,<.\src\Utility.c><Utility.c> 0x0
File 1,1,<.\src\Main.c><Main.c> 0x0
File 1,1,<.\src\Remote.c><Remote.c> 0x0
File 1,1,<.\src\it6602.c><it6602.c> 0x0
File 1,1,<.\src\it6602_cec.c><it6602_cec.c> 0x0
Options 1,0,0 // Target 'MEGAWINE'
Device (MPC82E52A)
Vendor (Megawin)
Cpu (IRAM(0 - 0xFF) IROM(0 - 0x1FFF) CLOCK(45000000))
FlashUt ()
StupF ("LIB\STARTUP.A51" ("Standard 8051 Startup Code"))
FlashDR ()
DevID ()
Rgf (REG89xx.H)
Mem ()
C ()
A ()
RL ()
OH ()
DBC_IFX ()
DBC_CMS ()
DBC_AMS ()
DBC_LMS ()
UseEnv=0
EnvBin ()
EnvInc ()
EnvLib ()
EnvReg (ÿMegawin\)
OrgReg (ÿMegawin\)
TgStat=16
OutDir (.\bin\)
OutName (IT66021_MEGAWIN_V101_140911)
GenApp=1
GenLib=0
GenHex=1
Debug=1
Browse=1
LstDir (.\lst\)
HexSel=0
MG32K=0
TGMORE=0
RunUsr 0 0 <>
RunUsr 1 0 <>
BrunUsr 0 0 <>
BrunUsr 1 0 <>
SVCSID <>
MODEL5=2
RTOS5=0
ROMSZ5=2
DHOLD5=0
XHOLD5=0
T51FL=80
XT51FL=0
CBANKS5=0
XBANKS5=0
RCB51 { 0,0,0,0,0,255,255,0,0 }
RXB51 { 0,0,0,0,0,0,0,0,0 }
OCM51 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
OCR51 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
IRO51 { 1,0,0,0,0,0,32,0,0 }
IRA51 { 0,0,0,0,0,0,1,0,0 }
XRA51 { 0,0,0,0,0,0,0,0,0 }
XRA512 { 0,0,0,0,0,0,0,0,0 }
IROM512 { 0,0,0,0,0,0,0,0,0 }
C51FL=21630224
C51VA=0
C51MSC ()
C51DEF ( _IT66021_ _MCU_ _MCU8051_)
C51UDF ()
INCC5 ()
AX51FL=4
AX51MSC ()
AX51SET ()
AX51RST ()
INCA5 ()
PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
IncBld=1
AlwaysBuild=0
GenAsm=0
AsmAsm=0
PublicsOnly=0
StopCode=3
CustArgs ()
LibMods ()
BankNo=65535
LX51FL=292
LX51OVL ()
LX51MSC ()
LX51DWN (16)
LX51LFI ()
LX51ASN ()
LX51RES ()
LX51CCL ()
LX51UCL ()
LX51CSC ()
LX51UCS ()
LX51COB ()
LX51XDB ()
LX51PDB ()
LX51BIB ()
LX51DAB ()
LX51IDB ()
LX51PRC ()
LX51STK ()
LX51COS ()
LX51XDS ()
LX51BIS ()
LX51DAS ()
LX51IDS ()
OPTDL (S8051.DLL)()(DP51.DLL)(-p52)(S8051.DLL)()(TP51.DLL)(-p52)
OPTDBG 48117,-1,()()()()()()()()()() ()()()()
FLASH1 { 1,0,0,0,0,0,0,0,255,255,255,255,0,0,0,0,0,0,0,0 }
FLASH2 ()
FLASH3 ()
FLASH4 ()
EndOpt
Options 1,1,0 // Group 'Source Group 1'
PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
IncBld=2
AlwaysBuild=2
GenAsm=2
AsmAsm=2
PublicsOnly=2
StopCode=11
CustArgs ()
LibMods ()
BankNo=65535
C51FL=177119914
C51VA=0
C51MSC ()
C51DEF ()
C51UDF ()
INCC5 ()
AX51FL=170
AX51MSC ()
AX51SET ()
AX51RST ()
INCA5 ()
EndOpt
mpp/sample/it66021/ite66021.zip
Executable → Regular
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mpp/sample/it66021/src/515XRAM.H
+24 -24
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@@ -1,24 +1,24 @@
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <515XRAM.H>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifndef _515xram_
#define _515xram_
/*
#define MySon
#ifdef MySon
extern // xdata PADMOD0 _at_ 0x0f50;
extern // xdata PORT4OE _at_ 0x0f57;
#else
#endif
*/
#endif
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <515XRAM.H>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifndef _515xram_
#define _515xram_
/*
#define MySon
#ifdef MySon
extern // xdata PADMOD0 _at_ 0x0f50;
extern // xdata PORT4OE _at_ 0x0f57;
#else
#endif
*/
#endif
mpp/sample/it66021/src/IO.c
+376 -376
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@@ -1,376 +1,376 @@
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <IO.c>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#include "config.h"
#include "MCU.h"
//#include "nop.h"
#include <stdio.h>
#ifdef _Myson_CS8957_
BYTE xdata PADMOD0 _at_ 0x0f50;
BYTE xdata PORT4OE _at_ 0x0f57;
BYTE xdata PORT40 _at_ 0x0f58;
BYTE xdata PORT41 _at_ 0x0f59;
BYTE xdata PORT42 _at_ 0x0f5A;
BYTE xdata PORT43 _at_ 0x0f5B;
BYTE xdata PORT44 _at_ 0x0f5C;
void InitMysonIO()
{
PADMOD0 = 0;
PORT4OE = 0x00;
PORT40 = 0;
PORT42 = 0;
PORT43 = 0;
}
#endif
//BYTE idata I2CDEV=0;
///////////////////////////////////////////////////////////////////////////////
//IO Pin Config For I2C control
//
//
//
//
///////////////////////////////////////////////////////////////////////////////
#ifdef _IT6602_BOARD_
sbit DEV0_SCL_PORT = P1^0;
sbit DEV0_SDA_PORT = P1^1;
sbit DEV1_SCL_PORT = P1^2;
sbit DEV1_SDA_PORT = P1^3;
sbit DEV2_SCL_PORT = P1^5;
sbit DEV2_SDA_PORT = P1^6;
sbit DEV3_SCL_PORT = P1^0;
sbit DEV3_SDA_PORT = P1^1;
sbit DEV4_SCL_PORT = P1^2;
sbit DEV4_SDA_PORT = P1^3;
#else
sbit DEV0_SCL_PORT = P0^0;
sbit DEV0_SDA_PORT = P0^1;
sbit DEV1_SCL_PORT = P0^2;
sbit DEV1_SDA_PORT = P0^3;
sbit DEV2_SCL_PORT = P0^5;
sbit DEV2_SDA_PORT = P0^6;
sbit DEV3_SCL_PORT = P0^0;
sbit DEV3_SDA_PORT = P0^1;
sbit DEV4_SCL_PORT = P0^2;
sbit DEV4_SDA_PORT = P0^3;
#endif
////////////////////////////////////////////////////////////////////////////////////////
//
////////////////////////////////////////////////////////////////////////////////////////
void HotPlug(BYTE bEnable)
{
if(bEnable)
gpHPD0 = HPDON;
else
gpHPD0 = HPDOFF;
}
void SetintActive(BOOL bactive)
{
bactive =0; //fake code
}
void set_8051_scl( BOOL bit_value,BYTE device )
{
// stall5us ;
switch(device)
{
case 0:
DEV0_SCL_PORT=bit_value;
break;
case 1:
DEV1_SCL_PORT=bit_value;
break;
case 2:
DEV2_SCL_PORT=bit_value;
break;
case 3:
DEV3_SCL_PORT=bit_value;
break;
case 4:
DEV4_SCL_PORT=bit_value;
break;
default:
DEV0_SCL_PORT=bit_value;
break;
}
// stall5us ;
}
void set_8051_sda( BOOL bit_value,BYTE device )
{
// stall5us ;
switch( device )
{
case 0:
DEV0_SDA_PORT=bit_value;
break;
case 1:
DEV1_SDA_PORT=bit_value;
break;
case 2:
DEV2_SDA_PORT=bit_value;
break;
case 3:
DEV3_SDA_PORT=bit_value;
break;
case 4:
DEV4_SDA_PORT=bit_value;
break;
default:
DEV0_SDA_PORT=bit_value;
break;
}
// stall5us ;
}
BOOL get_8051_sda( BYTE device )
{
switch( device )
{
case 0:
DEV0_SDA_PORT=1;
return DEV0_SDA_PORT;
break;
case 1:
DEV1_SDA_PORT=1;
return DEV1_SDA_PORT;
break;
case 2:
DEV2_SDA_PORT=1;
return DEV2_SDA_PORT;
break;
case 3:
DEV3_SDA_PORT=1;
return DEV3_SDA_PORT;
break;
case 4:
DEV4_SDA_PORT=1;
return DEV4_SDA_PORT;
break;
default:
DEV0_SDA_PORT=1;
return DEV0_SDA_PORT;
break;
}
}
void i2c_8051_start( BYTE device )
{
set_8051_sda( HIGH ,device);
set_8051_scl( HIGH ,device);
set_8051_sda( LOW ,device);
set_8051_scl( LOW ,device);
}
void i2c_8051_write( BYTE byte_data,BYTE device )
{
BYTE data bit_cnt,tmp;
BOOL data bit_value;
for(bit_cnt=0; bit_cnt<8; bit_cnt++) {
tmp=(byte_data << bit_cnt) & 0x80;
bit_value=tmp && 0x80;
set_8051_sda( bit_value,device);
set_8051_scl( HIGH ,device);
set_8051_scl( LOW ,device);
}
}
BOOL i2c_8051_wait_ack( BYTE device )
{
BOOL data ack_bit_value;
set_8051_sda( HIGH,device );
set_8051_scl( HIGH,device );
ack_bit_value=get_8051_sda( device );
set_8051_scl( LOW ,device);
return ack_bit_value;
}
BYTE i2c_8051_read( BYTE device )
{
BYTE data bit_cnt,byte_data;
BOOL data bit_value;
byte_data=0;
for(bit_cnt=0; bit_cnt<8; bit_cnt++) {
set_8051_scl( HIGH,device );
bit_value=get_8051_sda( device );
byte_data=(byte_data << 1) | bit_value;
set_8051_scl( LOW,device );
}
return byte_data;
}
void i2c_8051_send_ack( BOOL bit_value,BYTE device )
{
set_8051_sda( bit_value,device );
set_8051_scl( HIGH ,device);
set_8051_scl( LOW ,device);
set_8051_sda( HIGH,device );
}
void i2c_8051_end( BYTE device )
{
set_8051_sda( LOW,device );
set_8051_scl( HIGH,device );
set_8051_sda( HIGH,device );
}
BOOL i2c_write_byte( BYTE address,BYTE offset,BYTE byteno,BYTE *p_data,BYTE device )
{
BYTE data i;
i2c_8051_start(device);
i2c_8051_write(address&0xFE,device);
if( i2c_8051_wait_ack(device)==1 ) {
i2c_8051_end(device);
return 0;
}
i2c_8051_write(offset,device);
if( i2c_8051_wait_ack(device)==1 ) {
i2c_8051_end(device);
return 0;
}
for(i=0; i<byteno-1; i++) {
i2c_8051_write(*p_data,device);
if( i2c_8051_wait_ack(device)==1 ) {
i2c_8051_end(device);
return 0;
}
p_data++;
}
i2c_8051_write(*p_data,device);
if( i2c_8051_wait_ack(device)==1 ) {
i2c_8051_end(device);
return 0;
}
else {
i2c_8051_end(device);
return 1;
}
}
BOOL i2c_read_byte( BYTE address,BYTE offset,BYTE byteno,BYTE *p_data,BYTE device )
{
BYTE data i;
i2c_8051_start(device);
i2c_8051_write(address&0xFE,device);
if( i2c_8051_wait_ack(device)==1 ) {
i2c_8051_end(device);
return 0;
}
i2c_8051_write(offset,device);
if( i2c_8051_wait_ack(device)==1 ) {
i2c_8051_end(device);
return 0;
}
i2c_8051_start(device);
i2c_8051_write(address|0x01,device);
if( i2c_8051_wait_ack(device)==1 ) {
i2c_8051_end(device);
return 0;
}
for(i=0; i<byteno-1; i++) {
*p_data=i2c_8051_read(device);
i2c_8051_send_ack(LOW,device);
p_data++;
}
*p_data=i2c_8051_read(device);
i2c_8051_send_ack(HIGH,device);
i2c_8051_end(device);
return 1;
}
///////////////////////////////////////////////////////////////////////////////////////
//IIC control Functions
//
///////////////////////////////////////////////////////////////////////////////////////
#ifdef Enable_IT6602_CEC
BYTE IT6602_CEC_ReadI2C_Byte(BYTE RegAddr)
{
BYTE p_data;
BOOL FLAG;
FLAG=i2c_read_byte(CEC_ADDR,RegAddr,1,&p_data,IT6602CECGPIOid);
if(FLAG==0)
{
CEC_DEBUG_PRINTF(("IT6602_CEC I2C ERROR !!!"));
CEC_DEBUG_PRINTF(("===== Read Reg0x%X= \n",RegAddr));
}
return p_data;
}
SYS_STATUS IT6602_CEC_WriteI2C_Byte(BYTE offset,BYTE buffer )
{
BOOL flag;
flag=i2c_write_byte(CEC_ADDR,offset,1,&buffer,IT6602CECGPIOid);
return !flag;
}
#endif
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <IO.c>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#include "config.h"
#include "MCU.h"
//#include "nop.h"
#include <stdio.h>
#ifdef _Myson_CS8957_
BYTE xdata PADMOD0 _at_ 0x0f50;
BYTE xdata PORT4OE _at_ 0x0f57;
BYTE xdata PORT40 _at_ 0x0f58;
BYTE xdata PORT41 _at_ 0x0f59;
BYTE xdata PORT42 _at_ 0x0f5A;
BYTE xdata PORT43 _at_ 0x0f5B;
BYTE xdata PORT44 _at_ 0x0f5C;
void InitMysonIO()
{
PADMOD0 = 0;
PORT4OE = 0x00;
PORT40 = 0;
PORT42 = 0;
PORT43 = 0;
}
#endif
//BYTE idata I2CDEV=0;
///////////////////////////////////////////////////////////////////////////////
//IO Pin Config For I2C control
//
//
//
//
///////////////////////////////////////////////////////////////////////////////
#ifdef _IT6602_BOARD_
sbit DEV0_SCL_PORT = P1^0;
sbit DEV0_SDA_PORT = P1^1;
sbit DEV1_SCL_PORT = P1^2;
sbit DEV1_SDA_PORT = P1^3;
sbit DEV2_SCL_PORT = P1^5;
sbit DEV2_SDA_PORT = P1^6;
sbit DEV3_SCL_PORT = P1^0;
sbit DEV3_SDA_PORT = P1^1;
sbit DEV4_SCL_PORT = P1^2;
sbit DEV4_SDA_PORT = P1^3;
#else
sbit DEV0_SCL_PORT = P0^0;
sbit DEV0_SDA_PORT = P0^1;
sbit DEV1_SCL_PORT = P0^2;
sbit DEV1_SDA_PORT = P0^3;
sbit DEV2_SCL_PORT = P0^5;
sbit DEV2_SDA_PORT = P0^6;
sbit DEV3_SCL_PORT = P0^0;
sbit DEV3_SDA_PORT = P0^1;
sbit DEV4_SCL_PORT = P0^2;
sbit DEV4_SDA_PORT = P0^3;
#endif
////////////////////////////////////////////////////////////////////////////////////////
//
////////////////////////////////////////////////////////////////////////////////////////
void HotPlug(BYTE bEnable)
{
if(bEnable)
gpHPD0 = HPDON;
else
gpHPD0 = HPDOFF;
}
void SetintActive(BOOL bactive)
{
bactive =0; //fake code
}
void set_8051_scl( BOOL bit_value,BYTE device )
{
// stall5us ;
switch(device)
{
case 0:
DEV0_SCL_PORT=bit_value;
break;
case 1:
DEV1_SCL_PORT=bit_value;
break;
case 2:
DEV2_SCL_PORT=bit_value;
break;
case 3:
DEV3_SCL_PORT=bit_value;
break;
case 4:
DEV4_SCL_PORT=bit_value;
break;
default:
DEV0_SCL_PORT=bit_value;
break;
}
// stall5us ;
}
void set_8051_sda( BOOL bit_value,BYTE device )
{
// stall5us ;
switch( device )
{
case 0:
DEV0_SDA_PORT=bit_value;
break;
case 1:
DEV1_SDA_PORT=bit_value;
break;
case 2:
DEV2_SDA_PORT=bit_value;
break;
case 3:
DEV3_SDA_PORT=bit_value;
break;
case 4:
DEV4_SDA_PORT=bit_value;
break;
default:
DEV0_SDA_PORT=bit_value;
break;
}
// stall5us ;
}
BOOL get_8051_sda( BYTE device )
{
switch( device )
{
case 0:
DEV0_SDA_PORT=1;
return DEV0_SDA_PORT;
break;
case 1:
DEV1_SDA_PORT=1;
return DEV1_SDA_PORT;
break;
case 2:
DEV2_SDA_PORT=1;
return DEV2_SDA_PORT;
break;
case 3:
DEV3_SDA_PORT=1;
return DEV3_SDA_PORT;
break;
case 4:
DEV4_SDA_PORT=1;
return DEV4_SDA_PORT;
break;
default:
DEV0_SDA_PORT=1;
return DEV0_SDA_PORT;
break;
}
}
void i2c_8051_start( BYTE device )
{
set_8051_sda( HIGH ,device);
set_8051_scl( HIGH ,device);
set_8051_sda( LOW ,device);
set_8051_scl( LOW ,device);
}
void i2c_8051_write( BYTE byte_data,BYTE device )
{
BYTE data bit_cnt,tmp;
BOOL data bit_value;
for(bit_cnt=0; bit_cnt<8; bit_cnt++) {
tmp=(byte_data << bit_cnt) & 0x80;
bit_value=tmp && 0x80;
set_8051_sda( bit_value,device);
set_8051_scl( HIGH ,device);
set_8051_scl( LOW ,device);
}
}
BOOL i2c_8051_wait_ack( BYTE device )
{
BOOL data ack_bit_value;
set_8051_sda( HIGH,device );
set_8051_scl( HIGH,device );
ack_bit_value=get_8051_sda( device );
set_8051_scl( LOW ,device);
return ack_bit_value;
}
BYTE i2c_8051_read( BYTE device )
{
BYTE data bit_cnt,byte_data;
BOOL data bit_value;
byte_data=0;
for(bit_cnt=0; bit_cnt<8; bit_cnt++) {
set_8051_scl( HIGH,device );
bit_value=get_8051_sda( device );
byte_data=(byte_data << 1) | bit_value;
set_8051_scl( LOW,device );
}
return byte_data;
}
void i2c_8051_send_ack( BOOL bit_value,BYTE device )
{
set_8051_sda( bit_value,device );
set_8051_scl( HIGH ,device);
set_8051_scl( LOW ,device);
set_8051_sda( HIGH,device );
}
void i2c_8051_end( BYTE device )
{
set_8051_sda( LOW,device );
set_8051_scl( HIGH,device );
set_8051_sda( HIGH,device );
}
BOOL i2c_write_byte( BYTE address,BYTE offset,BYTE byteno,BYTE *p_data,BYTE device )
{
BYTE data i;
i2c_8051_start(device);
i2c_8051_write(address&0xFE,device);
if( i2c_8051_wait_ack(device)==1 ) {
i2c_8051_end(device);
return 0;
}
i2c_8051_write(offset,device);
if( i2c_8051_wait_ack(device)==1 ) {
i2c_8051_end(device);
return 0;
}
for(i=0; i<byteno-1; i++) {
i2c_8051_write(*p_data,device);
if( i2c_8051_wait_ack(device)==1 ) {
i2c_8051_end(device);
return 0;
}
p_data++;
}
i2c_8051_write(*p_data,device);
if( i2c_8051_wait_ack(device)==1 ) {
i2c_8051_end(device);
return 0;
}
else {
i2c_8051_end(device);
return 1;
}
}
BOOL i2c_read_byte( BYTE address,BYTE offset,BYTE byteno,BYTE *p_data,BYTE device )
{
BYTE data i;
i2c_8051_start(device);
i2c_8051_write(address&0xFE,device);
if( i2c_8051_wait_ack(device)==1 ) {
i2c_8051_end(device);
return 0;
}
i2c_8051_write(offset,device);
if( i2c_8051_wait_ack(device)==1 ) {
i2c_8051_end(device);
return 0;
}
i2c_8051_start(device);
i2c_8051_write(address|0x01,device);
if( i2c_8051_wait_ack(device)==1 ) {
i2c_8051_end(device);
return 0;
}
for(i=0; i<byteno-1; i++) {
*p_data=i2c_8051_read(device);
i2c_8051_send_ack(LOW,device);
p_data++;
}
*p_data=i2c_8051_read(device);
i2c_8051_send_ack(HIGH,device);
i2c_8051_end(device);
return 1;
}
///////////////////////////////////////////////////////////////////////////////////////
//IIC control Functions
//
///////////////////////////////////////////////////////////////////////////////////////
#ifdef Enable_IT6602_CEC
BYTE IT6602_CEC_ReadI2C_Byte(BYTE RegAddr)
{
BYTE p_data;
BOOL FLAG;
FLAG=i2c_read_byte(CEC_ADDR,RegAddr,1,&p_data,IT6602CECGPIOid);
if(FLAG==0)
{
CEC_DEBUG_PRINTF(("IT6602_CEC I2C ERROR !!!"));
CEC_DEBUG_PRINTF(("===== Read Reg0x%X= \n",RegAddr));
}
return p_data;
}
SYS_STATUS IT6602_CEC_WriteI2C_Byte(BYTE offset,BYTE buffer )
{
BOOL flag;
flag=i2c_write_byte(CEC_ADDR,offset,1,&buffer,IT6602CECGPIOid);
return !flag;
}
#endif
mpp/sample/it66021/src/IO.h
+52 -52
View File
@@ -1,52 +1,52 @@
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <IO.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifndef _IO_h_
#define _IO_h_
#include "typedef.h"
#ifdef SUPPORT_UART_CMD
void UartCommand();
#endif
//BYTE HDMI_IIC_Read( BYTE RegAddr);
//BOOL HDMI_IIC_Write( BYTE RegAddr,BYTE DataIn);
//BYTE HDMI_IIC_SET( BYTE offset, BYTE mask, BYTE datain );
BOOL i2c_write_byte( BYTE address,BYTE offset,BYTE byteno,BYTE *p_data,BYTE device );
BOOL i2c_read_byte( BYTE address,BYTE offset,BYTE byteno,BYTE *p_data,BYTE device );
#ifdef Enable_IT6602_CEC
#include "debug.h"
BYTE IT6602_CEC_ReadI2C_Byte(BYTE RegAddr);
SYS_STATUS IT6602_CEC_WriteI2C_Byte(BYTE offset,BYTE buffer );
#endif
//#define hdmirxrd(x) HDMI_IIC_Read(x)
//#define hdmirxwr(x,y) HDMI_IIC_Write(x,y)
void SetEDIDWp(BOOL ENA);
void HotPlug(BYTE Enable);
void init_printf(void);
void SetintActive(BOOL bactive);
#endif
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <IO.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifndef _IO_h_
#define _IO_h_
#include "typedef.h"
#ifdef SUPPORT_UART_CMD
void UartCommand();
#endif
//BYTE HDMI_IIC_Read( BYTE RegAddr);
//BOOL HDMI_IIC_Write( BYTE RegAddr,BYTE DataIn);
//BYTE HDMI_IIC_SET( BYTE offset, BYTE mask, BYTE datain );
BOOL i2c_write_byte( BYTE address,BYTE offset,BYTE byteno,BYTE *p_data,BYTE device );
BOOL i2c_read_byte( BYTE address,BYTE offset,BYTE byteno,BYTE *p_data,BYTE device );
#ifdef Enable_IT6602_CEC
#include "debug.h"
BYTE IT6602_CEC_ReadI2C_Byte(BYTE RegAddr);
SYS_STATUS IT6602_CEC_WriteI2C_Byte(BYTE offset,BYTE buffer );
#endif
//#define hdmirxrd(x) HDMI_IIC_Read(x)
//#define hdmirxwr(x,y) HDMI_IIC_Write(x,y)
void SetEDIDWp(BOOL ENA);
void HotPlug(BYTE Enable);
void init_printf(void);
void SetintActive(BOOL bactive);
#endif
mpp/sample/it66021/src/Main.c
+87 -87
View File
@@ -1,87 +1,87 @@
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <Main.c>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#include "config.h"
#include "IO.h"
#include "Utility.h"
#include "version.h"
#include <stdio.h>
#include <string.h>
#include "it6602.h"
#include "it6602_reg.h"
char Firmware_date[] = __DATE__;
char Firmware_time[] = __TIME__;
void InitMessage();
////////////////////////////////////////////////////////
// InitMessage()
//
// init Urt control and print current Version string
//
//
////////////////////////////////////////////////////////
void InitMessage()
{
// init_printf();
printf("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
printf(" %s \n",VERSION_STRING);
printf(" %s \n",Firmware_date);
printf(" %s \n",Firmware_time);
#if defined(_IT6602_)
printf(" IT6602 \n");
#elif defined(_IT66023_)
printf(" IT66023 \n");
#else
printf(" IT66021 \n");
#endif
printf("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n");
}
////////////////////////////////////////////////////////
// main()
//
//
//
////////////////////////////////////////////////////////
void main( void )
{
USHORT loopinterval;
InitMessage();
open_i2c_fd();
delay1ms(1000); //for power sequence
IT6602_fsm_init();
while(1)
{
loopinterval += getloopTicCount();
if( loopinterval >=MS_LOOP) //execute once each 50m second
{
loopinterval =0;
IT6602_fsm();
}
}
}
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <Main.c>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#include "config.h"
#include "IO.h"
#include "Utility.h"
#include "version.h"
#include <stdio.h>
#include <string.h>
#include "it6602.h"
#include "it6602_reg.h"
char Firmware_date[] = __DATE__;
char Firmware_time[] = __TIME__;
void InitMessage();
////////////////////////////////////////////////////////
// InitMessage()
//
// init Urt control and print current Version string
//
//
////////////////////////////////////////////////////////
void InitMessage()
{
// init_printf();
printf("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
printf(" %s \n",VERSION_STRING);
printf(" %s \n",Firmware_date);
printf(" %s \n",Firmware_time);
#if defined(_IT6602_)
printf(" IT6602 \n");
#elif defined(_IT66023_)
printf(" IT66023 \n");
#else
printf(" IT66021 \n");
#endif
printf("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n");
}
////////////////////////////////////////////////////////
// main()
//
//
//
////////////////////////////////////////////////////////
void main( void )
{
USHORT loopinterval;
InitMessage();
open_i2c_fd();
delay1ms(1000); //for power sequence
IT6602_fsm_init();
while(1)
{
loopinterval += getloopTicCount();
if( loopinterval >=MS_LOOP) //execute once each 50m second
{
loopinterval =0;
IT6602_fsm();
}
}
}
mpp/sample/it66021/src/REG_MPC82G516.H
+323 -323
View File
@@ -1,323 +1,323 @@
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <REG_MPC82G516.H>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
/* for Megawin MPC82G516 */
/*-----------------------------------------------------------------------------
Standard SFRs
-----------------------------------------------------------------------------*/
/* 8051 Registers */
sfr P0 = 0x80;
sfr P1 = 0x90;
sfr P2 = 0xA0;
sfr P3 = 0xB0;
sfr PSW = 0xD0;
sfr ACC = 0xE0;
sfr B = 0xF0;
sfr SP = 0x81;
sfr DPL = 0x82;
sfr DPH = 0x83;
sfr PCON = 0x87;
sfr TCON = 0x88;
sfr TMOD = 0x89;
sfr TL0 = 0x8A;
sfr TL1 = 0x8B;
sfr TH0 = 0x8C;
sfr TH1 = 0x8D;
sfr IE = 0xA8;
sfr IP = 0xB8;
sfr SCON = 0x98;
sfr SBUF = 0x99;
// (PSW)
sbit CY = PSW^7;
sbit AC = PSW^6;
sbit F0 = PSW^5;
sbit RS1 = PSW^4;
sbit RS0 = PSW^3;
sbit OV = PSW^2;
sbit P = PSW^0;
// (TCON)
sbit TF1 = TCON^7;
sbit TR1 = TCON^6;
sbit TF0 = TCON^5;
sbit TR0 = TCON^4;
sbit IE1 = TCON^3;
sbit IT1 = TCON^2;
sbit IE0 = TCON^1;
sbit IT0 = TCON^0;
// (IE)
sbit EA = IE^7;
sbit ES = IE^4;
sbit ET1 = IE^3;
sbit EX1 = IE^2;
sbit ET0 = IE^1;
sbit EX0 = IE^0;
// (IP)
sbit PS = IP^4;
sbit PT1 = IP^3;
sbit PX1 = IP^2;
sbit PT0 = IP^1;
sbit PX0 = IP^0;
// (SCON)
sbit SM0 = SCON^7;
sbit SM1 = SCON^6;
sbit SM2 = SCON^5;
sbit REN = SCON^4;
sbit TB8 = SCON^3;
sbit RB8 = SCON^2;
sbit TI = SCON^1;
sbit RI = SCON^0;
// (P3)
sbit P37 = P3^7;
sbit P36 = P3^6;
sbit P35 = P3^5;
sbit P34 = P3^4;
sbit P33 = P3^3;
sbit P32 = P3^2;
sbit P31 = P3^1;
sbit P30 = P3^0;
// (P2)
sbit P27 = P2^7;
sbit P26 = P2^6;
sbit P25 = P2^5;
sbit P24 = P2^4;
sbit P23 = P2^3;
sbit P22 = P2^2;
sbit P21 = P2^1;
sbit P20 = P2^0;
// (P1)
sbit P17 = P1^7;
sbit P16 = P1^6;
sbit P15 = P1^5;
sbit P14 = P1^4;
sbit P13 = P1^3;
sbit P12 = P1^2;
sbit P11 = P1^1;
sbit P10 = P1^0;
// (P0)
sbit P07 = P0^7;
sbit P06 = P0^6;
sbit P05 = P0^5;
sbit P04 = P0^4;
sbit P03 = P0^3;
sbit P02 = P0^2;
sbit P01 = P0^1;
sbit P00 = P0^0;
// (P3 alternate)
sbit RD = P3^7;
sbit WR = P3^6;
sbit T1 = P3^5;
sbit T0 = P3^4;
sbit INT1 = P3^3;
sbit INT0 = P3^2;
sbit TXD = P3^1;
sbit RXD = P3^0;
/* 8052 Extensions */
sfr T2CON = 0xC8;
sfr RCAP2L = 0xCA;
sfr RCAP2H = 0xCB;
sfr TL2 = 0xCC;
sfr TH2 = 0xCD;
// (IE)
sbit ET2 = IE^5;
// (IP)
sbit PT2 = IP^5;
// (T2CON)
sbit TF2 = T2CON^7;
sbit EXF2 = T2CON^6;
sbit RCLK = T2CON^5;
sbit TCLK = T2CON^4;
sbit EXEN2 = T2CON^3;
sbit TR2 = T2CON^2;
sbit C_T2 = T2CON^1;
sbit CP_RL2= T2CON^0;
// (P1 alternate)
sbit T2EX = P1^1;
sbit T2 = P1^0;
/*-----------------------------------------------------------------------------
New-defined SFRs
-----------------------------------------------------------------------------*/
/* MPC82G516 Extensions */
sfr AUXR = 0x8E;
sfr AUXR1 = 0xA2;
sfr SADDR = 0xA9;
sfr SADEN = 0xB9;
sfr WDTCR = 0xE1;
sfr PCON2 = 0xC7;
sfr EVRCR = 0x97;
sfr STRETCH= 0x8F;
sfr AUXR2 = 0xA6;
// for I/O
sfr P4 = 0xE8;
sfr P0M0 = 0x93;
sfr P0M1 = 0x94;
sfr P1M0 = 0x91;
sfr P1M1 = 0x92;
sfr P2M0 = 0x95;
sfr P2M1 = 0x96;
sfr P3M0 = 0xB1;
sfr P3M1 = 0xB2;
sfr P4M0 = 0xB3;
sfr P4M1 = 0xB4;
// for ISP
sfr IFD = 0xE2;
sfr IFADRH = 0xE3;
sfr IFADRL = 0xE4;
sfr IFMT = 0xE5;
sfr SCMD = 0xE6;
sfr ISPCR = 0xE7;
// for interrupt
sfr XICON = 0xC0;
sfr AUXIE = 0xAD;
sfr IPH = 0xB7;
sfr AUXIP = 0xAE;
sfr AUXIPH = 0xAF;
// for Timer2
sfr T2MOD = 0xC9;
// for UART2
sfr S2CON = 0xAA;
sfr S2BRT = 0xBA;
sfr S2BUF = 0x9A;
// for Keypad Interrupt
sfr KBPATN = 0xD5;
sfr KBCON = 0xD6;
sfr KBMASK = 0xD7;
// for ADC
sfr ADCTL = 0xC5;
sfr ADCH = 0xC6;
sfr ADCL = 0xBE;
sfr ADC = 0xC6; //the same as ADCH: ADC result, higher 8 bits
// for PCA
sfr CCON = 0xD8;
sfr CMOD = 0xD9;
sfr CCAPM0 = 0xDA;
sfr CCAPM1 = 0xDB;
sfr CCAPM2 = 0xDC;
sfr CCAPM3 = 0xDD;
sfr CCAPM4 = 0xDE;
sfr CCAPM5 = 0xDF;
sfr CL = 0xE9;
sfr CH = 0xF9;
sfr CCAP0L = 0xEA;
sfr CCAP0H = 0xFA;
sfr CCAP1L = 0xEB;
sfr CCAP1H = 0xFB;
sfr CCAP2L = 0xEC;
sfr CCAP2H = 0xFC;
sfr CCAP3L = 0xED;
sfr CCAP3H = 0xFD;
sfr CCAP4L = 0xEE;
sfr CCAP4H = 0xFE;
sfr CCAP5L = 0xEF;
sfr CCAP5H = 0xFF;
sfr PCAPWM0= 0xF2;
sfr PCAPWM1= 0xF3;
sfr PCAPWM2= 0xF4;
sfr PCAPWM3= 0xF5;
sfr PCAPWM4= 0xF6;
sfr PCAPWM5= 0xF7;
// for SPI
sfr SPSTAT = 0x84;
sfr SPCTL = 0x85;
sfr SPDAT = 0x86;
// for OCD
sfr SVAR = 0xCE;
sfr SBK = 0xCF;
// (CCON)
sbit CF = CCON^7;
sbit CR = CCON^6;
sbit CCF5 = CCON^5;
sbit CCF4 = CCON^4;
sbit CCF3 = CCON^3;
sbit CCF2 = CCON^2;
sbit CCF1 = CCON^1;
sbit CCF0 = CCON^0;
// (SCON)
sbit FE = SCON^7;
// (XICON)
sbit PX3 = XICON^7;
sbit EX3 = XICON^6;
sbit IE3 = XICON^5;
sbit IT3 = XICON^4;
sbit PX2 = XICON^3;
sbit EX2 = XICON^2;
sbit IE2 = XICON^1;
sbit IT2 = XICON^0;
// (P1 alternate)
sbit CEX5 = P1^7;
sbit CEX4 = P1^6;
sbit CEX3 = P1^5;
sbit CEX2 = P1^4;
sbit CEX1 = P1^3;
sbit CEX0 = P1^2;
sbit ECI = P1^1;
sbit SPI_CLK = P1^7;
sbit SPI_MISO = P1^6;
sbit SPI_MOSI = P1^5;
sbit SPI_SS = P1^4;
sbit S2TXD = P1^3;
sbit S2RXD = P1^2;
// (P2 alternate)
sbit KBI7 = P2^7;
sbit KBI6 = P2^6;
sbit KBI5 = P2^5;
sbit KBI4 = P2^4;
sbit KBI3 = P2^3;
sbit KBI2 = P2^2;
sbit KBI1 = P2^1;
sbit KBI0 = P2^0;
// (P3 alternate)
sbit S2CKO = P3^5;
sbit T0CKO = P3^4;
// (P4 alternate)
sbit INT3 = P4^2;
sbit INT2 = P4^3;
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <REG_MPC82G516.H>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
/* for Megawin MPC82G516 */
/*-----------------------------------------------------------------------------
Standard SFRs
-----------------------------------------------------------------------------*/
/* 8051 Registers */
sfr P0 = 0x80;
sfr P1 = 0x90;
sfr P2 = 0xA0;
sfr P3 = 0xB0;
sfr PSW = 0xD0;
sfr ACC = 0xE0;
sfr B = 0xF0;
sfr SP = 0x81;
sfr DPL = 0x82;
sfr DPH = 0x83;
sfr PCON = 0x87;
sfr TCON = 0x88;
sfr TMOD = 0x89;
sfr TL0 = 0x8A;
sfr TL1 = 0x8B;
sfr TH0 = 0x8C;
sfr TH1 = 0x8D;
sfr IE = 0xA8;
sfr IP = 0xB8;
sfr SCON = 0x98;
sfr SBUF = 0x99;
// (PSW)
sbit CY = PSW^7;
sbit AC = PSW^6;
sbit F0 = PSW^5;
sbit RS1 = PSW^4;
sbit RS0 = PSW^3;
sbit OV = PSW^2;
sbit P = PSW^0;
// (TCON)
sbit TF1 = TCON^7;
sbit TR1 = TCON^6;
sbit TF0 = TCON^5;
sbit TR0 = TCON^4;
sbit IE1 = TCON^3;
sbit IT1 = TCON^2;
sbit IE0 = TCON^1;
sbit IT0 = TCON^0;
// (IE)
sbit EA = IE^7;
sbit ES = IE^4;
sbit ET1 = IE^3;
sbit EX1 = IE^2;
sbit ET0 = IE^1;
sbit EX0 = IE^0;
// (IP)
sbit PS = IP^4;
sbit PT1 = IP^3;
sbit PX1 = IP^2;
sbit PT0 = IP^1;
sbit PX0 = IP^0;
// (SCON)
sbit SM0 = SCON^7;
sbit SM1 = SCON^6;
sbit SM2 = SCON^5;
sbit REN = SCON^4;
sbit TB8 = SCON^3;
sbit RB8 = SCON^2;
sbit TI = SCON^1;
sbit RI = SCON^0;
// (P3)
sbit P37 = P3^7;
sbit P36 = P3^6;
sbit P35 = P3^5;
sbit P34 = P3^4;
sbit P33 = P3^3;
sbit P32 = P3^2;
sbit P31 = P3^1;
sbit P30 = P3^0;
// (P2)
sbit P27 = P2^7;
sbit P26 = P2^6;
sbit P25 = P2^5;
sbit P24 = P2^4;
sbit P23 = P2^3;
sbit P22 = P2^2;
sbit P21 = P2^1;
sbit P20 = P2^0;
// (P1)
sbit P17 = P1^7;
sbit P16 = P1^6;
sbit P15 = P1^5;
sbit P14 = P1^4;
sbit P13 = P1^3;
sbit P12 = P1^2;
sbit P11 = P1^1;
sbit P10 = P1^0;
// (P0)
sbit P07 = P0^7;
sbit P06 = P0^6;
sbit P05 = P0^5;
sbit P04 = P0^4;
sbit P03 = P0^3;
sbit P02 = P0^2;
sbit P01 = P0^1;
sbit P00 = P0^0;
// (P3 alternate)
sbit RD = P3^7;
sbit WR = P3^6;
sbit T1 = P3^5;
sbit T0 = P3^4;
sbit INT1 = P3^3;
sbit INT0 = P3^2;
sbit TXD = P3^1;
sbit RXD = P3^0;
/* 8052 Extensions */
sfr T2CON = 0xC8;
sfr RCAP2L = 0xCA;
sfr RCAP2H = 0xCB;
sfr TL2 = 0xCC;
sfr TH2 = 0xCD;
// (IE)
sbit ET2 = IE^5;
// (IP)
sbit PT2 = IP^5;
// (T2CON)
sbit TF2 = T2CON^7;
sbit EXF2 = T2CON^6;
sbit RCLK = T2CON^5;
sbit TCLK = T2CON^4;
sbit EXEN2 = T2CON^3;
sbit TR2 = T2CON^2;
sbit C_T2 = T2CON^1;
sbit CP_RL2= T2CON^0;
// (P1 alternate)
sbit T2EX = P1^1;
sbit T2 = P1^0;
/*-----------------------------------------------------------------------------
New-defined SFRs
-----------------------------------------------------------------------------*/
/* MPC82G516 Extensions */
sfr AUXR = 0x8E;
sfr AUXR1 = 0xA2;
sfr SADDR = 0xA9;
sfr SADEN = 0xB9;
sfr WDTCR = 0xE1;
sfr PCON2 = 0xC7;
sfr EVRCR = 0x97;
sfr STRETCH= 0x8F;
sfr AUXR2 = 0xA6;
// for I/O
sfr P4 = 0xE8;
sfr P0M0 = 0x93;
sfr P0M1 = 0x94;
sfr P1M0 = 0x91;
sfr P1M1 = 0x92;
sfr P2M0 = 0x95;
sfr P2M1 = 0x96;
sfr P3M0 = 0xB1;
sfr P3M1 = 0xB2;
sfr P4M0 = 0xB3;
sfr P4M1 = 0xB4;
// for ISP
sfr IFD = 0xE2;
sfr IFADRH = 0xE3;
sfr IFADRL = 0xE4;
sfr IFMT = 0xE5;
sfr SCMD = 0xE6;
sfr ISPCR = 0xE7;
// for interrupt
sfr XICON = 0xC0;
sfr AUXIE = 0xAD;
sfr IPH = 0xB7;
sfr AUXIP = 0xAE;
sfr AUXIPH = 0xAF;
// for Timer2
sfr T2MOD = 0xC9;
// for UART2
sfr S2CON = 0xAA;
sfr S2BRT = 0xBA;
sfr S2BUF = 0x9A;
// for Keypad Interrupt
sfr KBPATN = 0xD5;
sfr KBCON = 0xD6;
sfr KBMASK = 0xD7;
// for ADC
sfr ADCTL = 0xC5;
sfr ADCH = 0xC6;
sfr ADCL = 0xBE;
sfr ADC = 0xC6; //the same as ADCH: ADC result, higher 8 bits
// for PCA
sfr CCON = 0xD8;
sfr CMOD = 0xD9;
sfr CCAPM0 = 0xDA;
sfr CCAPM1 = 0xDB;
sfr CCAPM2 = 0xDC;
sfr CCAPM3 = 0xDD;
sfr CCAPM4 = 0xDE;
sfr CCAPM5 = 0xDF;
sfr CL = 0xE9;
sfr CH = 0xF9;
sfr CCAP0L = 0xEA;
sfr CCAP0H = 0xFA;
sfr CCAP1L = 0xEB;
sfr CCAP1H = 0xFB;
sfr CCAP2L = 0xEC;
sfr CCAP2H = 0xFC;
sfr CCAP3L = 0xED;
sfr CCAP3H = 0xFD;
sfr CCAP4L = 0xEE;
sfr CCAP4H = 0xFE;
sfr CCAP5L = 0xEF;
sfr CCAP5H = 0xFF;
sfr PCAPWM0= 0xF2;
sfr PCAPWM1= 0xF3;
sfr PCAPWM2= 0xF4;
sfr PCAPWM3= 0xF5;
sfr PCAPWM4= 0xF6;
sfr PCAPWM5= 0xF7;
// for SPI
sfr SPSTAT = 0x84;
sfr SPCTL = 0x85;
sfr SPDAT = 0x86;
// for OCD
sfr SVAR = 0xCE;
sfr SBK = 0xCF;
// (CCON)
sbit CF = CCON^7;
sbit CR = CCON^6;
sbit CCF5 = CCON^5;
sbit CCF4 = CCON^4;
sbit CCF3 = CCON^3;
sbit CCF2 = CCON^2;
sbit CCF1 = CCON^1;
sbit CCF0 = CCON^0;
// (SCON)
sbit FE = SCON^7;
// (XICON)
sbit PX3 = XICON^7;
sbit EX3 = XICON^6;
sbit IE3 = XICON^5;
sbit IT3 = XICON^4;
sbit PX2 = XICON^3;
sbit EX2 = XICON^2;
sbit IE2 = XICON^1;
sbit IT2 = XICON^0;
// (P1 alternate)
sbit CEX5 = P1^7;
sbit CEX4 = P1^6;
sbit CEX3 = P1^5;
sbit CEX2 = P1^4;
sbit CEX1 = P1^3;
sbit CEX0 = P1^2;
sbit ECI = P1^1;
sbit SPI_CLK = P1^7;
sbit SPI_MISO = P1^6;
sbit SPI_MOSI = P1^5;
sbit SPI_SS = P1^4;
sbit S2TXD = P1^3;
sbit S2RXD = P1^2;
// (P2 alternate)
sbit KBI7 = P2^7;
sbit KBI6 = P2^6;
sbit KBI5 = P2^5;
sbit KBI4 = P2^4;
sbit KBI3 = P2^3;
sbit KBI2 = P2^2;
sbit KBI1 = P2^1;
sbit KBI0 = P2^0;
// (P3 alternate)
sbit S2CKO = P3^5;
sbit T0CKO = P3^4;
// (P4 alternate)
sbit INT3 = P4^2;
sbit INT2 = P4^3;
mpp/sample/it66021/src/Remote.c
+439 -439
View File
@@ -1,439 +1,439 @@
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <Remote.c>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifdef Enable_IR
//****************************************************************************
// Remote.c
//
// NEC format
//****************************************************************************
#include "Remote.h"
#include "Mcu.h"
#include "Utility.h"
#include "stdio.h"
#include "it6602.h"
#define InitBitReceiveReg() { \
Rmote_cnt++; \
In8bits = 0; \
g8bits_cnt = 0x80; \
Remote_State += 1; \
}
typedef enum {
Header_In = 0,
Header_9ms,
Header_4ms,
No_Header,
Get_Custom_8bits,
Custom_8bits,
Save_CustomCode,
CustomBar_8bits,
Save_CustomBarCode,
Data_8bits,
Save_DataCode,
DataBar_8bits,
Save_DataBarCode,
DataCode_Chk
}IR_Data;
BYTE idata Remote_State = 0;
BYTE idata In8bits;
BYTE idata g8bits_cnt;
BYTE idata Rmote_cnt = 0;
//WORD RmoteWidth_cnt = 1080;
BYTE idata k, SampleValue;
BYTE idata IRCode[4];
BYTE idata Byte32Code[32];
BYTE idata g_keyQue = NO_KEY;
#define MAXKEY 23
code BYTE IR2RCPTable[MAXKEY][MAXKEY]=
{
{ IR_PWR_CODE, RCP_SETUP_MENU }, // 0
{ IR_Mute_CODE, RCP_MUTE}, // 1
{ IR_Menu_CODE, RCP_ROOT_MENU }, // 2
{ IR_Up_CODE, RCP_UP }, // 3
{ IR_Down_CODE, RCP_DOWN }, // 4
{ IR_Left_CODE, RCP_LEFT }, // 5
{ IR_Right_CODE, RCP_RIGHT }, // 6
{ IR_Sel_CODE, RCP_SELECT }, // 7
{ IR_REW_CODE, RCP_REWIND}, // 8
{ IR_FFORWARD_CODE, RCP_FAST_FWD}, // 9
{ IR_PLAY_CODE, RCP_PLAY }, // 10
{ IR_STOP_CODE, RCP_STOP }, // 11
{ IR_PAUSE_CODE, RCP_PAUSE }, // 12
{ IR_SLEEP_CODE, RCP_SETUP_MENU }, // 13
{ IR_MODE_CODE, RCP_FAVORITE_MENU}, // 14
//{ IR_LIGHT_CODE, RCP_FWD}, // 15
{ IR_Exit_CODE, RCP_EXIT }, // 16
{ IR_EFFECT_CODE, RCP_ENTER}, // 17
// { IR_VFD_CODE, RCP_BKWD}, // 18
{ IR_VolUp_CODE, RCP_VOL_UP}, // 19
{ IR_VolDown_CODE, RCP_VOL_DOWN}, // 20
{ IR_ChUp_CODE, RCP_FAVORITE_MENU}, // 21
{ IR_ChDown_CODE, RCP_CONTENTS_MENU} // 22
// { IR_HDMI1_CODE, RCP_RSVD },
// { IR_HDMI2_CODE, RCP_RSVD },
};
void Remote_Receive_Pro(void)
{
switch (Remote_State)
{
case Header_In:
if (Remote_Receive_Pin == 0)
{
if (++Rmote_cnt<30)
break;
else
{
Remote_State = Header_9ms;
break;
}
}
else if (Rmote_cnt > 4)
{
SampleValue = 16;
Remote_State = No_Header;
break;
}
else
{
Rmo_Receive_Err();
}
break;
case No_Header:
if (Remote_Receive_Pin == 1)
Rmote_cnt++;
else
{
IE1 = 0;
if (Rmote_cnt > SampleValue)
In8bits = 0x80;
else
In8bits = 0x00;
Byte32Code[0]=Rmote_cnt;
k=1;
g8bits_cnt = 0x40;
Remote_State = Get_Custom_8bits;
Rmote_cnt = 0;
// printf("!2\n");
}
break;
case Header_9ms:
Rmote_cnt++;
if (Remote_Receive_Pin == 0)
break;
else
{
if (Rmote_cnt < 50 || Rmote_cnt >= 110)
Rmo_Receive_Err();
else
{
Rmote_cnt = 0;
Remote_State = Header_4ms;
}
}
break;
case Header_4ms: // check 24>gRmo_cnt>8 --> 4ms
Rmote_cnt++;
if (Remote_Receive_Pin == 0)
{
if (Rmote_cnt < 20)
Rmo_Receive_Err();
else
{
IE1 = 0; //INT1 edge trigger flag --> clear
k=0;
Rmote_cnt = 0;
In8bits = 0;
g8bits_cnt = 0x80;
Remote_State = Custom_8bits;
SampleValue = 16; // 12 for 11M crystal, 16 for 27M crystal
}
}
else{
if (Rmote_cnt < 60)
break;
else
Rmo_Receive_Err();
}
break;
case Get_Custom_8bits:
if (IE1 == 1) //INT1 edge trigger flag assert?
{
IE1 = 0; //INT1 edge trigger flag --> clear
if (Rmote_cnt <= 5)
break;
else
{
if (Rmote_cnt >SampleValue)
In8bits = In8bits + g8bits_cnt;
Byte32Code[k]=Rmote_cnt;
Rmote_cnt = 0;
g8bits_cnt >>= 1;
k++;
if (g8bits_cnt)
break;
else
Remote_State = Save_CustomCode;
}
}
else
{
if (++Rmote_cnt<40)
break;
else
{
Rmote_cnt = 0;
Remote_State = Header_In;
}
}
break;
case Custom_8bits:
case CustomBar_8bits:
case Data_8bits:
case DataBar_8bits:
if (IE1 == 1) //INT1 edge trigger flag assert?
{
IE1 = 0; //INT1 edge trigger flag --> clear
if (Rmote_cnt <= 5)
break;
else
{
if (Rmote_cnt >SampleValue)
In8bits = In8bits + g8bits_cnt;
Byte32Code[k]=Rmote_cnt;
Rmote_cnt = 0;
g8bits_cnt >>= 1;
k++;
if (g8bits_cnt)
break;
else
Remote_State += 1;
}
}
else
{
if (++Rmote_cnt<30)
break;
else
{
In8bits = In8bits + g8bits_cnt;
Byte32Code[k]=Rmote_cnt;
Rmote_cnt = 0;
g8bits_cnt >>= 1;
k++;
if (g8bits_cnt)
break;
else
{
Remote_State += 1;
}
}
}
break;
case Save_CustomCode:
IRCode[0]=In8bits;
InitBitReceiveReg();
break;
case Save_CustomBarCode:
IRCode[1]=In8bits;
InitBitReceiveReg();
break;
case Save_DataCode:
IRCode[2]=In8bits;
InitBitReceiveReg();
break;
case Save_DataBarCode:
IRCode[3]=In8bits;
InitBitReceiveReg();
break;
case DataCode_Chk:
if ( IRCode[0]==CUSTOM_CODE && IRCode[1]==CUSTOM_BAR )
{
g_keyQue = IRCode[2];
}
// disable -> else
// disable -> {
// disable -> printf(" IRCode[0] %X \r\n",IRCode[0]);
// disable -> printf(" IRCode[1] %X \r\n",IRCode[1]);
// disable -> }
Rmote_cnt = 0;
Remote_State = Header_In;
EX1 = 1; // Enable ExInt0 for remote control
IE1 = 0;
TR0 = 0;
break;
default:
break;
}
}
void Rmo_Receive_Err(void)
{
Rmote_cnt = 0;
Remote_State = Header_In;
EX1 = 1; // Enable ExInt0 for remote control
IE1 = 0;
TR0 = 0;
}
//***********************************************************************
// Function : MAIN_Timer
// Params : void
// Description: Service routine for timer T0.
// Returns : void
//***********************************************************************
void Timer0_Interrupt_Handler (void) interrupt 1 using 1
{
TR0 = 0; // stop timer
TH0 = IR_COUNTER_VALUE >> 8;
TL0 = IR_COUNTER_VALUE & 0xFF;
TR0 = 1; // start timer
Remote_Receive_Pro();
// P2_0=~P2_0;
// P2_1=~P2_1;
return;
}
#ifndef SUPPORT_I2C_SLAVE
//***********************************************************************
// Function : external interrupt 1
// Params : void
// Description: Service ExInt1
// Returns : void
//***********************************************************************
void ExInt1 (void) interrupt 2 using 2
{
EX1 = 0; // Disable ExInt0
TR0 = 1; // Enable timer 0
ET0 = 1; // Enable timer 0 overflow interrupt
// P2_0=~P2_0;
// P2_1=~P2_1;
}
#endif
void initial_INT1(void)
{
EX1 = 1; // Enable ExInt1 for IR functino
IT1 = 1; // set ExInt1 --> edge trigger for IR functino
}
//***********************************************************************
// Function : IRHandler
// Params : void
// Description: IR command handler
// Returns : void
//***********************************************************************
void IRHandler(void)
{
#if 1
unsigned char i;
if(g_keyQue!=NO_KEY)
{
MHLRX_DEBUG_PRINTF(("!!! IRHandler() !!!g_keyQue= %X \n", (int) g_keyQue));
switch(g_keyQue)
{
case IR_HDMI1_CODE:
it6602PortSelect(0);
break;
case IR_HDMI2_CODE:
it6602PortSelect(1);
break;
// case IR_AUX2_CODE:
//FIX_ID_003 xxxxx //Add IT6602 Video Output Configure Table
// IT6602ChangeTTLVideoOutputMode();
//FIX_ID_003 xxxxx
// break;
#ifdef Enable_IT6602_CEC
case IR_PWR_CODE:
IT6602_CECPowerOffByITEHDMI(1);
break;
case IR_NO4_CODE:
IT6602_CECPowerOnByITEHDMI(0);
case IR_NO5_CODE:
case IR_NO6_CODE:
IT6602_CECPowerOnByITEHDMI(1);
break;
#endif
//FIX_ID_005 xxxxx //Add Cbus Event Handler
// disable -> case IR_REW_CODE: IT6602MSCCmdTest(B_DevCapChange); break;
// disable -> case IR_PLAY_CODE: IT6602MSCCmdTest(B_HPD); break;
// disable -> case IR_PAUSE_CODE: IT6602MSCCmdTest(B_PATH_EN); break;
// disable -> case IR_FFORWARD_CODE: IT6602MSCCmdTest(B_Set_DCAP_RDY); break;
// disable -> case IR_Up_CODE: IT6602MSCCmdTest(0x10); break;
// disable -> case IR_Down_CODE: IT6602MSCCmdTest(0x20); break;
// disable -> case IR_Left_CODE: IT6602MSCCmdTest(0x40); break;
// disable -> case IR_Right_CODE: IT6602MSCCmdTest(0x80); break;
//FIX_ID_005 xxxxx
default:
for(i=0;i<MAXKEY;i++)
{
if(IR2RCPTable[i][0]==g_keyQue)
break;
}
if(i<MAXKEY)
RCPKeyPush(IR2RCPTable[i][1]);
break;
}
g_keyQue=NO_KEY;
}
#endif
}
#endif
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <Remote.c>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifdef Enable_IR
//****************************************************************************
// Remote.c
//
// NEC format
//****************************************************************************
#include "Remote.h"
#include "Mcu.h"
#include "Utility.h"
#include "stdio.h"
#include "it6602.h"
#define InitBitReceiveReg() { \
Rmote_cnt++; \
In8bits = 0; \
g8bits_cnt = 0x80; \
Remote_State += 1; \
}
typedef enum {
Header_In = 0,
Header_9ms,
Header_4ms,
No_Header,
Get_Custom_8bits,
Custom_8bits,
Save_CustomCode,
CustomBar_8bits,
Save_CustomBarCode,
Data_8bits,
Save_DataCode,
DataBar_8bits,
Save_DataBarCode,
DataCode_Chk
}IR_Data;
BYTE idata Remote_State = 0;
BYTE idata In8bits;
BYTE idata g8bits_cnt;
BYTE idata Rmote_cnt = 0;
//WORD RmoteWidth_cnt = 1080;
BYTE idata k, SampleValue;
BYTE idata IRCode[4];
BYTE idata Byte32Code[32];
BYTE idata g_keyQue = NO_KEY;
#define MAXKEY 23
code BYTE IR2RCPTable[MAXKEY][MAXKEY]=
{
{ IR_PWR_CODE, RCP_SETUP_MENU }, // 0
{ IR_Mute_CODE, RCP_MUTE}, // 1
{ IR_Menu_CODE, RCP_ROOT_MENU }, // 2
{ IR_Up_CODE, RCP_UP }, // 3
{ IR_Down_CODE, RCP_DOWN }, // 4
{ IR_Left_CODE, RCP_LEFT }, // 5
{ IR_Right_CODE, RCP_RIGHT }, // 6
{ IR_Sel_CODE, RCP_SELECT }, // 7
{ IR_REW_CODE, RCP_REWIND}, // 8
{ IR_FFORWARD_CODE, RCP_FAST_FWD}, // 9
{ IR_PLAY_CODE, RCP_PLAY }, // 10
{ IR_STOP_CODE, RCP_STOP }, // 11
{ IR_PAUSE_CODE, RCP_PAUSE }, // 12
{ IR_SLEEP_CODE, RCP_SETUP_MENU }, // 13
{ IR_MODE_CODE, RCP_FAVORITE_MENU}, // 14
//{ IR_LIGHT_CODE, RCP_FWD}, // 15
{ IR_Exit_CODE, RCP_EXIT }, // 16
{ IR_EFFECT_CODE, RCP_ENTER}, // 17
// { IR_VFD_CODE, RCP_BKWD}, // 18
{ IR_VolUp_CODE, RCP_VOL_UP}, // 19
{ IR_VolDown_CODE, RCP_VOL_DOWN}, // 20
{ IR_ChUp_CODE, RCP_FAVORITE_MENU}, // 21
{ IR_ChDown_CODE, RCP_CONTENTS_MENU} // 22
// { IR_HDMI1_CODE, RCP_RSVD },
// { IR_HDMI2_CODE, RCP_RSVD },
};
void Remote_Receive_Pro(void)
{
switch (Remote_State)
{
case Header_In:
if (Remote_Receive_Pin == 0)
{
if (++Rmote_cnt<30)
break;
else
{
Remote_State = Header_9ms;
break;
}
}
else if (Rmote_cnt > 4)
{
SampleValue = 16;
Remote_State = No_Header;
break;
}
else
{
Rmo_Receive_Err();
}
break;
case No_Header:
if (Remote_Receive_Pin == 1)
Rmote_cnt++;
else
{
IE1 = 0;
if (Rmote_cnt > SampleValue)
In8bits = 0x80;
else
In8bits = 0x00;
Byte32Code[0]=Rmote_cnt;
k=1;
g8bits_cnt = 0x40;
Remote_State = Get_Custom_8bits;
Rmote_cnt = 0;
// printf("!2\n");
}
break;
case Header_9ms:
Rmote_cnt++;
if (Remote_Receive_Pin == 0)
break;
else
{
if (Rmote_cnt < 50 || Rmote_cnt >= 110)
Rmo_Receive_Err();
else
{
Rmote_cnt = 0;
Remote_State = Header_4ms;
}
}
break;
case Header_4ms: // check 24>gRmo_cnt>8 --> 4ms
Rmote_cnt++;
if (Remote_Receive_Pin == 0)
{
if (Rmote_cnt < 20)
Rmo_Receive_Err();
else
{
IE1 = 0; //INT1 edge trigger flag --> clear
k=0;
Rmote_cnt = 0;
In8bits = 0;
g8bits_cnt = 0x80;
Remote_State = Custom_8bits;
SampleValue = 16; // 12 for 11M crystal, 16 for 27M crystal
}
}
else{
if (Rmote_cnt < 60)
break;
else
Rmo_Receive_Err();
}
break;
case Get_Custom_8bits:
if (IE1 == 1) //INT1 edge trigger flag assert?
{
IE1 = 0; //INT1 edge trigger flag --> clear
if (Rmote_cnt <= 5)
break;
else
{
if (Rmote_cnt >SampleValue)
In8bits = In8bits + g8bits_cnt;
Byte32Code[k]=Rmote_cnt;
Rmote_cnt = 0;
g8bits_cnt >>= 1;
k++;
if (g8bits_cnt)
break;
else
Remote_State = Save_CustomCode;
}
}
else
{
if (++Rmote_cnt<40)
break;
else
{
Rmote_cnt = 0;
Remote_State = Header_In;
}
}
break;
case Custom_8bits:
case CustomBar_8bits:
case Data_8bits:
case DataBar_8bits:
if (IE1 == 1) //INT1 edge trigger flag assert?
{
IE1 = 0; //INT1 edge trigger flag --> clear
if (Rmote_cnt <= 5)
break;
else
{
if (Rmote_cnt >SampleValue)
In8bits = In8bits + g8bits_cnt;
Byte32Code[k]=Rmote_cnt;
Rmote_cnt = 0;
g8bits_cnt >>= 1;
k++;
if (g8bits_cnt)
break;
else
Remote_State += 1;
}
}
else
{
if (++Rmote_cnt<30)
break;
else
{
In8bits = In8bits + g8bits_cnt;
Byte32Code[k]=Rmote_cnt;
Rmote_cnt = 0;
g8bits_cnt >>= 1;
k++;
if (g8bits_cnt)
break;
else
{
Remote_State += 1;
}
}
}
break;
case Save_CustomCode:
IRCode[0]=In8bits;
InitBitReceiveReg();
break;
case Save_CustomBarCode:
IRCode[1]=In8bits;
InitBitReceiveReg();
break;
case Save_DataCode:
IRCode[2]=In8bits;
InitBitReceiveReg();
break;
case Save_DataBarCode:
IRCode[3]=In8bits;
InitBitReceiveReg();
break;
case DataCode_Chk:
if ( IRCode[0]==CUSTOM_CODE && IRCode[1]==CUSTOM_BAR )
{
g_keyQue = IRCode[2];
}
// disable -> else
// disable -> {
// disable -> printf(" IRCode[0] %X \r\n",IRCode[0]);
// disable -> printf(" IRCode[1] %X \r\n",IRCode[1]);
// disable -> }
Rmote_cnt = 0;
Remote_State = Header_In;
EX1 = 1; // Enable ExInt0 for remote control
IE1 = 0;
TR0 = 0;
break;
default:
break;
}
}
void Rmo_Receive_Err(void)
{
Rmote_cnt = 0;
Remote_State = Header_In;
EX1 = 1; // Enable ExInt0 for remote control
IE1 = 0;
TR0 = 0;
}
//***********************************************************************
// Function : MAIN_Timer
// Params : void
// Description: Service routine for timer T0.
// Returns : void
//***********************************************************************
void Timer0_Interrupt_Handler (void) interrupt 1 using 1
{
TR0 = 0; // stop timer
TH0 = IR_COUNTER_VALUE >> 8;
TL0 = IR_COUNTER_VALUE & 0xFF;
TR0 = 1; // start timer
Remote_Receive_Pro();
// P2_0=~P2_0;
// P2_1=~P2_1;
return;
}
#ifndef SUPPORT_I2C_SLAVE
//***********************************************************************
// Function : external interrupt 1
// Params : void
// Description: Service ExInt1
// Returns : void
//***********************************************************************
void ExInt1 (void) interrupt 2 using 2
{
EX1 = 0; // Disable ExInt0
TR0 = 1; // Enable timer 0
ET0 = 1; // Enable timer 0 overflow interrupt
// P2_0=~P2_0;
// P2_1=~P2_1;
}
#endif
void initial_INT1(void)
{
EX1 = 1; // Enable ExInt1 for IR functino
IT1 = 1; // set ExInt1 --> edge trigger for IR functino
}
//***********************************************************************
// Function : IRHandler
// Params : void
// Description: IR command handler
// Returns : void
//***********************************************************************
void IRHandler(void)
{
#if 1
unsigned char i;
if(g_keyQue!=NO_KEY)
{
MHLRX_DEBUG_PRINTF(("!!! IRHandler() !!!g_keyQue= %X \n", (int) g_keyQue));
switch(g_keyQue)
{
case IR_HDMI1_CODE:
it6602PortSelect(0);
break;
case IR_HDMI2_CODE:
it6602PortSelect(1);
break;
// case IR_AUX2_CODE:
//FIX_ID_003 xxxxx //Add IT6602 Video Output Configure Table
// IT6602ChangeTTLVideoOutputMode();
//FIX_ID_003 xxxxx
// break;
#ifdef Enable_IT6602_CEC
case IR_PWR_CODE:
IT6602_CECPowerOffByITEHDMI(1);
break;
case IR_NO4_CODE:
IT6602_CECPowerOnByITEHDMI(0);
case IR_NO5_CODE:
case IR_NO6_CODE:
IT6602_CECPowerOnByITEHDMI(1);
break;
#endif
//FIX_ID_005 xxxxx //Add Cbus Event Handler
// disable -> case IR_REW_CODE: IT6602MSCCmdTest(B_DevCapChange); break;
// disable -> case IR_PLAY_CODE: IT6602MSCCmdTest(B_HPD); break;
// disable -> case IR_PAUSE_CODE: IT6602MSCCmdTest(B_PATH_EN); break;
// disable -> case IR_FFORWARD_CODE: IT6602MSCCmdTest(B_Set_DCAP_RDY); break;
// disable -> case IR_Up_CODE: IT6602MSCCmdTest(0x10); break;
// disable -> case IR_Down_CODE: IT6602MSCCmdTest(0x20); break;
// disable -> case IR_Left_CODE: IT6602MSCCmdTest(0x40); break;
// disable -> case IR_Right_CODE: IT6602MSCCmdTest(0x80); break;
//FIX_ID_005 xxxxx
default:
for(i=0;i<MAXKEY;i++)
{
if(IR2RCPTable[i][0]==g_keyQue)
break;
}
if(i<MAXKEY)
RCPKeyPush(IR2RCPTable[i][1]);
break;
}
g_keyQue=NO_KEY;
}
#endif
}
#endif
mpp/sample/it66021/src/Remote.h
+159 -159
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@@ -1,159 +1,159 @@
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <Remote.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifdef Enable_IR
//****************************************************************************
//
// Remote.h
//
// NEC Remocon Key code define
//
//****************************************************************************
//#define ITE_IR
#ifdef ITE_IR
//ITE Remote control define !!
#define CUSTOM_CODE 0xC0
#define CUSTOM_BAR 0x3F
//
#define IR_PWR_CODE 0x50
#define IR_NO0_CODE 0x08
#define IR_HDMI1_CODE 0x88
#define IR_HDMI2_CODE 0x48
//#define IR_NO1_CODE 0x88
//#define IR_NO2_CODE 0x48
#define IR_NO3_CODE 0xC8
#define IR_NO4_CODE 0x28
#define IR_NO5_CODE 0xA8
#define IR_NO6_CODE 0x68
#define IR_NO7_CODE 0xE8
#define IR_NO8_CODE 0x18
#define IR_NO9_CODE 0x98
#define IR_ChUp_CODE 0x7A
#define IR_ChDown_CODE 0x20
#define IR_VolUp_CODE 0xD8
#define IR_VolDown_CODE 0x32
#define IR_Menu_CODE 0xE0
#define IR_Exit_CODE 0xA0
#define IR_Up_CODE 0x00
#define IR_Down_CODE 0x80
#define IR_Left_CODE 0xC0
#define IR_Right_CODE 0x40
#define IR_Sel_CODE 0xF8
#define IR_REW_CODE 0xB2
#define IR_FFORWARD_CODE 0xF0
#define IR_PLAY_CODE 0xB0
#define IR_STOP_CODE 0x70
//#define IR_PAUSE_CODE 0xB0 //the same as play key
#define IR_PAUSE_CODE 0xBA // last key
#define IR_MP3_CODE 0xC2 // mp3 key
#define IR_VIDEO_CODE 0xD0 // video key
#define IR_RETURN_CODE 0xA0
#define IR_EFFECT_CODE 0x86
#define IR_VFD_CODE 0x01
#define IR_SPDIF_CODE 0x52
#define IR_AUX1_CODE 0xD2
#define IR_AUX2_CODE 0xFA
#define IR_Mute_CODE 0x58
#define IR_Info_CODE 0x52 // i key
#define IR_SLEEP_CODE 0xA2 // red
#define IR_MODE_CODE 0x62 // green
#define IR_LIGHT_CODE 0x12 // yellow
#define IR_BLUE_CODE 0x92 //blue
#else
//Zinwell remote control define !!
#define CUSTOM_CODE 0x00
#define CUSTOM_BAR 0x1F
#define IR_PWR_CODE 0xE1
#define IR_Mute_CODE 0x71
#define IR_Menu_CODE 0xF1
#define IR_Up_CODE 0x41
#define IR_Down_CODE 0xA1
#define IR_Left_CODE 0xC1
#define IR_Right_CODE 0x81
#define IR_Sel_CODE 0x21
#define IR_REW_CODE 0x5A
#define IR_FFORWARD_CODE 0xBA
#define IR_PLAY_CODE 0xDA
#define IR_STOP_CODE 0xBA
#define IR_PAUSE_CODE 0x3A
#define IR_HDMI1_CODE 0xA6
#define IR_HDMI2_CODE 0x7A
#define IR_SLEEP_CODE 0x06
#define IR_MODE_CODE 0xB1
#define IR_ChDown_CODE 0x31
#define IR_Exit_CODE 0xD1
#define IR_EFFECT_CODE 0x86
#define IR_ChUp_CODE 0x01
#define IR_SPDIF_CODE 0x52
#define IR_VolUp_CODE 0xD2
#define IR_VolDown_CODE 0xFA
#endif
#define NO_KEY 0xFF
#define KEYPAD_IN1 0xFE
#define KEYPAD_IN2 0xFD
#define KEYPAD_IN3 0xFB
#define KEYPAD_IN4 0xF7
#define KEYPAD_IN5 0xEF
#define KEYPAD_IN6 0xDF
#define KEYPAD_PWR 0xBF
//========================================================
void Remote_Receive_Pro(void);
void Rmo_Receive_Err(void);
void IRHandler(void);
void initialTimer0(void);
void initial_INT1(void);
#endif
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <Remote.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifdef Enable_IR
//****************************************************************************
//
// Remote.h
//
// NEC Remocon Key code define
//
//****************************************************************************
//#define ITE_IR
#ifdef ITE_IR
//ITE Remote control define !!
#define CUSTOM_CODE 0xC0
#define CUSTOM_BAR 0x3F
//
#define IR_PWR_CODE 0x50
#define IR_NO0_CODE 0x08
#define IR_HDMI1_CODE 0x88
#define IR_HDMI2_CODE 0x48
//#define IR_NO1_CODE 0x88
//#define IR_NO2_CODE 0x48
#define IR_NO3_CODE 0xC8
#define IR_NO4_CODE 0x28
#define IR_NO5_CODE 0xA8
#define IR_NO6_CODE 0x68
#define IR_NO7_CODE 0xE8
#define IR_NO8_CODE 0x18
#define IR_NO9_CODE 0x98
#define IR_ChUp_CODE 0x7A
#define IR_ChDown_CODE 0x20
#define IR_VolUp_CODE 0xD8
#define IR_VolDown_CODE 0x32
#define IR_Menu_CODE 0xE0
#define IR_Exit_CODE 0xA0
#define IR_Up_CODE 0x00
#define IR_Down_CODE 0x80
#define IR_Left_CODE 0xC0
#define IR_Right_CODE 0x40
#define IR_Sel_CODE 0xF8
#define IR_REW_CODE 0xB2
#define IR_FFORWARD_CODE 0xF0
#define IR_PLAY_CODE 0xB0
#define IR_STOP_CODE 0x70
//#define IR_PAUSE_CODE 0xB0 //the same as play key
#define IR_PAUSE_CODE 0xBA // last key
#define IR_MP3_CODE 0xC2 // mp3 key
#define IR_VIDEO_CODE 0xD0 // video key
#define IR_RETURN_CODE 0xA0
#define IR_EFFECT_CODE 0x86
#define IR_VFD_CODE 0x01
#define IR_SPDIF_CODE 0x52
#define IR_AUX1_CODE 0xD2
#define IR_AUX2_CODE 0xFA
#define IR_Mute_CODE 0x58
#define IR_Info_CODE 0x52 // i key
#define IR_SLEEP_CODE 0xA2 // red
#define IR_MODE_CODE 0x62 // green
#define IR_LIGHT_CODE 0x12 // yellow
#define IR_BLUE_CODE 0x92 //blue
#else
//Zinwell remote control define !!
#define CUSTOM_CODE 0x00
#define CUSTOM_BAR 0x1F
#define IR_PWR_CODE 0xE1
#define IR_Mute_CODE 0x71
#define IR_Menu_CODE 0xF1
#define IR_Up_CODE 0x41
#define IR_Down_CODE 0xA1
#define IR_Left_CODE 0xC1
#define IR_Right_CODE 0x81
#define IR_Sel_CODE 0x21
#define IR_REW_CODE 0x5A
#define IR_FFORWARD_CODE 0xBA
#define IR_PLAY_CODE 0xDA
#define IR_STOP_CODE 0xBA
#define IR_PAUSE_CODE 0x3A
#define IR_HDMI1_CODE 0xA6
#define IR_HDMI2_CODE 0x7A
#define IR_SLEEP_CODE 0x06
#define IR_MODE_CODE 0xB1
#define IR_ChDown_CODE 0x31
#define IR_Exit_CODE 0xD1
#define IR_EFFECT_CODE 0x86
#define IR_ChUp_CODE 0x01
#define IR_SPDIF_CODE 0x52
#define IR_VolUp_CODE 0xD2
#define IR_VolDown_CODE 0xFA
#endif
#define NO_KEY 0xFF
#define KEYPAD_IN1 0xFE
#define KEYPAD_IN2 0xFD
#define KEYPAD_IN3 0xFB
#define KEYPAD_IN4 0xF7
#define KEYPAD_IN5 0xEF
#define KEYPAD_IN6 0xDF
#define KEYPAD_PWR 0xBF
//========================================================
void Remote_Receive_Pro(void);
void Rmo_Receive_Err(void);
void IRHandler(void);
void initialTimer0(void);
void initial_INT1(void);
#endif
mpp/sample/it66021/src/Utility.c
+35 -35
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@@ -1,35 +1,35 @@
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <Utility.c>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#include "config.h"
//#include "Mcu.h"
//#include "IO.h"
#include "Utility.h"
#include "stdio.h"
USHORT getloopTicCount()
{
usleep(5000);
return 1;
}
void delay1ms(USHORT ms)
{
usleep(1000 * ms);
}
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <Utility.c>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#include "config.h"
//#include "Mcu.h"
//#include "IO.h"
#include "Utility.h"
#include "stdio.h"
USHORT getloopTicCount()
{
usleep(5000);
return 1;
}
void delay1ms(USHORT ms)
{
usleep(1000 * ms);
}
mpp/sample/it66021/src/Utility.h
+78 -78
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@@ -1,78 +1,78 @@
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <Utility.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifndef _Utility_h_
#define _Utility_h_
//#include "Reg_c51.h"
#include "mcu.h"
#ifdef MEGAWIN82516
#define CLOCK 11059200L
#define MachineCycle 12
#else
#ifdef _IT6602_BOARD_
#define CLOCK 27000000L
#else
#define CLOCK 24000000L
#endif
#define MachineCycle 6
#endif
#ifdef MYSON_8957
#define ENABLE_I2C_PROTOCAL_CMD
#define ENABLE_ITE_I2C_DEBUG_MODE
#define BAUD_RATE 115200L // 115200L // 19200L // 57600L
#else
#define BAUD_RATE 57600L //57600L // 115200L // 19200L // 57600L
#endif
#define MICROSECONDS_TIMER(microseconds) (((CLOCK /1000000)* (microseconds))/MachineCycle)
#define COUNTER1ms MICROSECONDS_TIMER(1000) // 1000 us = 1 ms
#define COUNTER10ms MICROSECONDS_TIMER(10000) // 10000 us = 10 ms
#define Tick100us MICROSECONDS_TIMER(100) //Timer 0 100us(IR sampling time)
#define Tick1ms (65536 - COUNTER1ms)
#define Tick10ms (65536 - COUNTER10ms)
#define IR_COUNTER_VALUE (65536 - Tick100us)
#define BAUD_SETTING (65536L - (CLOCK / (32L * BAUD_RATE)))
#define CAT_HDMI_PORTA 0
#define CAT_HDMI_PORTB 1
#define SIZEOF_CSCMTX 18
#define SIZEOF_CSCGAIN 6
#define SIZEOF_CSCOFFSET 3
//extern BYTE Ena_SP_FUNCTION;
//void HoldSystem();
//void DelayUS(USHORT us);
void delay1ms(USHORT ms);
//void Dump_CAT6613Reg();
//void init_printf(void);
//void Key_handler();
//void init_timer();
USHORT getloopTicCount();
//void initialTimer1(void);
#endif
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <Utility.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifndef _Utility_h_
#define _Utility_h_
//#include "Reg_c51.h"
#include "mcu.h"
#ifdef MEGAWIN82516
#define CLOCK 11059200L
#define MachineCycle 12
#else
#ifdef _IT6602_BOARD_
#define CLOCK 27000000L
#else
#define CLOCK 24000000L
#endif
#define MachineCycle 6
#endif
#ifdef MYSON_8957
#define ENABLE_I2C_PROTOCAL_CMD
#define ENABLE_ITE_I2C_DEBUG_MODE
#define BAUD_RATE 115200L // 115200L // 19200L // 57600L
#else
#define BAUD_RATE 57600L //57600L // 115200L // 19200L // 57600L
#endif
#define MICROSECONDS_TIMER(microseconds) (((CLOCK /1000000)* (microseconds))/MachineCycle)
#define COUNTER1ms MICROSECONDS_TIMER(1000) // 1000 us = 1 ms
#define COUNTER10ms MICROSECONDS_TIMER(10000) // 10000 us = 10 ms
#define Tick100us MICROSECONDS_TIMER(100) //Timer 0 100us(IR sampling time)
#define Tick1ms (65536 - COUNTER1ms)
#define Tick10ms (65536 - COUNTER10ms)
#define IR_COUNTER_VALUE (65536 - Tick100us)
#define BAUD_SETTING (65536L - (CLOCK / (32L * BAUD_RATE)))
#define CAT_HDMI_PORTA 0
#define CAT_HDMI_PORTB 1
#define SIZEOF_CSCMTX 18
#define SIZEOF_CSCGAIN 6
#define SIZEOF_CSCOFFSET 3
//extern BYTE Ena_SP_FUNCTION;
//void HoldSystem();
//void DelayUS(USHORT us);
void delay1ms(USHORT ms);
//void Dump_CAT6613Reg();
//void init_printf(void);
//void Key_handler();
//void init_timer();
USHORT getloopTicCount();
//void initialTimer1(void);
#endif
mpp/sample/it66021/src/config.h
+57 -57
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@@ -1,57 +1,57 @@
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <config.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifndef _CONFIG_H_
#define _CONFIG_H_
#define _MCU_8051_
#ifndef _MCU_8051_
#include "platform.h"
#endif
#define _IT66021_
#ifndef _IT66023_
#ifndef _IT6602_
#ifndef _IT66021_
#define _IT6602_
#endif
#endif
#endif
#ifdef _IT66023_
#pragma message("defined _IT66023_")
//#define ENABLE_IT66023 // only for IT66023 Usage
#endif
#ifdef _IT6602_
#pragma message("defined _IT6602_")
#endif
#ifdef _IT66021_
#pragma message("defined _IT66021_")
#endif
//#define SUPPORT_I2C_SLAVE
#ifdef SUPPORT_I2C_SLAVE
#pragma message ("SUPPORT_I2C_SLAVE defined")
#endif
#define _EN_DUAL_PIXEL_CTRL_
#define _EN_BLOCK_PWRDN_
#define SUPPORT_OUTPUTRGB
#define SUPPORT_INPUTYUV
#endif // _CONFIG_H_
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <config.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifndef _CONFIG_H_
#define _CONFIG_H_
#define _MCU_8051_
#ifndef _MCU_8051_
#include "platform.h"
#endif
#define _IT66021_
#ifndef _IT66023_
#ifndef _IT6602_
#ifndef _IT66021_
#define _IT6602_
#endif
#endif
#endif
#ifdef _IT66023_
#pragma message("defined _IT66023_")
//#define ENABLE_IT66023 // only for IT66023 Usage
#endif
#ifdef _IT6602_
#pragma message("defined _IT6602_")
#endif
#ifdef _IT66021_
#pragma message("defined _IT66021_")
#endif
//#define SUPPORT_I2C_SLAVE
#ifdef SUPPORT_I2C_SLAVE
#pragma message ("SUPPORT_I2C_SLAVE defined")
#endif
#define _EN_DUAL_PIXEL_CTRL_
#define _EN_BLOCK_PWRDN_
#define SUPPORT_OUTPUTRGB
#define SUPPORT_INPUTYUV
#endif // _CONFIG_H_
mpp/sample/it66021/src/debug.h
+68 -68
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@@ -1,68 +1,68 @@
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <debug.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifndef _DEBUG_H_
#define _DEBUG_H_
#ifndef Debug_message
#define Debug_message 1
#endif
#if Debug_message
#include <stdio.h>
#define MHLRX_DEBUG_PRINTF(x) printf x
#define EQ_DEBUG_PRINTF(x) printf x
#define EQ_PORT0_PRINTF(x) printf x
#define EQ_PORT1_PRINTF(x) printf x
#define VIDEOTIMNG_DEBUG_PRINTF(x) printf x
#define IT6602_DEBUG_INT_PRINTF(x) printf x
#define IT6602_MHL_DEBUG_PRINTF(x) printf x
#define MHL_MSC_DEBUG_PRINTF(x) printf x
#define HDMIRX_VIDEO_PRINTF(x) printf x
#define HDMIRX_AUDIO_PRINTF(x) printf x
#define HDMIRX_DEBUG_PRINT(x) printf x
#define CEC_DEBUG_PRINTF(x) //printf x
#define EDID_DEBUG_PRINTF(x) //printf x
#define ITEHDMI_DEBUG_PRINTF(x) printf x
#define VSDB_DEBUG_PRINTF(x) //printf x
#define RCP_DEBUG_PRINTF(x) printf x
#define MHL3D_DEBUG_PRINTF(x) //printf x
#define CBUS_CAL_PRINTF(x) printf x
#define MHL_INT_PRINTF(x) printf x
#else
#define MHLRX_DEBUG_PRINTF(x)
#define EQ_DEBUG_PRINTF(x)
#define EQ_PORT0_PRINTF(x)
#define EQ_PORT1_PRINTF(x)
#define VIDEOTIMNG_DEBUG_PRINTF(x)
#define IT6602_DEBUG_INT_PRINTF(x)
#define IT6602_MHL_DEBUG_PRINTF(x)
#define MHL_MSC_DEBUG_PRINTF(x)
#define HDMIRX_VIDEO_PRINTF(x)
#define HDMIRX_AUDIO_PRINTF(x)
#define HDMIRX_DEBUG_PRINT(x)
#define CEC_DEBUG_PRINTF(x)
#define EDID_DEBUG_PRINTF(x)
#define ITEHDMI_DEBUG_PRINTF(x)
#define VSDB_DEBUG_PRINTF(x)
#define RCP_DEBUG_PRINTF(x)
#define MHL3D_DEBUG_PRINTF(x)
#define CBUS_CAL_PRINTF(x)
#define MHL_INT_PRINTF(x)
#endif
#endif
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <debug.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifndef _DEBUG_H_
#define _DEBUG_H_
#ifndef Debug_message
#define Debug_message 1
#endif
#if Debug_message
#include <stdio.h>
#define MHLRX_DEBUG_PRINTF(x) printf x
#define EQ_DEBUG_PRINTF(x) printf x
#define EQ_PORT0_PRINTF(x) printf x
#define EQ_PORT1_PRINTF(x) printf x
#define VIDEOTIMNG_DEBUG_PRINTF(x) printf x
#define IT6602_DEBUG_INT_PRINTF(x) printf x
#define IT6602_MHL_DEBUG_PRINTF(x) printf x
#define MHL_MSC_DEBUG_PRINTF(x) printf x
#define HDMIRX_VIDEO_PRINTF(x) printf x
#define HDMIRX_AUDIO_PRINTF(x) printf x
#define HDMIRX_DEBUG_PRINT(x) printf x
#define CEC_DEBUG_PRINTF(x) //printf x
#define EDID_DEBUG_PRINTF(x) //printf x
#define ITEHDMI_DEBUG_PRINTF(x) printf x
#define VSDB_DEBUG_PRINTF(x) //printf x
#define RCP_DEBUG_PRINTF(x) printf x
#define MHL3D_DEBUG_PRINTF(x) //printf x
#define CBUS_CAL_PRINTF(x) printf x
#define MHL_INT_PRINTF(x) printf x
#else
#define MHLRX_DEBUG_PRINTF(x)
#define EQ_DEBUG_PRINTF(x)
#define EQ_PORT0_PRINTF(x)
#define EQ_PORT1_PRINTF(x)
#define VIDEOTIMNG_DEBUG_PRINTF(x)
#define IT6602_DEBUG_INT_PRINTF(x)
#define IT6602_MHL_DEBUG_PRINTF(x)
#define MHL_MSC_DEBUG_PRINTF(x)
#define HDMIRX_VIDEO_PRINTF(x)
#define HDMIRX_AUDIO_PRINTF(x)
#define HDMIRX_DEBUG_PRINT(x)
#define CEC_DEBUG_PRINTF(x)
#define EDID_DEBUG_PRINTF(x)
#define ITEHDMI_DEBUG_PRINTF(x)
#define VSDB_DEBUG_PRINTF(x)
#define RCP_DEBUG_PRINTF(x)
#define MHL3D_DEBUG_PRINTF(x)
#define CBUS_CAL_PRINTF(x)
#define MHL_INT_PRINTF(x)
#endif
#endif
mpp/sample/it66021/src/it6602.c
+12649 -12649
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mpp/sample/it66021/src/it6602.h
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mpp/sample/it66021/src/it6602_cec.c
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mpp/sample/it66021/src/it6602_cec.h
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mpp/sample/it66021/src/it6602_reg.h
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mpp/sample/it66021/src/it6602_repeater.c
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///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <it6602_repeater.c>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifdef SUPPORT_HDCP_REPEATER
#define SUPPORT_PSEUDO_REPEATER
#include "it6602.h"
#include "sha1.h"
//RXHDCP_State_Type RHDCPState = RXHDCP_Reset ;
// BOOL repeater = FALSE ;
// static BYTE RxHDCPStatusFlag = 0 ;
static BYTE cDownStream = 0 ;
static BYTE KSVOffset=0 ;
static _XDATA BYTE Vr[20] ;
static _XDATA BYTE M0[8] ;
static _XDATA BYTE SHABuff[64] ;
extern BYTE bHDCPMode ;
#if defined(Debug_message)
#if Debug_message
char _CODE *RXHDCPStr[] =
{
"RXHDCP_Reset = 0",
"RXHDCP_AuthStart",
"RXHDCP_AuthDone",
"RXHDCP_UpdateKSVList",
"RXHDCP_Ready",
"RXHDCP_FailReady",
"RXHDCP_Reserved"
};
#endif
#endif
///////////////////////////////////////////////////////////////////////////////
// Function Prototype
///////////////////////////////////////////////////////////////////////////////
BOOL it6602_HDCP_WriteVR(struct it6602_dev_data *it6602,BYTE *pVr);
///////////////////////////////////////////////////////////////////////////////
// Function Body
///////////////////////////////////////////////////////////////////////////////
void it6602_HDCP_SetReceiver(struct it6602_dev_data *it6602)
{
/*
PowerDownHDMI();
it6602->m_HDCPRepeater = 0 ;
InitHDMIRX(TRUE);
*/
}
void it6602_HDCP_SetRepeater(struct it6602_dev_data *it6602)
{
/*
PowerDownHDMI();
it6602->m_HDCPRepeater = 1 ;
InitHDMIRX(TRUE);
*/
}
#ifdef REPEATER_DEBUG
// void it6602_HDCP_SetRdyTimeOut(struct it6602_dev_data *it6602)
// {
// PowerDownHDMI();
// bHDCPMode = HDCP_REPEATER | HDCP_RDY_TIMEOUT ;
// InitHDMIRX(TRUE);
// }
//
// void it6602_HDCP_SetInvalidV(struct it6602_dev_data *it6602)
// {
// PowerDownHDMI();
// bHDCPMode = HDCP_REPEATER | HDCP_INVALID_V ;
// InitHDMIRX(FALSE);
// }
//
// void it6602_HDCP_SetOverDownStream(struct it6602_dev_data *it6602)
// {
// PowerDownHDMI();
// bHDCPMode = HDCP_REPEATER | HDCP_OVER_DOWNSTREAM ;
// InitHDMIRX(TRUE);
// }
//
// void it6602_HDCP_SetOverCascade(struct it6602_dev_data *it6602)
// {
// PowerDownHDMI();
// bHDCPMode = HDCP_REPEATER | HDCP_OVER_CASCADE ;
// InitHDMIRX(TRUE);
// }
#endif // REPEATER_DEBUG
void it6602_HDCP_RepeaterCapabilitySet(struct it6602_dev_data *it6602,BYTE uc)
{
unsigned char reg ;
hdmirxset(REG_RX_P0_HDCP_CTRL,uc,uc);
hdmirxset(REG_RX_P1_HDCP_CTRL,uc,uc);
HDCP_DEBUG_PRINTF(("RxHDCPRepeaterCapabilitySet=%2X\n",(int)uc));
}
void it6602_HDCP_RepeaterCapabilityClear(struct it6602_dev_data *it6602,BYTE uc)
{
unsigned char reg ;
if( 0 == it6602->m_ucCurrentHDMIPort )
{
reg = REG_RX_P0_HDCP_CTRL ;
}
else
{
reg = REG_RX_P1_HDCP_CTRL ;
}
hdmirxset(reg,uc,0);
HDCP_DEBUG_PRINTF(("RxHDCPRepeaterCapabilityClear=%2X\n",(int)uc));
}
BOOL it6602_HDCP_GenVR(BYTE Vr[])
{
// extern void SHA_Simple(void *p, LONG len, BYTE *output);
int i, n ;
n = cDownStream*5+10 ;
for(i = n ; i < 64 ; i++)
{
SHABuff[i] = 0 ;
}
for(i = 0 ; i < 64 ; i++)
{
HDCP_DEBUG_PRINTF(("%02X ",(int)SHABuff[i]));
if(0==((i+1)%8))HDCP_DEBUG_PRINTF(("\n"));
}
HDCP_DEBUG_PRINTF(("n=%2X\n",(int)n));
SHA_Simple(SHABuff, (LONG)n, Vr);
HDCP_DEBUG_PRINTF(("SHA[]: "));
for(i = 0 ; i < 20 ; i++)
{
HDCP_DEBUG_PRINTF(("%02X ",(int)Vr[i]));
}
HDCP_DEBUG_PRINTF(("\n"));
return TRUE ;
}
BOOL set_it6602_HDCP_KSVList(struct it6602_dev_data *it6602,BYTE offset, BYTE *pKSVList, BYTE count)
{
BYTE i=0;
BYTE idx = 0 ;
BYTE c ;
if(!pKSVList)
{
return FALSE ;
}
chgbank(1) ;
if((offset+count)> HDMIRX_MAX_KSV)
{
return FALSE ;
}
for(KSVOffset = offset ; (KSVOffset < HDMIRX_MAX_KSV)&& (idx < count); KSVOffset ++, idx++)
{
for(i = 0 ;i<5;i++)
{
c = pKSVList[idx*5+i] ;
hdmirxwr(REG_RX_KSV_00+i+KSVOffset*5, c) ;
SHABuff[KSVOffset*5+i] = c ;
}
}
chgbank(0);
return TRUE;
}
BOOL it6602_HDCP_GetM0(struct it6602_dev_data *it6602)
{
BYTE i;
BYTE reg ;
if(cDownStream > HDMIRX_MAX_KSV)
{
return FALSE ;
}
chgbank(2) ;
if(0==it6602->m_ucCurrentHDMIPort)
{
reg = REG_RX_P0_M0 ;
}
else
{
reg = REG_RX_P1_M0 ;
}
for(i =0 ;i<8;i++)
{
SHABuff[cDownStream*5+2+i]=hdmirxrd(reg+i);
HDCP_DEBUG_PRINTF(("M[%d] = %02X\n",i,(int)SHABuff[cDownStream*5+2+i]));
}
chgbank(0) ;
HDCP_DEBUG_PRINTF(("RxHDCPGetM0\n"));
return TRUE;
}
BOOL it6602_HDCP_GetBstatus(struct it6602_dev_data *it6602,USHORT *pBstatus)
{
if(!pBstatus)
{
return FALSE ;
}
chgbank(1);
if(it6602->m_ucCurrentHDMIPort==1)
{
*pBstatus=hdmirxrd(REG_RX_P1_BSTATUS_L);
*pBstatus <<= 8 ;
*pBstatus |= hdmirxrd(REG_RX_P1_BSTATUS_L);
}
else
{
*pBstatus=hdmirxrd(REG_RX_P0_BSTATUS_L);
*pBstatus <<= 8 ;
*pBstatus |= hdmirxrd(REG_RX_P0_BSTATUS_L);
}
chgbank(0);
HDCP_DEBUG_PRINTF(("RxHDCPGetBstatus\n"));
return TRUE;
}
void set_it6602_HDCP_BStatus(struct it6602_dev_data *it6602,WORD bstatus)
{
BYTE HDCP ;
chgbank(1);
if(it6602->m_ucCurrentHDMIPort==1)
{
hdmirxwr(REG_RX_P1_BSTATUS_H,(BYTE)((bstatus>>8)& 0x0F));
hdmirxwr(REG_RX_P1_BSTATUS_L,(BYTE)(bstatus & 0xFF));
}
else
{
hdmirxwr(REG_RX_P0_BSTATUS_H,(BYTE)((bstatus>>8)& 0x0F));
hdmirxwr(REG_RX_P0_BSTATUS_L,(BYTE)(bstatus & 0xFF));
}
chgbank(0);
cDownStream = (BYTE)(bstatus &0x7F);
if((0==(bstatus & 0x880))&& cDownStream <= HDMIRX_MAX_KSV)
{
SHABuff[cDownStream*5] = (BYTE)(bstatus &0xFF);
SHABuff[cDownStream*5+1] = (BYTE)((bstatus>>8)&0x0F)| (IsHDMIMode()?0x10:0);
}
}
BOOL it6602_HDCP_WriteVR(struct it6602_dev_data *it6602,BYTE *pVr)
{
BYTE i;
if(!pVr)
{
return FALSE ;
}
chgbank(1);
for(i = 0 ; i < 20 ; i++ )
{
hdmirxwr(REG_RX_SHA1_00 +i,*(pVr+i));
if(!(i%5))HDCP_DEBUG_PRINTF(("\n"));
HDCP_DEBUG_PRINTF(("SHA1[%2X]=%2X ,",(int)i,(int)*(pVr+i))) ;
}
chgbank(0);
Dump_ITEHDMIReg();
return TRUE;
}
void set_it6602_HDCP_Event(struct it6602_dev_data *it6602,BYTE event)
{
it6602->m_HDCPStatusFlag |= event ;
}
BOOL get_it6602_HDCP_Event(struct it6602_dev_data *it6602,BYTE event)
{
BOOL retv ;
retv = (it6602->m_HDCPStatusFlag & event)?TRUE:FALSE ;
it6602->m_HDCPStatusFlag &= ~event ;
return retv ;
}
void set_it6602_HDCP_CalcSHA(struct it6602_dev_data *it6602)
{
#if 1
IT6602_SwitchRxHDCPState(it6602,RXHDCP_UpdateKSVList);
#else
it6602_HDCP_GetM0(it6602);
it6602_HDCP_GenVR(Vr);
it6602_HDCP_WriteVR(it6602,Vr);
IT6602_SwitchRxHDCPState(it6602,RXHDCP_Ready);
#endif
}
void IT6602_SwitchRxHDCPState(struct it6602_dev_data *it6602, RxHDCP_State_Type state)
{
if(it6602->m_RxHDCPState == state)
{
return ;
}
HDCP_DEBUG_PRINTF(("IT6602_SwitchRxHDCPState():%s->%s\n",RXHDCPStr[it6602->m_RxHDCPState ],RXHDCPStr[it6602->m_RxHDCPState ])) ;
switch(state)
{
case RXHDCP_Reset:
it6602_HDCP_RepeaterCapabilityClear(it6602,B_KSV_READY);
break ;
case RXHDCP_AuthStart:
it6602_HDCP_RepeaterCapabilityClear(it6602,B_KSV_READY);
set_it6602_HDCP_Event(it6602,EVENT_RXHDCP_AUTH_START);
downstream_ActivateHDCP(it6602) ; // for activate downstream HDCP
break ;
case RXHDCP_AuthDone:
set_it6602_HDCP_Event(it6602,EVENT_RXHDCP_AUTH_DONE);
KSVOffset=0 ;
cDownStream = 0 ;
break ;
case RXHDCP_UpdateKSVList:
break ;
case RXHDCP_Ready:
it6602_HDCP_RepeaterCapabilitySet(it6602,B_KSV_READY);
break ;
case RXHDCP_FailReady:
it6602_HDCP_RepeaterCapabilitySet(it6602,B_KSV_READY);
break ;
}
it6602->m_RxHDCPState = state ;
}
void set_it6602_HDCP_FailReady(struct it6602_dev_data *it6602)
{
IT6602_SwitchRxHDCPState(it6602,RXHDCP_FailReady);
}
void it6602_HDCP_Handler(struct it6602_dev_data *it6602)
{
if(!(it6602->m_HDCPRepeater))
{
return ;
}
switch(it6602->m_RxHDCPState)
{
case RXHDCP_Reset:
/*
if(hdmirxrd(REG_P0_HDCP_STATUS)& B_R0_READY)
{
IT6602_SwitchRxHDCPState(it6602,RXHDCP_AuthDone);
}
break ;
*/
case RXHDCP_AuthStart:
if(0==it6602->m_ucCurrentHDMIPort)
{
if(hdmirxrd(REG_P0_HDCP_STATUS)& B_R0_READY)
{
IT6602_SwitchRxHDCPState(it6602,RXHDCP_AuthDone);
}
}
else
{
if(hdmirxrd(REG_P1_HDCP_STATUS)& B_R0_READY)
{
IT6602_SwitchRxHDCPState(it6602,RXHDCP_AuthDone);
}
}
break ;
case RXHDCP_AuthDone:
break ;
case RXHDCP_UpdateKSVList:
it6602_HDCP_GetM0(it6602);
it6602_HDCP_GenVR(Vr);
it6602_HDCP_WriteVR(it6602,Vr);
IT6602_SwitchRxHDCPState(it6602,RXHDCP_Ready);
break ;
}
}
void downstream_ActivateHDCP(struct it6602_dev_data *it6602) // for activate downstream HDCP
{
// it should drive true sink HDCP behavior. Here is a dummy funnciton.
}
#ifdef SUPPORT_PSEUDO_REPEATER
static _CODE BYTE SampleKSVList[] = {
0x2E,0x17,0x6A,0x79,0x35,
0x0F,0xE2,0x71,0x8E,0x47,
0xA6,0x97,0x53,0xE8,0x74,
0x0F,0xF5,0x26,0x36,0x54
};
#endif
void downstream_HDCPComplete(struct it6602_dev_data *it6602) // for activate downstream HDCP
{
// it should drive true sink HDCP behavior. Here is a pseudo funnciton.
#ifdef SUPPORT_PSEUDO_REPEATER
USHORT bStatus = 0x0103 ;
BYTE KSVList[5] ;
int i,j ;
int DownStreamCount = 3;
for(i = 0 ; i < 5*DownStreamCount ; i+=5)
{
for( j = 0 ;j< 5 ; j++)
{
KSVList[j] = SampleKSVList[i+j] ;
}
set_it6602_HDCP_KSVList(it6602,i+5,KSVList,1);
}
if( DownStreamCount > 0 )
{
bStatus=DownStreamCount|0x0100 ;
}
else
{
bStatus=0;
}
set_it6602_HDCP_BStatus(it6602,bStatus);
set_it6602_HDCP_CalcSHA(it6602);
#endif// SUPPORT_PSEUDO_REPEATER
IT6602_SwitchRxHDCPState(it6602,RXHDCP_UpdateKSVList) ;
}
#endif // SUPPORT_HDCP_REPEATER
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <it6602_repeater.c>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifdef SUPPORT_HDCP_REPEATER
#define SUPPORT_PSEUDO_REPEATER
#include "it6602.h"
#include "sha1.h"
//RXHDCP_State_Type RHDCPState = RXHDCP_Reset ;
// BOOL repeater = FALSE ;
// static BYTE RxHDCPStatusFlag = 0 ;
static BYTE cDownStream = 0 ;
static BYTE KSVOffset=0 ;
static _XDATA BYTE Vr[20] ;
static _XDATA BYTE M0[8] ;
static _XDATA BYTE SHABuff[64] ;
extern BYTE bHDCPMode ;
#if defined(Debug_message)
#if Debug_message
char _CODE *RXHDCPStr[] =
{
"RXHDCP_Reset = 0",
"RXHDCP_AuthStart",
"RXHDCP_AuthDone",
"RXHDCP_UpdateKSVList",
"RXHDCP_Ready",
"RXHDCP_FailReady",
"RXHDCP_Reserved"
};
#endif
#endif
///////////////////////////////////////////////////////////////////////////////
// Function Prototype
///////////////////////////////////////////////////////////////////////////////
BOOL it6602_HDCP_WriteVR(struct it6602_dev_data *it6602,BYTE *pVr);
///////////////////////////////////////////////////////////////////////////////
// Function Body
///////////////////////////////////////////////////////////////////////////////
void it6602_HDCP_SetReceiver(struct it6602_dev_data *it6602)
{
/*
PowerDownHDMI();
it6602->m_HDCPRepeater = 0 ;
InitHDMIRX(TRUE);
*/
}
void it6602_HDCP_SetRepeater(struct it6602_dev_data *it6602)
{
/*
PowerDownHDMI();
it6602->m_HDCPRepeater = 1 ;
InitHDMIRX(TRUE);
*/
}
#ifdef REPEATER_DEBUG
// void it6602_HDCP_SetRdyTimeOut(struct it6602_dev_data *it6602)
// {
// PowerDownHDMI();
// bHDCPMode = HDCP_REPEATER | HDCP_RDY_TIMEOUT ;
// InitHDMIRX(TRUE);
// }
//
// void it6602_HDCP_SetInvalidV(struct it6602_dev_data *it6602)
// {
// PowerDownHDMI();
// bHDCPMode = HDCP_REPEATER | HDCP_INVALID_V ;
// InitHDMIRX(FALSE);
// }
//
// void it6602_HDCP_SetOverDownStream(struct it6602_dev_data *it6602)
// {
// PowerDownHDMI();
// bHDCPMode = HDCP_REPEATER | HDCP_OVER_DOWNSTREAM ;
// InitHDMIRX(TRUE);
// }
//
// void it6602_HDCP_SetOverCascade(struct it6602_dev_data *it6602)
// {
// PowerDownHDMI();
// bHDCPMode = HDCP_REPEATER | HDCP_OVER_CASCADE ;
// InitHDMIRX(TRUE);
// }
#endif // REPEATER_DEBUG
void it6602_HDCP_RepeaterCapabilitySet(struct it6602_dev_data *it6602,BYTE uc)
{
unsigned char reg ;
hdmirxset(REG_RX_P0_HDCP_CTRL,uc,uc);
hdmirxset(REG_RX_P1_HDCP_CTRL,uc,uc);
HDCP_DEBUG_PRINTF(("RxHDCPRepeaterCapabilitySet=%2X\n",(int)uc));
}
void it6602_HDCP_RepeaterCapabilityClear(struct it6602_dev_data *it6602,BYTE uc)
{
unsigned char reg ;
if( 0 == it6602->m_ucCurrentHDMIPort )
{
reg = REG_RX_P0_HDCP_CTRL ;
}
else
{
reg = REG_RX_P1_HDCP_CTRL ;
}
hdmirxset(reg,uc,0);
HDCP_DEBUG_PRINTF(("RxHDCPRepeaterCapabilityClear=%2X\n",(int)uc));
}
BOOL it6602_HDCP_GenVR(BYTE Vr[])
{
// extern void SHA_Simple(void *p, LONG len, BYTE *output);
int i, n ;
n = cDownStream*5+10 ;
for(i = n ; i < 64 ; i++)
{
SHABuff[i] = 0 ;
}
for(i = 0 ; i < 64 ; i++)
{
HDCP_DEBUG_PRINTF(("%02X ",(int)SHABuff[i]));
if(0==((i+1)%8))HDCP_DEBUG_PRINTF(("\n"));
}
HDCP_DEBUG_PRINTF(("n=%2X\n",(int)n));
SHA_Simple(SHABuff, (LONG)n, Vr);
HDCP_DEBUG_PRINTF(("SHA[]: "));
for(i = 0 ; i < 20 ; i++)
{
HDCP_DEBUG_PRINTF(("%02X ",(int)Vr[i]));
}
HDCP_DEBUG_PRINTF(("\n"));
return TRUE ;
}
BOOL set_it6602_HDCP_KSVList(struct it6602_dev_data *it6602,BYTE offset, BYTE *pKSVList, BYTE count)
{
BYTE i=0;
BYTE idx = 0 ;
BYTE c ;
if(!pKSVList)
{
return FALSE ;
}
chgbank(1) ;
if((offset+count)> HDMIRX_MAX_KSV)
{
return FALSE ;
}
for(KSVOffset = offset ; (KSVOffset < HDMIRX_MAX_KSV)&& (idx < count); KSVOffset ++, idx++)
{
for(i = 0 ;i<5;i++)
{
c = pKSVList[idx*5+i] ;
hdmirxwr(REG_RX_KSV_00+i+KSVOffset*5, c) ;
SHABuff[KSVOffset*5+i] = c ;
}
}
chgbank(0);
return TRUE;
}
BOOL it6602_HDCP_GetM0(struct it6602_dev_data *it6602)
{
BYTE i;
BYTE reg ;
if(cDownStream > HDMIRX_MAX_KSV)
{
return FALSE ;
}
chgbank(2) ;
if(0==it6602->m_ucCurrentHDMIPort)
{
reg = REG_RX_P0_M0 ;
}
else
{
reg = REG_RX_P1_M0 ;
}
for(i =0 ;i<8;i++)
{
SHABuff[cDownStream*5+2+i]=hdmirxrd(reg+i);
HDCP_DEBUG_PRINTF(("M[%d] = %02X\n",i,(int)SHABuff[cDownStream*5+2+i]));
}
chgbank(0) ;
HDCP_DEBUG_PRINTF(("RxHDCPGetM0\n"));
return TRUE;
}
BOOL it6602_HDCP_GetBstatus(struct it6602_dev_data *it6602,USHORT *pBstatus)
{
if(!pBstatus)
{
return FALSE ;
}
chgbank(1);
if(it6602->m_ucCurrentHDMIPort==1)
{
*pBstatus=hdmirxrd(REG_RX_P1_BSTATUS_L);
*pBstatus <<= 8 ;
*pBstatus |= hdmirxrd(REG_RX_P1_BSTATUS_L);
}
else
{
*pBstatus=hdmirxrd(REG_RX_P0_BSTATUS_L);
*pBstatus <<= 8 ;
*pBstatus |= hdmirxrd(REG_RX_P0_BSTATUS_L);
}
chgbank(0);
HDCP_DEBUG_PRINTF(("RxHDCPGetBstatus\n"));
return TRUE;
}
void set_it6602_HDCP_BStatus(struct it6602_dev_data *it6602,WORD bstatus)
{
BYTE HDCP ;
chgbank(1);
if(it6602->m_ucCurrentHDMIPort==1)
{
hdmirxwr(REG_RX_P1_BSTATUS_H,(BYTE)((bstatus>>8)& 0x0F));
hdmirxwr(REG_RX_P1_BSTATUS_L,(BYTE)(bstatus & 0xFF));
}
else
{
hdmirxwr(REG_RX_P0_BSTATUS_H,(BYTE)((bstatus>>8)& 0x0F));
hdmirxwr(REG_RX_P0_BSTATUS_L,(BYTE)(bstatus & 0xFF));
}
chgbank(0);
cDownStream = (BYTE)(bstatus &0x7F);
if((0==(bstatus & 0x880))&& cDownStream <= HDMIRX_MAX_KSV)
{
SHABuff[cDownStream*5] = (BYTE)(bstatus &0xFF);
SHABuff[cDownStream*5+1] = (BYTE)((bstatus>>8)&0x0F)| (IsHDMIMode()?0x10:0);
}
}
BOOL it6602_HDCP_WriteVR(struct it6602_dev_data *it6602,BYTE *pVr)
{
BYTE i;
if(!pVr)
{
return FALSE ;
}
chgbank(1);
for(i = 0 ; i < 20 ; i++ )
{
hdmirxwr(REG_RX_SHA1_00 +i,*(pVr+i));
if(!(i%5))HDCP_DEBUG_PRINTF(("\n"));
HDCP_DEBUG_PRINTF(("SHA1[%2X]=%2X ,",(int)i,(int)*(pVr+i))) ;
}
chgbank(0);
Dump_ITEHDMIReg();
return TRUE;
}
void set_it6602_HDCP_Event(struct it6602_dev_data *it6602,BYTE event)
{
it6602->m_HDCPStatusFlag |= event ;
}
BOOL get_it6602_HDCP_Event(struct it6602_dev_data *it6602,BYTE event)
{
BOOL retv ;
retv = (it6602->m_HDCPStatusFlag & event)?TRUE:FALSE ;
it6602->m_HDCPStatusFlag &= ~event ;
return retv ;
}
void set_it6602_HDCP_CalcSHA(struct it6602_dev_data *it6602)
{
#if 1
IT6602_SwitchRxHDCPState(it6602,RXHDCP_UpdateKSVList);
#else
it6602_HDCP_GetM0(it6602);
it6602_HDCP_GenVR(Vr);
it6602_HDCP_WriteVR(it6602,Vr);
IT6602_SwitchRxHDCPState(it6602,RXHDCP_Ready);
#endif
}
void IT6602_SwitchRxHDCPState(struct it6602_dev_data *it6602, RxHDCP_State_Type state)
{
if(it6602->m_RxHDCPState == state)
{
return ;
}
HDCP_DEBUG_PRINTF(("IT6602_SwitchRxHDCPState():%s->%s\n",RXHDCPStr[it6602->m_RxHDCPState ],RXHDCPStr[it6602->m_RxHDCPState ])) ;
switch(state)
{
case RXHDCP_Reset:
it6602_HDCP_RepeaterCapabilityClear(it6602,B_KSV_READY);
break ;
case RXHDCP_AuthStart:
it6602_HDCP_RepeaterCapabilityClear(it6602,B_KSV_READY);
set_it6602_HDCP_Event(it6602,EVENT_RXHDCP_AUTH_START);
downstream_ActivateHDCP(it6602) ; // for activate downstream HDCP
break ;
case RXHDCP_AuthDone:
set_it6602_HDCP_Event(it6602,EVENT_RXHDCP_AUTH_DONE);
KSVOffset=0 ;
cDownStream = 0 ;
break ;
case RXHDCP_UpdateKSVList:
break ;
case RXHDCP_Ready:
it6602_HDCP_RepeaterCapabilitySet(it6602,B_KSV_READY);
break ;
case RXHDCP_FailReady:
it6602_HDCP_RepeaterCapabilitySet(it6602,B_KSV_READY);
break ;
}
it6602->m_RxHDCPState = state ;
}
void set_it6602_HDCP_FailReady(struct it6602_dev_data *it6602)
{
IT6602_SwitchRxHDCPState(it6602,RXHDCP_FailReady);
}
void it6602_HDCP_Handler(struct it6602_dev_data *it6602)
{
if(!(it6602->m_HDCPRepeater))
{
return ;
}
switch(it6602->m_RxHDCPState)
{
case RXHDCP_Reset:
/*
if(hdmirxrd(REG_P0_HDCP_STATUS)& B_R0_READY)
{
IT6602_SwitchRxHDCPState(it6602,RXHDCP_AuthDone);
}
break ;
*/
case RXHDCP_AuthStart:
if(0==it6602->m_ucCurrentHDMIPort)
{
if(hdmirxrd(REG_P0_HDCP_STATUS)& B_R0_READY)
{
IT6602_SwitchRxHDCPState(it6602,RXHDCP_AuthDone);
}
}
else
{
if(hdmirxrd(REG_P1_HDCP_STATUS)& B_R0_READY)
{
IT6602_SwitchRxHDCPState(it6602,RXHDCP_AuthDone);
}
}
break ;
case RXHDCP_AuthDone:
break ;
case RXHDCP_UpdateKSVList:
it6602_HDCP_GetM0(it6602);
it6602_HDCP_GenVR(Vr);
it6602_HDCP_WriteVR(it6602,Vr);
IT6602_SwitchRxHDCPState(it6602,RXHDCP_Ready);
break ;
}
}
void downstream_ActivateHDCP(struct it6602_dev_data *it6602) // for activate downstream HDCP
{
// it should drive true sink HDCP behavior. Here is a dummy funnciton.
}
#ifdef SUPPORT_PSEUDO_REPEATER
static _CODE BYTE SampleKSVList[] = {
0x2E,0x17,0x6A,0x79,0x35,
0x0F,0xE2,0x71,0x8E,0x47,
0xA6,0x97,0x53,0xE8,0x74,
0x0F,0xF5,0x26,0x36,0x54
};
#endif
void downstream_HDCPComplete(struct it6602_dev_data *it6602) // for activate downstream HDCP
{
// it should drive true sink HDCP behavior. Here is a pseudo funnciton.
#ifdef SUPPORT_PSEUDO_REPEATER
USHORT bStatus = 0x0103 ;
BYTE KSVList[5] ;
int i,j ;
int DownStreamCount = 3;
for(i = 0 ; i < 5*DownStreamCount ; i+=5)
{
for( j = 0 ;j< 5 ; j++)
{
KSVList[j] = SampleKSVList[i+j] ;
}
set_it6602_HDCP_KSVList(it6602,i+5,KSVList,1);
}
if( DownStreamCount > 0 )
{
bStatus=DownStreamCount|0x0100 ;
}
else
{
bStatus=0;
}
set_it6602_HDCP_BStatus(it6602,bStatus);
set_it6602_HDCP_CalcSHA(it6602);
#endif// SUPPORT_PSEUDO_REPEATER
IT6602_SwitchRxHDCPState(it6602,RXHDCP_UpdateKSVList) ;
}
#endif // SUPPORT_HDCP_REPEATER
mpp/sample/it66021/src/mcu.h
+106 -106
View File
@@ -1,106 +1,106 @@
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <mcu.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifndef _MCU_H_
#define _MCU_H_
//#include "515xram.h"
#include "typedef.h"
#include <stdio.h>
//#define MEGAWIN82516 TRUE //IT6602 Demo board for TI442x platform
#ifdef MEGAWIN82516
#include "REG_MPC82G516.H"
#else
//#include "Reg_c51.h"
#endif
#ifdef Enable_IR
#include "Remote.h"
#endif
#define _IT6602_BOARD_
#ifndef _MCU_8051_
#define _MCU_8051_
#endif
//#define SUPPORT_UART_CMD
//#define Enable_IT6602_CEC //for ARC and HEAC Function
#ifdef Enable_IT6602_CEC
#ifdef Enable_IT6602_CEC
#include "it6602_cec.h"
#endif
#define DEBUG_IT6602_CEC
#define IT6602CECGPIOid 0 // for identife IT6602_CEC use Pin 1.0 & 1.1
#endif
/****************************************************************************/
/****************************************************************************/
#define IT6602A0_HDMI_ADDR 0x90 //Hardware Fixed I2C address of IT6602 HDMI
#define IT6602B0_HDMI_ADDR 0x92 //Hardware Fixed I2C address of IT6602 HDMI
#define MHL_ADDR 0xE0 //Software programmable I2C address of IT6602 MHL
#define EDID_ADDR 0xA8 //Software programmable I2C address of IT6602 EDID RAM
#define CEC_ADDR 0xC8 //Software programmable I2C address of IT6602 CEC
#define DP_ADDR 0x90
#define ADC_ADDR 0x90
#define HDMI_DEV 0
#define DP_DEV 0
#define RXDEV 0
#define MAXRXDEV 1
/****************************************************************************/
/****************************************************************************/
#define HDMI_DEV 0
#define SWADR 0x96
#define EDID_HEAD 0xA0
#define DELAY_TIME 1
#define IDLE_TIME 100
#define HIGH 1
#define LOW 0
#define ACTIVE 1
#define DISABLE 0
/****************************************************************************/
/****************************************************************************/
#ifdef _HPDMOS_
#define HPDON 0
#define HPDOFF 1
#else
#define HPDON 1
#define HPDOFF 0
#endif
#endif
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <mcu.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifndef _MCU_H_
#define _MCU_H_
//#include "515xram.h"
#include "typedef.h"
#include <stdio.h>
//#define MEGAWIN82516 TRUE //IT6602 Demo board for TI442x platform
#ifdef MEGAWIN82516
#include "REG_MPC82G516.H"
#else
//#include "Reg_c51.h"
#endif
#ifdef Enable_IR
#include "Remote.h"
#endif
#define _IT6602_BOARD_
#ifndef _MCU_8051_
#define _MCU_8051_
#endif
//#define SUPPORT_UART_CMD
//#define Enable_IT6602_CEC //for ARC and HEAC Function
#ifdef Enable_IT6602_CEC
#ifdef Enable_IT6602_CEC
#include "it6602_cec.h"
#endif
#define DEBUG_IT6602_CEC
#define IT6602CECGPIOid 0 // for identife IT6602_CEC use Pin 1.0 & 1.1
#endif
/****************************************************************************/
/****************************************************************************/
#define IT6602A0_HDMI_ADDR 0x90 //Hardware Fixed I2C address of IT6602 HDMI
#define IT6602B0_HDMI_ADDR 0x92 //Hardware Fixed I2C address of IT6602 HDMI
#define MHL_ADDR 0xE0 //Software programmable I2C address of IT6602 MHL
#define EDID_ADDR 0xA8 //Software programmable I2C address of IT6602 EDID RAM
#define CEC_ADDR 0xC8 //Software programmable I2C address of IT6602 CEC
#define DP_ADDR 0x90
#define ADC_ADDR 0x90
#define HDMI_DEV 0
#define DP_DEV 0
#define RXDEV 0
#define MAXRXDEV 1
/****************************************************************************/
/****************************************************************************/
#define HDMI_DEV 0
#define SWADR 0x96
#define EDID_HEAD 0xA0
#define DELAY_TIME 1
#define IDLE_TIME 100
#define HIGH 1
#define LOW 0
#define ACTIVE 1
#define DISABLE 0
/****************************************************************************/
/****************************************************************************/
#ifdef _HPDMOS_
#define HPDON 0
#define HPDOFF 1
#else
#define HPDON 1
#define HPDOFF 0
#endif
#endif
mpp/sample/it66021/src/nop.h
+2127 -2127
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File diff suppressed because it is too large Load Diff
mpp/sample/it66021/src/reg_c51.h
+263 -263
View File
@@ -1,263 +1,263 @@
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <reg_c51.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifndef _REG_C51_h_
#define _REG_C51_h_
#define Sfr(x,y) sfr x=y
#define Sbit(x,y,z) sbit x=y^z
#define Sfr16(x,y) sfr16 x=y
/*----------------------------------------*/
/* Include file for 8051 SFR Definitions */
/*----------------------------------------*/
/* BYTE Register */
Sfr (P0,0x80);
Sbit (P0_7,0x80,7);
Sbit (P0_6,0x80,6);
Sbit (P0_5,0x80,5);
Sbit (P0_4,0x80,4);
Sbit (P0_3,0x80,3);
Sbit (P0_2,0x80,2);
Sbit (P0_1,0x80,1);
Sbit (P0_0,0x80,0);
Sfr (P1,0x90);
Sbit (P1_7,0x90,7);
Sbit (P1_6,0x90,6);
Sbit (P1_5,0x90,5);
Sbit (P1_4,0x90,4);
Sbit (P1_3,0x90,3);
Sbit (P1_2,0x90,2);
Sbit (P1_1,0x90,1);
Sbit (P1_0,0x90,0);
Sfr (P2,0xA0);
Sbit (P2_7,0xA0,7);
Sbit (P2_6,0xA0,6);
Sbit (P2_5,0xA0,5);
Sbit (P2_4,0xA0,4);
Sbit (P2_3,0xA0,3);
Sbit (P2_2,0xA0,2);
Sbit (P2_1,0xA0,1);
Sbit (P2_0,0xA0,0);
Sfr (P3,0xB0);
Sbit (P3_7,0xB0,7);
Sbit (P3_6,0xB0,6);
Sbit (P3_5,0xB0,5);
Sbit (P3_4,0xB0,4);
Sbit (P3_3,0xB0,3);
Sbit (P3_2,0xB0,2);
Sbit (P3_1,0xB0,1);
Sbit (P3_0,0xB0,0);
Sbit (RD,0xB0,7);
Sbit (WR,0xB0,6);
Sbit (T1,0xB0,5);
Sbit (T0,0xB0,4);
Sbit (INT1,0xB0,3);
Sbit (INT0,0xB0,2);
Sbit (TXD,0xB0,1);
Sbit (RXD,0xB0,0);
Sfr (P5,0xE8);
Sbit (P5_7,0xE8,7);
Sbit (P5_6,0xE8,6);
Sbit (P5_5,0xE8,5);
Sbit (P5_4,0xE8,4);
Sbit (P5_3,0xE8,3);
Sbit (P5_2,0xE8,2);
Sbit (P5_1,0xE8,1);
Sbit (P5_0,0xE8,0);
Sfr (PSW,0xD0);
Sbit (CY,0xD0,7);
Sbit (AC,0xD0,6);
Sbit (F0,0xD0,5);
Sbit (RS1,0xD0,4);
Sbit (RS0,0xD0,3);
Sbit (OV,0xD0,2);
Sbit (UD,0xD0,1);
Sbit (P,0xD0,0);
Sfr (ACC,0xE0);
Sfr (B,0xF0);
Sfr (SP,0x81);
Sfr (DPL,0x82);
Sfr (DPH,0x83);
Sfr (PCON,0x87);
Sfr (CKCON0,0x8F);
Sfr (CKCON1,0xAF);
/*------------------ TIMERS registers ---------------------*/
Sfr (TCON,0x88);
Sbit (TF1,0x88,7);
Sbit (TR1,0x88,6);
Sbit (TF0,0x88,5);
Sbit (TR0,0x88,4);
Sbit (IE1,0x88,3);
Sbit (IT1,0x88,2);
Sbit (IE0,0x88,1);
Sbit (IT0,0x88,0);
Sfr (TMOD,0x89);
Sfr (T2CON,0xC8);
Sbit (TF2,0xC8,7);
Sbit (EXF2,0xC8,6);
Sbit (RCLK,0xC8,5);
Sbit (TCLK,0xC8,4);
Sbit (EXEN2,0xC8,3);
Sbit (TR2,0xC8,2);
Sbit (C_T2,0xC8,1);
Sbit (CP_RL2,0xC8,0);
Sfr (T2MOD,0xC9);
Sfr (TL0,0x8A);
Sfr (TL1,0x8B);
Sfr (TL2,0xCC);
Sfr (TH0,0x8C);
Sfr (TH1,0x8D);
Sfr (TH2,0xCD);
Sfr (RCAP2L,0xCA);
Sfr (RCAP2H,0xCB);
Sfr (WDTRST,0xA6);
Sfr (WDTPRG,0xA7);
/*------------------- UART registers ------------------------*/
Sfr (SCON,0x98);
Sbit (SM0,0x98,7);
Sbit (FE,0x98,7);
Sbit (SM1,0x98,6);
Sbit (SM2,0x98,5);
Sbit (REN,0x98,4);
Sbit (TB8,0x98,3);
Sbit (RB8,0x98,2);
Sbit (TI,0x98,1);
Sbit (RI,0x98,0);
Sfr (SBUF,0x99);
Sfr (SADEN,0xB9);
Sfr (SADDR,0xA9);
/*-------------------- Internal Baud Rate Generator --------*/
Sfr (BRL,0x9A);
Sfr (BDRCON,0x9B);
/*-------------------- IT registers -----------------------*/
Sfr (IEN0,0xA8);
Sfr (IEN1,0xB1);
Sfr (IPH0,0xB7);
Sfr (IPH1,0xB3);
Sfr (IPL0,0xB8);
Sfr (IPL1,0xB2);
/* IEN0 */
Sbit (EA,0xA8,7);
Sbit (EC,0xA8,6);
Sbit (ET2,0xA8,5);
Sbit (ES,0xA8,4);
Sbit (ET1,0xA8,3);
Sbit (EX1,0xA8,2);
Sbit (ET0,0xA8,1);
Sbit (EX0,0xA8,0);
/*--------------------- PCA registers -----------------------------*/
Sfr (CCON,0xD8);
Sfr (CMOD,0xD9);
Sfr (CH,0xF9);
Sfr (CL,0xE9);
Sfr (CCAP0H,0xFA);
Sfr (CCAP0L,0xEA);
Sfr (CCAPM0,0xDA);
Sfr (CCAP1H,0xFB);
Sfr (CCAP1L,0xEB);
Sfr (CCAPM1,0xDB);
Sfr (CCAP2H,0xFC);
Sfr (CCAP2L,0xEC);
Sfr (CCAPM2,0xDC);
Sfr (CCAP3H,0xFD);
Sfr (CCAP3L,0xED);
Sfr (CCAPM3,0xDD);
Sfr (CCAP4H,0xFE);
Sfr (CCAP4L,0xEE);
Sfr (CCAPM4,0xDE);
/* CCON */
Sbit (CF,0xD8,7);
Sbit (CR,0xD8,6);
Sbit (CCF4,0xD8,4);
Sbit (CCF3,0xD8,3);
Sbit (CCF2,0xD8,2);
Sbit (CCF1,0xD8,1);
Sbit (CCF0,0xD8,0);
/*------------------ T W I registers ------------------------------*/
Sfr ( SSCON,0x93);
Sfr ( SSCS,0x94);
Sfr ( SSDAT,0x95);
Sfr ( SSADR,0x96);
Sfr ( PI2,0xF8);
Sbit (PI2_1,0xF8,1);
Sbit (PI2_0,0xF8,0);
/*-------------------- OSC control registers ----------------------*/
Sfr ( CKSEL,0x85 );
Sfr ( OSCCON,0x86 );
Sfr ( CKRL,0x97 );
/*-------------------- Keyboard control registers -----------------*/
Sfr ( KBLS,0x9C );
Sfr ( KBE,0x9D );
Sfr ( KBF,0x9E );
/*-------------------- SPI ---------------------- -----------------*/
Sfr ( SPCON,0xC3 );
Sfr ( SPSTA,0xC4 );
Sfr ( SPDAT,0xC5 );
/*------ Misc ----------------------------------------------------*/
Sfr ( AUXR,0x8E);
Sfr ( AUXR1,0xA2);
Sfr ( FCON,0xD1);
/*------ E data --------------------------------------------------*/
Sfr ( EECON,0xD2 );
#ifdef MySon
Sfr (P4,0xC0);
Sbit (P4_7,0xC0,7);
Sbit (P4_6,0xC0,6);
Sbit (P4_5,0xC0,5);
Sbit (P4_4,0xC0,4);
Sbit (P4_3,0xC0,3);
Sbit (P4_2,0xC0,2);
Sbit (P4_1,0xC0,1);
Sbit (P4_0,0xC0,0);
#else
Sfr ( P4,0xE8);
Sbit (P4_7,0xE8,7);
Sbit (P4_6,0xE8,6);
Sbit (P4_5,0xE8,5);
Sbit (P4_4,0xE8,4);
Sbit (P4_3,0xE8,3);
Sbit (P4_2,0xE8,2);
Sbit (P4_1,0xE8,1);
Sbit (P4_0,0xE8,0);
#endif
#endif
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <reg_c51.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifndef _REG_C51_h_
#define _REG_C51_h_
#define Sfr(x,y) sfr x=y
#define Sbit(x,y,z) sbit x=y^z
#define Sfr16(x,y) sfr16 x=y
/*----------------------------------------*/
/* Include file for 8051 SFR Definitions */
/*----------------------------------------*/
/* BYTE Register */
Sfr (P0,0x80);
Sbit (P0_7,0x80,7);
Sbit (P0_6,0x80,6);
Sbit (P0_5,0x80,5);
Sbit (P0_4,0x80,4);
Sbit (P0_3,0x80,3);
Sbit (P0_2,0x80,2);
Sbit (P0_1,0x80,1);
Sbit (P0_0,0x80,0);
Sfr (P1,0x90);
Sbit (P1_7,0x90,7);
Sbit (P1_6,0x90,6);
Sbit (P1_5,0x90,5);
Sbit (P1_4,0x90,4);
Sbit (P1_3,0x90,3);
Sbit (P1_2,0x90,2);
Sbit (P1_1,0x90,1);
Sbit (P1_0,0x90,0);
Sfr (P2,0xA0);
Sbit (P2_7,0xA0,7);
Sbit (P2_6,0xA0,6);
Sbit (P2_5,0xA0,5);
Sbit (P2_4,0xA0,4);
Sbit (P2_3,0xA0,3);
Sbit (P2_2,0xA0,2);
Sbit (P2_1,0xA0,1);
Sbit (P2_0,0xA0,0);
Sfr (P3,0xB0);
Sbit (P3_7,0xB0,7);
Sbit (P3_6,0xB0,6);
Sbit (P3_5,0xB0,5);
Sbit (P3_4,0xB0,4);
Sbit (P3_3,0xB0,3);
Sbit (P3_2,0xB0,2);
Sbit (P3_1,0xB0,1);
Sbit (P3_0,0xB0,0);
Sbit (RD,0xB0,7);
Sbit (WR,0xB0,6);
Sbit (T1,0xB0,5);
Sbit (T0,0xB0,4);
Sbit (INT1,0xB0,3);
Sbit (INT0,0xB0,2);
Sbit (TXD,0xB0,1);
Sbit (RXD,0xB0,0);
Sfr (P5,0xE8);
Sbit (P5_7,0xE8,7);
Sbit (P5_6,0xE8,6);
Sbit (P5_5,0xE8,5);
Sbit (P5_4,0xE8,4);
Sbit (P5_3,0xE8,3);
Sbit (P5_2,0xE8,2);
Sbit (P5_1,0xE8,1);
Sbit (P5_0,0xE8,0);
Sfr (PSW,0xD0);
Sbit (CY,0xD0,7);
Sbit (AC,0xD0,6);
Sbit (F0,0xD0,5);
Sbit (RS1,0xD0,4);
Sbit (RS0,0xD0,3);
Sbit (OV,0xD0,2);
Sbit (UD,0xD0,1);
Sbit (P,0xD0,0);
Sfr (ACC,0xE0);
Sfr (B,0xF0);
Sfr (SP,0x81);
Sfr (DPL,0x82);
Sfr (DPH,0x83);
Sfr (PCON,0x87);
Sfr (CKCON0,0x8F);
Sfr (CKCON1,0xAF);
/*------------------ TIMERS registers ---------------------*/
Sfr (TCON,0x88);
Sbit (TF1,0x88,7);
Sbit (TR1,0x88,6);
Sbit (TF0,0x88,5);
Sbit (TR0,0x88,4);
Sbit (IE1,0x88,3);
Sbit (IT1,0x88,2);
Sbit (IE0,0x88,1);
Sbit (IT0,0x88,0);
Sfr (TMOD,0x89);
Sfr (T2CON,0xC8);
Sbit (TF2,0xC8,7);
Sbit (EXF2,0xC8,6);
Sbit (RCLK,0xC8,5);
Sbit (TCLK,0xC8,4);
Sbit (EXEN2,0xC8,3);
Sbit (TR2,0xC8,2);
Sbit (C_T2,0xC8,1);
Sbit (CP_RL2,0xC8,0);
Sfr (T2MOD,0xC9);
Sfr (TL0,0x8A);
Sfr (TL1,0x8B);
Sfr (TL2,0xCC);
Sfr (TH0,0x8C);
Sfr (TH1,0x8D);
Sfr (TH2,0xCD);
Sfr (RCAP2L,0xCA);
Sfr (RCAP2H,0xCB);
Sfr (WDTRST,0xA6);
Sfr (WDTPRG,0xA7);
/*------------------- UART registers ------------------------*/
Sfr (SCON,0x98);
Sbit (SM0,0x98,7);
Sbit (FE,0x98,7);
Sbit (SM1,0x98,6);
Sbit (SM2,0x98,5);
Sbit (REN,0x98,4);
Sbit (TB8,0x98,3);
Sbit (RB8,0x98,2);
Sbit (TI,0x98,1);
Sbit (RI,0x98,0);
Sfr (SBUF,0x99);
Sfr (SADEN,0xB9);
Sfr (SADDR,0xA9);
/*-------------------- Internal Baud Rate Generator --------*/
Sfr (BRL,0x9A);
Sfr (BDRCON,0x9B);
/*-------------------- IT registers -----------------------*/
Sfr (IEN0,0xA8);
Sfr (IEN1,0xB1);
Sfr (IPH0,0xB7);
Sfr (IPH1,0xB3);
Sfr (IPL0,0xB8);
Sfr (IPL1,0xB2);
/* IEN0 */
Sbit (EA,0xA8,7);
Sbit (EC,0xA8,6);
Sbit (ET2,0xA8,5);
Sbit (ES,0xA8,4);
Sbit (ET1,0xA8,3);
Sbit (EX1,0xA8,2);
Sbit (ET0,0xA8,1);
Sbit (EX0,0xA8,0);
/*--------------------- PCA registers -----------------------------*/
Sfr (CCON,0xD8);
Sfr (CMOD,0xD9);
Sfr (CH,0xF9);
Sfr (CL,0xE9);
Sfr (CCAP0H,0xFA);
Sfr (CCAP0L,0xEA);
Sfr (CCAPM0,0xDA);
Sfr (CCAP1H,0xFB);
Sfr (CCAP1L,0xEB);
Sfr (CCAPM1,0xDB);
Sfr (CCAP2H,0xFC);
Sfr (CCAP2L,0xEC);
Sfr (CCAPM2,0xDC);
Sfr (CCAP3H,0xFD);
Sfr (CCAP3L,0xED);
Sfr (CCAPM3,0xDD);
Sfr (CCAP4H,0xFE);
Sfr (CCAP4L,0xEE);
Sfr (CCAPM4,0xDE);
/* CCON */
Sbit (CF,0xD8,7);
Sbit (CR,0xD8,6);
Sbit (CCF4,0xD8,4);
Sbit (CCF3,0xD8,3);
Sbit (CCF2,0xD8,2);
Sbit (CCF1,0xD8,1);
Sbit (CCF0,0xD8,0);
/*------------------ T W I registers ------------------------------*/
Sfr ( SSCON,0x93);
Sfr ( SSCS,0x94);
Sfr ( SSDAT,0x95);
Sfr ( SSADR,0x96);
Sfr ( PI2,0xF8);
Sbit (PI2_1,0xF8,1);
Sbit (PI2_0,0xF8,0);
/*-------------------- OSC control registers ----------------------*/
Sfr ( CKSEL,0x85 );
Sfr ( OSCCON,0x86 );
Sfr ( CKRL,0x97 );
/*-------------------- Keyboard control registers -----------------*/
Sfr ( KBLS,0x9C );
Sfr ( KBE,0x9D );
Sfr ( KBF,0x9E );
/*-------------------- SPI ---------------------- -----------------*/
Sfr ( SPCON,0xC3 );
Sfr ( SPSTA,0xC4 );
Sfr ( SPDAT,0xC5 );
/*------ Misc ----------------------------------------------------*/
Sfr ( AUXR,0x8E);
Sfr ( AUXR1,0xA2);
Sfr ( FCON,0xD1);
/*------ E data --------------------------------------------------*/
Sfr ( EECON,0xD2 );
#ifdef MySon
Sfr (P4,0xC0);
Sbit (P4_7,0xC0,7);
Sbit (P4_6,0xC0,6);
Sbit (P4_5,0xC0,5);
Sbit (P4_4,0xC0,4);
Sbit (P4_3,0xC0,3);
Sbit (P4_2,0xC0,2);
Sbit (P4_1,0xC0,1);
Sbit (P4_0,0xC0,0);
#else
Sfr ( P4,0xE8);
Sbit (P4_7,0xE8,7);
Sbit (P4_6,0xE8,6);
Sbit (P4_5,0xE8,5);
Sbit (P4_4,0xE8,4);
Sbit (P4_3,0xE8,3);
Sbit (P4_2,0xE8,2);
Sbit (P4_1,0xE8,1);
Sbit (P4_0,0xE8,0);
#endif
#endif
mpp/sample/it66021/src/sha1.c
+152 -152
View File
@@ -1,152 +1,152 @@
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <sha1.c>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#include <stdio.h>
//#include <stdlib.h>
#include "sha1.h"
#ifndef DISABLE_HDCP
#define WCOUNT 17
ULONG VH[5];
ULONG w[WCOUNT];
#define rol(x,y)(((x)<< (y))| (((ULONG)x)>> (32-y)))
void SHATransform(ULONG * h)
{
int t;
ULONG tmp;
h[0]=0x67452301;
h[1]=0xefcdab89;
h[2]=0x98badcfe;
h[3]=0x10325476;
h[4]=0xc3d2e1f0;
for (t=0; t < 20; t++){
if(t>=16)
{
tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];
w[(t)% WCOUNT]=rol(tmp,1);
}
HDCP_DEBUG_PRINTF2(("w[%d]=%08lX\n",t,w[(t)% WCOUNT]));
tmp=rol(h[0],5)+ ((h[1] & h[2])| (h[3] & ~h[1]))+ h[4] + w[(t)% WCOUNT] + 0x5a827999;
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
h[4]=h[3];
h[3]=h[2];
h[2]=rol(h[1],30);
h[1]=h[0];
h[0]=tmp;
}
for (t=20; t < 40; t++){
tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];
w[(t)% WCOUNT]=rol(tmp,1);
HDCP_DEBUG_PRINTF2(("w[%d]=%08lX\n",t,w[(t)% WCOUNT]));
tmp=rol(h[0],5)+ (h[1] ^ h[2] ^ h[3])+ h[4] + w[(t)% WCOUNT] + 0x6ed9eba1;
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
h[4]=h[3];
h[3]=h[2];
h[2]=rol(h[1],30);
h[1]=h[0];
h[0]=tmp;
}
for (t=40; t < 60; t++){
tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];
w[(t)% WCOUNT]=rol(tmp,1);
HDCP_DEBUG_PRINTF2(("w[%d]=%08lX\n",t,w[(t)% WCOUNT]));
tmp=rol(h[0],5)+ ((h[1] & h[2])| (h[1] & h[3])| (h[2] & h[3]))+ h[4] + w[(t)% WCOUNT] + 0x8f1bbcdc;
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
h[4]=h[3];
h[3]=h[2];
h[2]=rol(h[1],30);
h[1]=h[0];
h[0]=tmp;
}
for (t=60; t < 80; t++)
{
tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];
w[(t)% WCOUNT]=rol(tmp,1);
HDCP_DEBUG_PRINTF2(("w[%d]=%08lX\n",t,w[(t)% WCOUNT]));
tmp=rol(h[0],5)+ (h[1] ^ h[2] ^ h[3])+ h[4] + w[(t)% WCOUNT] + 0xca62c1d6;
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
h[4]=h[3];
h[3]=h[2];
h[2]=rol(h[1],30);
h[1]=h[0];
h[0]=tmp;
}
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
h[0] +=0x67452301;
h[1] +=0xefcdab89;
h[2] +=0x98badcfe;
h[3] +=0x10325476;
h[4] +=0xc3d2e1f0;
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
}
void SHA_Simple(void *p,WORD len,BYTE *output)
{
// SHA_State s;
WORD i,t;
ULONG c;
BYTE *pBuff=p;
for(i=0;i < len;i++)
{
t=i/4;
if(i%4==0)
{
w[t]=0;
}
c=pBuff[i];
c <<=(3-(i%4))*8;
w[t] |=c;
HDCP_DEBUG_PRINTF2(("pBuff[%d]=%02X,c=%08lX,w[%d]=%08lX\n",(int)i,(int)pBuff[i],c,(int)t,w[t]));
}
t=i/4;
if(i%4==0)
{
w[t]=0;
}
//c=0x80 << ((3-i%4)*24);
c=0x80;
c <<=((3-i%4)*8);
w[t]|=c;t++;
for(; t < 15;t++)
{
w[t]=0;
}
w[15]=len*8;
for(i = 0 ; i < 16 ; i++)
{
HDCP_DEBUG_PRINTF2(("w[%d] = %08lX\n",i,w[i]));
}
SHATransform(VH);
for(i=0;i < 5;i++)
{
output[i*4+3]=(BYTE)((VH[i]>>24)&0xFF);
output[i*4+2]=(BYTE)((VH[i]>>16)&0xFF);
output[i*4+1]=(BYTE)((VH[i]>>8)&0xFF);
output[i*4+0]=(BYTE)(VH[i]&0xFF);
}
}
#endif
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <sha1.c>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#include <stdio.h>
//#include <stdlib.h>
#include "sha1.h"
#ifndef DISABLE_HDCP
#define WCOUNT 17
ULONG VH[5];
ULONG w[WCOUNT];
#define rol(x,y)(((x)<< (y))| (((ULONG)x)>> (32-y)))
void SHATransform(ULONG * h)
{
int t;
ULONG tmp;
h[0]=0x67452301;
h[1]=0xefcdab89;
h[2]=0x98badcfe;
h[3]=0x10325476;
h[4]=0xc3d2e1f0;
for (t=0; t < 20; t++){
if(t>=16)
{
tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];
w[(t)% WCOUNT]=rol(tmp,1);
}
HDCP_DEBUG_PRINTF2(("w[%d]=%08lX\n",t,w[(t)% WCOUNT]));
tmp=rol(h[0],5)+ ((h[1] & h[2])| (h[3] & ~h[1]))+ h[4] + w[(t)% WCOUNT] + 0x5a827999;
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
h[4]=h[3];
h[3]=h[2];
h[2]=rol(h[1],30);
h[1]=h[0];
h[0]=tmp;
}
for (t=20; t < 40; t++){
tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];
w[(t)% WCOUNT]=rol(tmp,1);
HDCP_DEBUG_PRINTF2(("w[%d]=%08lX\n",t,w[(t)% WCOUNT]));
tmp=rol(h[0],5)+ (h[1] ^ h[2] ^ h[3])+ h[4] + w[(t)% WCOUNT] + 0x6ed9eba1;
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
h[4]=h[3];
h[3]=h[2];
h[2]=rol(h[1],30);
h[1]=h[0];
h[0]=tmp;
}
for (t=40; t < 60; t++){
tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];
w[(t)% WCOUNT]=rol(tmp,1);
HDCP_DEBUG_PRINTF2(("w[%d]=%08lX\n",t,w[(t)% WCOUNT]));
tmp=rol(h[0],5)+ ((h[1] & h[2])| (h[1] & h[3])| (h[2] & h[3]))+ h[4] + w[(t)% WCOUNT] + 0x8f1bbcdc;
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
h[4]=h[3];
h[3]=h[2];
h[2]=rol(h[1],30);
h[1]=h[0];
h[0]=tmp;
}
for (t=60; t < 80; t++)
{
tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];
w[(t)% WCOUNT]=rol(tmp,1);
HDCP_DEBUG_PRINTF2(("w[%d]=%08lX\n",t,w[(t)% WCOUNT]));
tmp=rol(h[0],5)+ (h[1] ^ h[2] ^ h[3])+ h[4] + w[(t)% WCOUNT] + 0xca62c1d6;
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
h[4]=h[3];
h[3]=h[2];
h[2]=rol(h[1],30);
h[1]=h[0];
h[0]=tmp;
}
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
h[0] +=0x67452301;
h[1] +=0xefcdab89;
h[2] +=0x98badcfe;
h[3] +=0x10325476;
h[4] +=0xc3d2e1f0;
HDCP_DEBUG_PRINTF2(("%08lX %08lX %08lX %08lX %08lX\n",h[0],h[1],h[2],h[3],h[4]));
}
void SHA_Simple(void *p,WORD len,BYTE *output)
{
// SHA_State s;
WORD i,t;
ULONG c;
BYTE *pBuff=p;
for(i=0;i < len;i++)
{
t=i/4;
if(i%4==0)
{
w[t]=0;
}
c=pBuff[i];
c <<=(3-(i%4))*8;
w[t] |=c;
HDCP_DEBUG_PRINTF2(("pBuff[%d]=%02X,c=%08lX,w[%d]=%08lX\n",(int)i,(int)pBuff[i],c,(int)t,w[t]));
}
t=i/4;
if(i%4==0)
{
w[t]=0;
}
//c=0x80 << ((3-i%4)*24);
c=0x80;
c <<=((3-i%4)*8);
w[t]|=c;t++;
for(; t < 15;t++)
{
w[t]=0;
}
w[15]=len*8;
for(i = 0 ; i < 16 ; i++)
{
HDCP_DEBUG_PRINTF2(("w[%d] = %08lX\n",i,w[i]));
}
SHATransform(VH);
for(i=0;i < 5;i++)
{
output[i*4+3]=(BYTE)((VH[i]>>24)&0xFF);
output[i*4+2]=(BYTE)((VH[i]>>16)&0xFF);
output[i*4+1]=(BYTE)((VH[i]>>8)&0xFF);
output[i*4+0]=(BYTE)(VH[i]&0xFF);
}
}
#endif
mpp/sample/it66021/src/sha1.h
+56 -56
View File
@@ -1,56 +1,56 @@
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <sha1.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
///*****************************************
// Copyright (C)2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <sha1.h>
// @author Jau-chih.Tseng@ite.com.tw
// @date 2010/06/04
// @fileversion: COMMON_FILE_1.01
//******************************************/
#ifndef _SHA_1_H_
#define _SHA_1_H_
#ifdef _MCU_8051_
#include "Mcu.h"
#endif
#include <string.h>
#include "debug.h"
#include "config.h"
#include "typedef.h"
#if Debug_message
#include <stdio.h>
#endif
#ifndef HDCP_DEBUG_PRINTF
#define HDCP_DEBUG_PRINTF(x)
#endif //HDCP_DEBUG_PRINTF
#ifndef HDCP_DEBUG_PRINTF1
#define HDCP_DEBUG_PRINTF1(x)
#endif //HDCP_DEBUG_PRINTF1
#ifndef HDCP_DEBUG_PRINTF2
#define HDCP_DEBUG_PRINTF2(x)
#endif //HDCP_DEBUG_PRINTF2
#ifndef DISABLE_HDCP
void SHA_Simple(void *p,WORD len,BYTE *output);
void SHATransform(ULONG * h);
#endif
#endif // _SHA_1_H_
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <sha1.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
///*****************************************
// Copyright (C)2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <sha1.h>
// @author Jau-chih.Tseng@ite.com.tw
// @date 2010/06/04
// @fileversion: COMMON_FILE_1.01
//******************************************/
#ifndef _SHA_1_H_
#define _SHA_1_H_
#ifdef _MCU_8051_
#include "Mcu.h"
#endif
#include <string.h>
#include "debug.h"
#include "config.h"
#include "typedef.h"
#if Debug_message
#include <stdio.h>
#endif
#ifndef HDCP_DEBUG_PRINTF
#define HDCP_DEBUG_PRINTF(x)
#endif //HDCP_DEBUG_PRINTF
#ifndef HDCP_DEBUG_PRINTF1
#define HDCP_DEBUG_PRINTF1(x)
#endif //HDCP_DEBUG_PRINTF1
#ifndef HDCP_DEBUG_PRINTF2
#define HDCP_DEBUG_PRINTF2(x)
#endif //HDCP_DEBUG_PRINTF2
#ifndef DISABLE_HDCP
void SHA_Simple(void *p,WORD len,BYTE *output);
void SHATransform(ULONG * h);
#endif
#endif // _SHA_1_H_
mpp/sample/it66021/src/typedef.h
+619 -619
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File diff suppressed because it is too large Load Diff
mpp/sample/it66021/src/version.h
+19 -19
View File
@@ -1,19 +1,19 @@
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <version.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifndef _VERSION_H_
#define _VERSION_H_
#define VERSION_STRING "ITE_MHLRX_SAMPLE_V1.01"
#define SHORT_VERSION_STRING "V101\n "
#define VERSION_INTERNAL_STRING "ITE_MHLRX_SAMPLE_V1.01_EKIAL"
#endif// _VERSION_H_
#define VERSION_EDID_SERIALID 0x101
///*****************************************
// Copyright (C) 2009-2014
// ITE Tech. Inc. All Rights Reserved
// Proprietary and Confidential
///*****************************************
// @file <version.h>
// @author Max.Kao@ite.com.tw
// @date 2014/09/11
// @fileversion: ITE_MHLRX_SAMPLE_V1.01
//******************************************/
#ifndef _VERSION_H_
#define _VERSION_H_
#define VERSION_STRING "ITE_MHLRX_SAMPLE_V1.01"
#define SHORT_VERSION_STRING "V101\n "
#define VERSION_INTERNAL_STRING "ITE_MHLRX_SAMPLE_V1.01_EKIAL"
#endif// _VERSION_H_
#define VERSION_EDID_SERIALID 0x101