/*
  Copyright (c), 2001-2022, Shenshu Tech. Co., Ltd.
 */

#ifndef __MIPI_RX_HAL_H__
#define __MIPI_RX_HAL_H__

#include "type.h"
#include "ot_mipi_rx.h"
#include "mipi_rx_reg.h"

#define MIPI_RX_LANE_NUM    4

#define MIPI_RX_MAX_PHY_NUM 4

#define MIPI_RX_PHY_ID_0  0
#define MIPI_RX_PHY_ID_1  1
#define MIPI_RX_PHY_ID_2  2
#define MIPI_RX_PHY_ID_3  3

#define MIPI_RX_LANE_ID_INVALID (-1)
#define MIPI_RX_LANE_ID_0        0
#define MIPI_RX_LANE_ID_1        1
#define MIPI_RX_LANE_ID_2        2
#define MIPI_RX_LANE_ID_3        3

#define MIPI_RX_VC_0  0
#define MIPI_RX_VC_1  1
#define MIPI_RX_VC_2  2
#define MIPI_RX_VC_3  3

#define MIPI_CIL_INT_MASK   0x00003f3f
#define MIPI_CTRL_INT_MASK  0x00030003
#define MIPI_CSI_INT_MASK  0x000001ff
#define ALIGN0_INT_MASK     0x0000001f
#define MIPI_CHN_INT_MASK   0x0000000a

typedef struct {
    unsigned int clk1_fsm_timeout_err_cnt;
    unsigned int clk0_fsm_timeout_err_cnt;
    unsigned int d0_fsm_timeout_err_cnt;
    unsigned int d1_fsm_timeout_err_cnt;
    unsigned int d2_fsm_timeout_err_cnt;
    unsigned int d3_fsm_timeout_err_cnt;

    unsigned int clk1_fsm_escape_err_cnt;
    unsigned int clk0_fsm_escape_err_cnt;
    unsigned int d0_fsm_escape_err_cnt;
    unsigned int d1_fsm_escape_err_cnt;
    unsigned int d2_fsm_escape_err_cnt;
    unsigned int d3_fsm_escape_err_cnt;
} phy_err_int_cnt_t;

typedef struct {
    /* Packet err */
    unsigned int err_ecc_double_cnt;
    unsigned int vc3_err_crc_cnt;
    unsigned int vc2_err_crc_cnt;
    unsigned int vc1_err_crc_cnt;
    unsigned int vc0_err_crc_cnt;
    unsigned int vc3_err_ecc_corrected_cnt;
    unsigned int vc2_err_ecc_corrected_cnt;
    unsigned int vc1_err_ecc_corrected_cnt;
    unsigned int vc0_err_ecc_corrected_cnt;

    /* Frame err */
    unsigned int err_f_seq_vc3_cnt;
    unsigned int err_f_seq_vc2_cnt;
    unsigned int err_f_seq_vc1_cnt;
    unsigned int err_f_seq_vc0_cnt;
    unsigned int err_f_bndry_match_vc3_cnt;
    unsigned int err_f_bndry_match_vc2_cnt;
    unsigned int err_f_bndry_match_vc1_cnt;
    unsigned int err_f_bndry_match_vc0_cnt;

    /* Ctrl err */
    unsigned int data_fifo_rderr_cnt;
    unsigned int cmd_fifo_rderr_cnt;
    unsigned int data_fifo_wrerr_cnt;
    unsigned int cmd_fifo_wrerr_cnt;
} mipi_err_int_cnt_t;

typedef struct {
    unsigned int cmd_rd_err_cnt;
    unsigned int cmd_wr_err_cnt;
    unsigned int pop_err_cnt;
    unsigned int lvds_state_err_cnt;
    unsigned int link0_rd_err_cnt;
    unsigned int link0_wr_err_cnt;
} lvds_err_int_cnt_t;

typedef struct {
    unsigned int lane3_align_err_cnt;
    unsigned int lane2_align_err_cnt;
    unsigned int lane1_align_err_cnt;
    unsigned int lane0_align_err_cnt;
    unsigned int fifo_full_err_cnt;
} align_err_int_cnt_t;

typedef enum {
    WORK_4LANE_MODE = 0x00,
    WORK_2LANE_MODE,
    WORK_0LANE_MODE,
    WORK_LANE_MODE_BUTT
} mipi_lane_mode_t;

/* mipi_rx function */
unsigned int mipi_rx_get_chip_id(void);

phy_err_int_cnt_t *mipi_hal_get_phy_err_int(int phy_id);
mipi_err_int_cnt_t *mipi_hal_get_mipi_err_int(int phy_id);
align_err_int_cnt_t *mipi_hal_get_align_err_int(int phy_id);

void mipi_rx_set_regs(mipi_rx_regs_type_t *regs);
void mipi_rx_set_irq(unsigned int mipi_rx_irq);

void mipi_rx_drv_set_work_mode(combo_dev_t devno, input_mode_t input_mode);
void mipi_rx_drv_set_mipi_crop_en(combo_dev_t devno, bool enable);
void mipi_rx_drv_set_mipi_yuv_dt(combo_dev_t devno, data_type_t input_data_type);
unsigned int mipi_rx_drv_get_phy_data(int phy_id, short lane_id);
unsigned int mipi_rx_drv_get_phy_mipi_link_data(int phy_id, short lane_id);

void mipi_rx_drv_set_clear_en(combo_dev_t devno);
void mipi_rx_drv_set_scan_mode(combo_dev_t devno, mipi_scan_mode_t scan_mode);
void mipi_rx_drv_set_link_lane_id(combo_dev_t devno, input_mode_t input_mode, const short *p_lane_id);

void mipi_rx_drv_set_pn_swap(combo_dev_t devno, const unsigned char *pn_reverse);

void mipi_rx_drv_set_mem_cken(combo_dev_t devno, bool enable);
void mipi_rx_drv_set_phy_config(combo_dev_t devno, input_mode_t input_mode, unsigned int lane_bitmap);
void mipi_rx_drv_set_phy_cmvmode(input_mode_t input_mode, phy_cmv_mode_t cmv_mode, unsigned int lane_bitmap);

void mipi_rx_unlock_config(void);

int mipi_rx_drv_is_lane_valid(combo_dev_t devno, short lane_id, lane_divide_mode_t mode);
void mipi_rx_drv_set_hs_mode(lane_divide_mode_t lane_divide_mode);

int check_lane_can_used(combo_dev_t devno, const short lane_id[], int lane_num);
int mipi_check_lane_mode(combo_dev_t devno, const short lane_id[], int lane_num);
void mipi_init_lane_mode(void);

void mipi_rx_drv_get_mipi_imgsize_statis(combo_dev_t devno, short vc, img_size_t *p_size);

void mipi_rx_drv_enable_clock(combo_dev_t combo_dev);
void mipi_rx_drv_disable_clock(combo_dev_t combo_dev);

void mipi_rx_drv_core_reset(combo_dev_t combo_dev);
void mipi_rx_drv_core_unreset(combo_dev_t combo_dev);

int mipi_rx_drv_init(void);
void mipi_rx_drv_exit(void);

void mipi_rx_drv_set_chn_int_mask(combo_dev_t devno);
void mipi_rx_drv_set_mipi_ctrl_int_mask(combo_dev_t devno, unsigned int mask);
void mipi_rx_drv_set_mipi_csi_int_mask(combo_dev_t devno, unsigned int mask);
void mipi_rx_drv_set_align_int_mask(combo_dev_t devno, unsigned int mask);
void mipi_rx_drv_set_chn_int_category_mask(combo_dev_t devno, unsigned int mask);

#endif