148 lines
3.6 KiB
C
148 lines
3.6 KiB
C
/*
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Copyright (c), 2001-2022, Shenshu Tech. Co., Ltd.
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*/
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#ifndef __OT_MIPI_RX_H__
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#define __OT_MIPI_RX_H__
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#include "osal_ioctl.h"
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typedef unsigned int combo_dev_t;
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#define MIPI_LANE_NUM_PRE_DEV 4
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#define MIPI_VC_NUM 4
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#define MIPI_RX_MAX_DEV_NUM 4
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#define MIPI_LANE_ID_0 0
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#define MIPI_LANE_ID_1 1
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#define MIPI_LANE_ID_2 2
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#define MIPI_LANE_ID_3 3
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#ifdef OT_MIPI_DEBUG
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#define ot_msg(x...) \
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do { \
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osal_printk("%s->%d: ", __FUNCTION__, __LINE__); \
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osal_printk(x); \
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osal_printk("\n"); \
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} while (0)
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#else
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#define ot_msg(args...) \
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do { \
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} while (0)
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#endif
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#define ot_err(x...) \
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do { \
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osal_printk("%s(%d): ", __FUNCTION__, __LINE__); \
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osal_printk(x); \
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} while (0)
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#define mipirx_check_null_ptr_return(ptr) \
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do { \
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if ((ptr) == NULL) { \
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ot_err("NULL pointer \r\n"); \
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return TD_FAILURE; \
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} \
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} while (0)
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#define ot_mipi_rx_unused(x) ((void)x)
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typedef enum {
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LANE_DIVIDE_MODE_0 = 0,
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LANE_DIVIDE_MODE_BUTT
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} lane_divide_mode_t;
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typedef enum {
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WORK_MODE_MIPI = 0x0,
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WORK_MODE_BUTT
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} work_mode_t;
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typedef enum {
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INPUT_MODE_MIPI = 0x0,
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INPUT_MODE_BUTT
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} input_mode_t;
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typedef enum {
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MIPI_SCAN_INTERLACED = 0,
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MIPI_SCAN_PROGRESSIVE,
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MIPI_SCAN_BUTT
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} mipi_scan_mode_t;
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typedef struct {
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int x;
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int y;
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unsigned int width;
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unsigned int height;
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} img_rect_t;
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typedef struct {
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unsigned int width;
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unsigned int height;
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} img_size_t;
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typedef enum {
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DATA_TYPE_YUV422_8BIT = 0,
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DATA_TYPE_BUTT
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} data_type_t;
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typedef struct {
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data_type_t input_data_type;
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short lane_id[MIPI_LANE_NUM_PRE_DEV]; /* lane_id: -1 - disable */
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} mipi_dev_attr_t;
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typedef struct {
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combo_dev_t devno; /* device number */
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input_mode_t input_mode; /* input mode: MIPI/LVDS/SUBLVDS/HISPI/DC */
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img_rect_t img_rect; /* reserved */
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mipi_scan_mode_t scan_mode; /* reserved */
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mipi_dev_attr_t mipi_attr;
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} combo_dev_attr_t;
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typedef struct {
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combo_dev_t devno;
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unsigned char pn_swap[MIPI_LANE_NUM_PRE_DEV];
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} combo_dev_pn_swap_t;
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typedef enum {
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PHY_CMV_GE1200MV = 0x00,
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PHY_CMV_LT1200MV = 0x01,
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PHY_CMV_BUTT
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} phy_cmv_mode_t;
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typedef struct {
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combo_dev_t devno;
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phy_cmv_mode_t cmv_mode;
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} phy_cmv_t;
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#define OT_MIPI_IOC_MAGIC 'm'
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/* init data lane, input mode, data type */
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#define OT_MIPI_SET_DEV_ATTR _IOW(OT_MIPI_IOC_MAGIC, 0x01, combo_dev_attr_t)
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#define OT_MIPI_SET_PN_SWAP _IOW(OT_MIPI_IOC_MAGIC, 0x02, combo_dev_pn_swap_t)
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/* set phy common mode voltage mode */
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#define OT_MIPI_SET_PHY_CMVMODE _IOW(OT_MIPI_IOC_MAGIC, 0x04, phy_cmv_t)
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/* reset mipi */
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#define OT_MIPI_RESET_MIPI _IOW(OT_MIPI_IOC_MAGIC, 0x07, combo_dev_t)
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/* unreset mipi */
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#define OT_MIPI_UNRESET_MIPI _IOW(OT_MIPI_IOC_MAGIC, 0x08, combo_dev_t)
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/* set mipi hs_mode */
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#define OT_MIPI_SET_HS_MODE _IOW(OT_MIPI_IOC_MAGIC, 0x0b, lane_divide_mode_t)
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/* enable mipi clock */
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#define OT_MIPI_ENABLE_MIPI_CLOCK _IOW(OT_MIPI_IOC_MAGIC, 0x0c, combo_dev_t)
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/* disable mipi clock */
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#define OT_MIPI_DISABLE_MIPI_CLOCK _IOW(OT_MIPI_IOC_MAGIC, 0x0d, combo_dev_t)
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#endif /* __OT_MIPI_RX_H__ */
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