324 lines
5.6 KiB
C++
324 lines
5.6 KiB
C++
///*****************************************
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// Copyright (C) 2009-2014
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// ITE Tech. Inc. All Rights Reserved
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// Proprietary and Confidential
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///*****************************************
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// @file <REG_MPC82G516.H>
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// @author Max.Kao@ite.com.tw
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// @date 2014/09/11
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// @fileversion: ITE_MHLRX_SAMPLE_V1.01
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//******************************************/
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/* for Megawin MPC82G516 */
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/*-----------------------------------------------------------------------------
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Standard SFRs
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-----------------------------------------------------------------------------*/
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/* 8051 Registers */
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sfr P0 = 0x80;
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sfr P1 = 0x90;
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sfr P2 = 0xA0;
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sfr P3 = 0xB0;
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sfr PSW = 0xD0;
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sfr ACC = 0xE0;
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sfr B = 0xF0;
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sfr SP = 0x81;
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sfr DPL = 0x82;
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sfr DPH = 0x83;
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sfr PCON = 0x87;
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sfr TCON = 0x88;
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sfr TMOD = 0x89;
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sfr TL0 = 0x8A;
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sfr TL1 = 0x8B;
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sfr TH0 = 0x8C;
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sfr TH1 = 0x8D;
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sfr IE = 0xA8;
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sfr IP = 0xB8;
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sfr SCON = 0x98;
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sfr SBUF = 0x99;
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// (PSW)
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sbit CY = PSW^7;
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sbit AC = PSW^6;
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sbit F0 = PSW^5;
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sbit RS1 = PSW^4;
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sbit RS0 = PSW^3;
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sbit OV = PSW^2;
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sbit P = PSW^0;
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// (TCON)
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sbit TF1 = TCON^7;
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sbit TR1 = TCON^6;
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sbit TF0 = TCON^5;
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sbit TR0 = TCON^4;
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sbit IE1 = TCON^3;
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sbit IT1 = TCON^2;
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sbit IE0 = TCON^1;
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sbit IT0 = TCON^0;
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// (IE)
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sbit EA = IE^7;
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sbit ES = IE^4;
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sbit ET1 = IE^3;
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sbit EX1 = IE^2;
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sbit ET0 = IE^1;
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sbit EX0 = IE^0;
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// (IP)
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sbit PS = IP^4;
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sbit PT1 = IP^3;
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sbit PX1 = IP^2;
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sbit PT0 = IP^1;
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sbit PX0 = IP^0;
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// (SCON)
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sbit SM0 = SCON^7;
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sbit SM1 = SCON^6;
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sbit SM2 = SCON^5;
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sbit REN = SCON^4;
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sbit TB8 = SCON^3;
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sbit RB8 = SCON^2;
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sbit TI = SCON^1;
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sbit RI = SCON^0;
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// (P3)
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sbit P37 = P3^7;
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sbit P36 = P3^6;
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sbit P35 = P3^5;
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sbit P34 = P3^4;
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sbit P33 = P3^3;
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sbit P32 = P3^2;
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sbit P31 = P3^1;
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sbit P30 = P3^0;
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// (P2)
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sbit P27 = P2^7;
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sbit P26 = P2^6;
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sbit P25 = P2^5;
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sbit P24 = P2^4;
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sbit P23 = P2^3;
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sbit P22 = P2^2;
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sbit P21 = P2^1;
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sbit P20 = P2^0;
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// (P1)
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sbit P17 = P1^7;
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sbit P16 = P1^6;
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sbit P15 = P1^5;
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sbit P14 = P1^4;
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sbit P13 = P1^3;
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sbit P12 = P1^2;
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sbit P11 = P1^1;
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sbit P10 = P1^0;
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// (P0)
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sbit P07 = P0^7;
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sbit P06 = P0^6;
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sbit P05 = P0^5;
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sbit P04 = P0^4;
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sbit P03 = P0^3;
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sbit P02 = P0^2;
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sbit P01 = P0^1;
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sbit P00 = P0^0;
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// (P3 alternate)
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sbit RD = P3^7;
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sbit WR = P3^6;
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sbit T1 = P3^5;
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sbit T0 = P3^4;
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sbit INT1 = P3^3;
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sbit INT0 = P3^2;
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sbit TXD = P3^1;
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sbit RXD = P3^0;
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/* 8052 Extensions */
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sfr T2CON = 0xC8;
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sfr RCAP2L = 0xCA;
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sfr RCAP2H = 0xCB;
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sfr TL2 = 0xCC;
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sfr TH2 = 0xCD;
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// (IE)
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sbit ET2 = IE^5;
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// (IP)
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sbit PT2 = IP^5;
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// (T2CON)
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sbit TF2 = T2CON^7;
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sbit EXF2 = T2CON^6;
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sbit RCLK = T2CON^5;
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sbit TCLK = T2CON^4;
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sbit EXEN2 = T2CON^3;
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sbit TR2 = T2CON^2;
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sbit C_T2 = T2CON^1;
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sbit CP_RL2= T2CON^0;
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// (P1 alternate)
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sbit T2EX = P1^1;
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sbit T2 = P1^0;
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/*-----------------------------------------------------------------------------
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New-defined SFRs
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-----------------------------------------------------------------------------*/
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/* MPC82G516 Extensions */
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sfr AUXR = 0x8E;
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sfr AUXR1 = 0xA2;
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sfr SADDR = 0xA9;
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sfr SADEN = 0xB9;
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sfr WDTCR = 0xE1;
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sfr PCON2 = 0xC7;
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sfr EVRCR = 0x97;
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sfr STRETCH= 0x8F;
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sfr AUXR2 = 0xA6;
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// for I/O
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sfr P4 = 0xE8;
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sfr P0M0 = 0x93;
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sfr P0M1 = 0x94;
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sfr P1M0 = 0x91;
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sfr P1M1 = 0x92;
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sfr P2M0 = 0x95;
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sfr P2M1 = 0x96;
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sfr P3M0 = 0xB1;
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sfr P3M1 = 0xB2;
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sfr P4M0 = 0xB3;
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sfr P4M1 = 0xB4;
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// for ISP
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sfr IFD = 0xE2;
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sfr IFADRH = 0xE3;
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sfr IFADRL = 0xE4;
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sfr IFMT = 0xE5;
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sfr SCMD = 0xE6;
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sfr ISPCR = 0xE7;
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// for interrupt
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sfr XICON = 0xC0;
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sfr AUXIE = 0xAD;
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sfr IPH = 0xB7;
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sfr AUXIP = 0xAE;
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sfr AUXIPH = 0xAF;
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// for Timer2
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sfr T2MOD = 0xC9;
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// for UART2
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sfr S2CON = 0xAA;
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sfr S2BRT = 0xBA;
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sfr S2BUF = 0x9A;
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// for Keypad Interrupt
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sfr KBPATN = 0xD5;
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sfr KBCON = 0xD6;
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sfr KBMASK = 0xD7;
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// for ADC
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sfr ADCTL = 0xC5;
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sfr ADCH = 0xC6;
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sfr ADCL = 0xBE;
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sfr ADC = 0xC6; //the same as ADCH: ADC result, higher 8 bits
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// for PCA
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sfr CCON = 0xD8;
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sfr CMOD = 0xD9;
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sfr CCAPM0 = 0xDA;
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sfr CCAPM1 = 0xDB;
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sfr CCAPM2 = 0xDC;
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sfr CCAPM3 = 0xDD;
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sfr CCAPM4 = 0xDE;
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sfr CCAPM5 = 0xDF;
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sfr CL = 0xE9;
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sfr CH = 0xF9;
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sfr CCAP0L = 0xEA;
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sfr CCAP0H = 0xFA;
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sfr CCAP1L = 0xEB;
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sfr CCAP1H = 0xFB;
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sfr CCAP2L = 0xEC;
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sfr CCAP2H = 0xFC;
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sfr CCAP3L = 0xED;
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sfr CCAP3H = 0xFD;
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sfr CCAP4L = 0xEE;
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sfr CCAP4H = 0xFE;
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sfr CCAP5L = 0xEF;
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sfr CCAP5H = 0xFF;
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sfr PCAPWM0= 0xF2;
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sfr PCAPWM1= 0xF3;
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sfr PCAPWM2= 0xF4;
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sfr PCAPWM3= 0xF5;
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sfr PCAPWM4= 0xF6;
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sfr PCAPWM5= 0xF7;
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// for SPI
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sfr SPSTAT = 0x84;
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sfr SPCTL = 0x85;
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sfr SPDAT = 0x86;
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// for OCD
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sfr SVAR = 0xCE;
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sfr SBK = 0xCF;
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// (CCON)
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sbit CF = CCON^7;
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sbit CR = CCON^6;
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sbit CCF5 = CCON^5;
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sbit CCF4 = CCON^4;
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sbit CCF3 = CCON^3;
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sbit CCF2 = CCON^2;
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sbit CCF1 = CCON^1;
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sbit CCF0 = CCON^0;
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// (SCON)
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sbit FE = SCON^7;
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// (XICON)
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sbit PX3 = XICON^7;
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sbit EX3 = XICON^6;
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sbit IE3 = XICON^5;
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sbit IT3 = XICON^4;
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sbit PX2 = XICON^3;
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sbit EX2 = XICON^2;
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sbit IE2 = XICON^1;
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sbit IT2 = XICON^0;
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// (P1 alternate)
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sbit CEX5 = P1^7;
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sbit CEX4 = P1^6;
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sbit CEX3 = P1^5;
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sbit CEX2 = P1^4;
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sbit CEX1 = P1^3;
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sbit CEX0 = P1^2;
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sbit ECI = P1^1;
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sbit SPI_CLK = P1^7;
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sbit SPI_MISO = P1^6;
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sbit SPI_MOSI = P1^5;
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sbit SPI_SS = P1^4;
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sbit S2TXD = P1^3;
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sbit S2RXD = P1^2;
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// (P2 alternate)
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sbit KBI7 = P2^7;
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sbit KBI6 = P2^6;
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sbit KBI5 = P2^5;
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sbit KBI4 = P2^4;
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sbit KBI3 = P2^3;
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sbit KBI2 = P2^2;
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sbit KBI1 = P2^1;
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sbit KBI0 = P2^0;
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// (P3 alternate)
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sbit S2CKO = P3^5;
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sbit T0CKO = P3^4;
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// (P4 alternate)
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sbit INT3 = P4^2;
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sbit INT2 = P4^3;
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