114 lines
3.1 KiB
C
Executable File
114 lines
3.1 KiB
C
Executable File
/*
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* Copyright (c) XMEDIA. All rights reserved.
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*/
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#ifndef __CHIP_REGS_H__
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#define __CHIP_REGS_H__
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#define BIT(nr) (1 << (nr))
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#define RAM_START_ADRS 0x04010500
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#define STACK_TRAINING 0x04018000
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#define DDR_DDRT_REG_BASE 0x11330000
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#define TIMER0_REG_BASE 0x12000000
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#define TIMER1_REG_BASE 0x12000020
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#define TIMER2_REG_BASE 0x12001000
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#define TIMER3_REG_BASE 0x12001020
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#define REG_TIMER_RELOAD 0x0
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#define REG_TIMER_VALUE 0x4
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#define REG_TIMER_CONTROL 0x8
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#define CRG_REG_BASE 0x12010000
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#define SYS_CTRL_REG_BASE 0x12020000
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#define REG_BASE_SCTL SYS_CTRL_REG_BASE
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#define REG_SC_CTRL 0
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#define REMAPCLEAR BIT(8)
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#define REMAPCLEAR_SHIFT 8
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#define TIME0_CLK_SEL BIT(16)
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#define TIME0_CLK_SEL_SHIFT 16
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#define TIME0_CLK_SEL_3M 0x0
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#define TIME0_CLK_SEL_APB 0x1
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#define REG_SC_SYSRES 0x8
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#define REG_SYSSTAT 0x008C
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#define REG_OTP_PO_BIT2 0x88
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/* Generic register */
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#define REG_SC_DDRT0 0x90
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#define REG_SC_DDRT1 0x94
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#define REG_SC_DDRT2 0x98
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#define REG_SC_DDRT3 0x9c
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#define REG_SC_DDRT4 0xa0
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#define REG_SC_DDRT5 0xa4
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#define REG_SC_DDRT6 0xa8
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#define REG_SC_DDRT7 0xac
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#define REG_SC_DDRT8 0xb0
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#define REG_SC_DDRT9 0xb4
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#define REG_SC_DDRT10 0xb8
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#define REG_SC_DDRT11 0xbc
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#define REG_SC_DDRT12 0xc0
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#define REG_SC_DDRT13 0xc4
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#define REG_SC_DDRT14 0xc8
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#define REG_SC_DDRT15 0xcc
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#define REG_SC_SYSBOOT0 0x130
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#define REG_SC_SYSBOOT1 0x134
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#define REG_SC_SYSBOOT2 0x138
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#define REG_SC_SYSBOOT3 0x13c
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#define REG_SC_SYSBOOT4 0x140
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#define REG_SC_SYSBOOT5 0x144
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#define REG_SC_SYSBOOT6 0x148
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#define REG_SC_SYSBOOT7 0x14c
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#define REG_SC_SYSBOOT8 0x150
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#define REG_SC_SYSBOOT9 0x154
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#define REG_SC_SYSBOOT10 0x158
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#define REG_SC_SYSBOOT11 0x15c
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#define REG_SC_SYSBOOT12 0x160
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#define REG_SC_SYSBOOT13 0x164
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#define REG_SC_SYSBOOT14 0x168
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#define REG_SC_SYSBOOT15 0x16c
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#define DDRCA_UPDATE (SYS_CTRL_REG_BASE + 0x8034)
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#define DDRCA_RANDOM0 (SYS_CTRL_REG_BASE + 0x8600)
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#define DDRCA_RANDOM1 (SYS_CTRL_REG_BASE + 0x8604)
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#define DDRCA_RANDOM2 (SYS_CTRL_REG_BASE + 0x8608)
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#define DDRCA_RANDOM3 (SYS_CTRL_REG_BASE + 0x860c)
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#define MISC_REG_BASE 0x12028000
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#define DDRC0_REG_BASE 0x11330000
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#define UART0_REG_BASE 0x12040000
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#define FMC_MEM_BASE 0x14000000
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#define DDR_MEM_BASE 0x40000000
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#define TIMER0_BASE 0x12000000
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#define SERIAL_BASE UART0_REG_BASE
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#define UART_PL01x_DR 0x00
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#define UART_PL01x_RSR 0x04
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#define UART_PL01x_ECR 0x04
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#define UART_PL01x_FR 0x18
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#define UART_PL01x_FR_TXFE 0x80
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#define UART_PL01x_FR_RXFF 0x40
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#define UART_PL01x_FR_TXFF 0x20
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#define UART_PL01x_FR_RXFE 0x10
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#define UART_PL01x_FR_BUSY 0x08
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#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)
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#define START_MAGIC 0x444f574e
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#define SUCCESS 0
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#define FAILURE -1
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#define REG_OTP_PO_BIT0 0x12020080
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/* i2c0 reg */
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#define REG_I2C_BASE (0x12060000)
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/* clk reg control */
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#define CRG_I2C (CRG_REG_BASE + 0x1B8)
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#define I2C_CKEN BIT(16)
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#define I2C_SRST BIT(24)
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#endif
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