56 lines
1.1 KiB
C
56 lines
1.1 KiB
C
#ifndef H_DRV_PM_DDR_H
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#define H_DRV_PM_DDR_H
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#define HASH_SIZE_PER_BYTE 32
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#define DDR_CALIB_SIZE 832
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struct lpds_param {
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uint8_t lpds_hash[HASH_SIZE_PER_BYTE];
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uint8_t ddr_hash[HASH_SIZE_PER_BYTE];
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uint32_t data_start;
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uint32_t data_size;
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uint32_t hash_flag;
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uint32_t str_flag;
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uint32_t resume_addr;
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uint32_t resume_addr_backup;
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uint8_t reserve0[24];
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uint8_t scrambling_key[16];
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uint8_t ddr_calib[DDR_CALIB_SIZE];
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uint32_t ddr_size;
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uint32_t hpm_state;
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uint32_t power_state;
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uint8_t reserve1[20];
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uint32_t ddr_suspend_crc;
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uint32_t ddr_resume_crc;
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};
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struct ddr_calib_data {
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uint32_t calib_data_saved;
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uint32_t gate_dqs0_result;
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uint32_t gate_dqs1_result;
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uint32_t rx_dqs0_result;
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uint32_t rx_dqsb0_result;
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uint32_t rx_dqs1_result;
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uint32_t rx_dqsb1_result;
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uint32_t rx_dm0_result;
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uint32_t rx_dm1_result;
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uint32_t rx_dq_result[16];
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uint32_t tx_dqs0_result;
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uint32_t tx_dqsb0_result;
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uint32_t tx_dqs1_result;
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uint32_t tx_dqsb1_result;
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uint32_t tx_dm0_result;
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uint32_t tx_dm1_result;
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uint32_t tx_dq_result[16];
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};
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int pm_ddr_param_get(struct lpds_param *p_lpds_param);
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#endif
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