397 lines
13 KiB
C
Executable File
397 lines
13 KiB
C
Executable File
/*
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* Copyright (c) LOTUS. All rights reserved.
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*/
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#ifndef __XMFALCON_H
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#define __XMFALCON_H
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#include <linux/sizes.h>
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#include <asm/arch/platform.h>
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#include <linux/kconfig.h>
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/* ======================== DEBUG begin ==============================*/
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#define CP15_NO_INIT_IN_BOOTROM
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/*#define SYSCTRL_STAT_NOINIT_NAND */
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/* ======================== DEBUG end ==============================*/
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#define CONFIG_SYS_CACHELINE_SIZE 64
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/* Open it as you need #define CONFIG_REMAKE_ELF */
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#define CONFIG_SUPPORT_RAW_INITRD
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#define CONFIG_BOARD_EARLY_INIT_F
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/* Physical Memory Map */
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/* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */
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#define CONFIG_SYS_TEXT_BASE 0x40800000
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#define CONFIG_SYS_TEXT_BASE_ORI 0x40700000
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#define SEC_UBOOT_DATA_ADDR 0x41000000
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#define PHYS_SDRAM_1 0x40000000
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#define PHYS_SDRAM_1_SIZE 0x4000000
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#ifdef CONFIG_QS_MCU
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/* Hide some memory from u-boot, this memory is used by RISC-V MCU AE */
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#define CONFIG_SYS_MEM_TOP_HIDE (1 * 1024 * 1024)
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#endif
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#define CONFIG_SYS_BOOTM_LEN 0x2000000
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#define CONFIG_SYS_INIT_SP_ADDR 0x04013000
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
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#define CONFIG_SYS_GBL_DATA_SIZE 128
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
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#define CONFIG_SYS_MEMTEST_END (gd->start_addr_sp - 0x100000)
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#define CONFIG_SYS_MEMTEST_SCRATCH (SYS_CTRL_REG_BASE + 0x0c4)
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 24000000
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#define CONFIG_SYS_TIMER_RATE CFG_TIMER_CLK
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#define CONFIG_SYS_TIMER_COUNTER (CFG_TIMERBASE + REG_TIMER_VALUE)
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#define CONFIG_SYS_TIMER_COUNTS_DOWN
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE 0xf6801000
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#define GICC_BASE 0xf6802000
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_1M)
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#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
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/* PL011 Serial Configuration */
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#define CONFIG_PL011_CLOCK 24000000
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#define CONFIG_PL01x_PORTS \
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{(void *)UART0_REG_BASE, (void *)UART1_REG_BASE, \
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(void *)UART2_REG_BASE}
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#define CONFIG_CUR_UART_BASE UART0_REG_BASE
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/* Flash Memory Configuration v100 */
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#ifdef CONFIG_FMC
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#define CONFIG_FMC_REG_BASE (FMC_REG_BASE + 0x10)
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#define CONFIG_FMC_BUFFER_BASE FMC_MEM_BASE
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#define CONFIG_FMC_MAX_CS_NUM 1
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#endif
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#ifdef CONFIG_FMC_SPI_NOR
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#define CONFIG_SPI_NOR_MAX_CHIP_NUM 1
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#define CONFIG_SPI_NOR_QUIET_TEST
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#endif
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#ifdef CONFIG_FMC_SPI_NAND
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#define CONFIG_SPI_NAND_MAX_CHIP_NUM 1
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#define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_SPI_NAND_MAX_CHIP_NUM
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#define CONFIG_SYS_NAND_MAX_CHIPS CONFIG_SPI_NAND_MAX_CHIP_NUM
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#define CONFIG_SYS_NAND_BASE FMC_MEM_BASE
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#endif
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#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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/*
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*-----------------------------------------------------------------------
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* Fast ethernet Configuration
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*-----------------------------------------------------------------------
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*/
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#ifdef CONFIG_NET_FEMAC
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#ifndef CONFIG_LOTUS_FPGA
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#define INNER_PHY
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#endif
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#define SFV_MII_MODE 0
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#define SFV_RMII_MODE 1
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#define BSPETH_MII_RMII_MODE_U SFV_MII_MODE
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#define BSPETH_MII_RMII_MODE_D SFV_MII_MODE
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#ifdef CONFIG_LOTUS_FPGA
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#define SFV_PHY_U 1 /* for fpga, phy addr is 1 */
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#else
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#define SFV_PHY_U 0 /* for asc, phy addr is 0 */
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#endif
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#define SFV_PHY_D 2
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#endif
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#ifdef CONFIG_FTGMAC030
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#define CONFIG_SYS_RX_ETH_BUFFER (16)
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#endif
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/*
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*-----------------------------------------------------------------------
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* SD/MMC configuration
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_MISC_INIT_R
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/* Command line configuration */
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#define CONFIG_MENU
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/* #define CONFIG_CMD_UNZIP */
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#define CONFIG_CMD_ENV
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#define CONFIG_MTD_PARTITIONS
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/* BOOTP options */
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#define CONFIG_BOOTP_BOOTFILESIZE
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/* Initial environment variables */
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/*
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* Defines where the kernel and FDT will be put in RAM
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*/
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#ifndef CONFIG_TINY_BOOT
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/* Assume we boot with root on the seventh partition of eMMC */
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#ifndef SYSCTRL_STAT_NOINIT_NAND
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#define CONFIG_BOOTARGS "mem=32M console=ttyAMA0,115200 root=/dev/mtdblock3 rootfstype=jffs2 rw mtdparts=sfc:512K(boot),512K(bootargs),4M(kernel),11M(rootfs)"
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#else
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#define CONFIG_BOOTARGS "mem=32M console=ttyAMA0,115200 debug root=/dev/mtdblock3 rootfstype=yaffs2 rw init=/linuxrc rootwait mtdparts=nand:512K(boot),512K(bootargs),4M(kernel),32M(rootfs),-(others)"
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#endif
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#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
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#define BOOT_TARGET_DEVICES(func) \
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func(USB, usb, 0) \
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func(MMC, mmc, 1) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#endif /* CONFIG_TINY_BOOT */
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/* allow change env */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_COMMAND_HISTORY
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#define CONFIG_ENV_VARS_UBOOT_CONFIG
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/* kernel parameter list phy addr */
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#define CFG_BOOT_PARAMS (CONFIG_SYS_SDRAM_BASE + 0x0100)
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_MAXARGS 64 /* max command args */
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#define CONFIG_SYS_NO_FLASH
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/* Open it as you need #define DDR_SCRAMB_ENABLE */
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#define CONFIG_PRODUCTNAME "xmfalcon"
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/* the flag for auto update. 1:enable; 0:disable */
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#define CONFIG_AUTO_UPDATE 1
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#if (CONFIG_AUTO_UPDATE == 1)
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#define CONFIG_AUTO_UPDATE_ADAPTATION 1
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/* Open it as you need #define CONFIG_AUTO_SD_UPDATE 1 */
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/* Open it as you need #define CONFIG_AUTO_USB_UPDATE 1 */
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#define CONFIG_FS_FAT 1
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#define CONFIG_FS_FAT_MAX_CLUSTSIZE 65536
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#endif
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/*---------------------------------------------------------------------
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* sdcard system updae
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* ---------------------------------------------------------------------*/
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#ifdef CONFIG_AUTO_SD_UPDATE
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#ifndef CONFIG_SDHCI
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#define CONFIG_MMC_WRITE 1
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#define CONFIG_MMC_QUIRKS 1
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#define CONFIG_MMC_HW_PARTITIONING 1
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#define CONFIG_MMC_HS400_ES_SUPPORT 1
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#define CONFIG_MMC_HS400_SUPPORT 1
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#define CONFIG_MMC_HS200_SUPPORT 1
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#define CONFIG_MMC_VERBOSE 1
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#define CONFIG_MMC_SDHCI 1
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#define CONFIG_MMC_SDHCI_ADMA 1
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#endif
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#ifndef CONFIG_MMC
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#define CONFIG_MMC 1
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#endif
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#endif
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/* SD/MMC configuration */
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#ifdef CONFIG_MMC
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#define CONFIG_SUPPORT_EMMC_BOOT
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#define CONFIG_GENERIC_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_EXT4_SPARSE
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#define CONFIG_SDHCI
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#define CONFIG_LOTUS_SDHCI
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#define CONFIG_LOTUS_SDHCI_MAX_FREQ 200000000
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#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_FS_EXT4
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#define CONFIG_SDHCI_ADMA
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#endif
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#ifndef CONFIG_FMC
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#define CONFIG_EMMC
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#endif
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_CMDLINE_TAG
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#define HW_GZIP_HEAD_SIZE 0x10
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#define HEAD_MAGIC_NUM0 0x70697A67 /* 'g''z''i''p' */
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#define HEAD_MAGIC_NUM0_OFFSET 0x8
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#define HEAD_MAGIC_NUM1 0x64616568 /* 'h''e''a''d' */
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#define HEAD_MAGIC_NUM1_OFFSET 0xC
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#define COMPRESSED_SIZE_OFFSET 0x0
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#define UNCOMPRESSED_SIZE_OFFSET 0x4
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/* Open it as you need #define CONFIG_OSD_ENABLE */ /* For VO */
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/* Open it as you need #define CONFIG_CIPHER_ENABLE */
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/* Open it as you need #define CONFIG_AUDIO_ENABLE */
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/* Open it as you need #definee CONFIG_EDMA_PLL_TRAINNING */
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#define SECUREBOOT_OTP_REG_BASE_ADDR_PHY (0x10090000)
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/******* Head area ***************/
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/* | relative base:0x0
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* | root rsa pub key n (512 bytes)
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* | root rsa pub key e (512 bytes)
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* | 508 bytes fill 0
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* | 4 bytes: value of e
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* | relative base:0x400
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* | params area (0x1bc0)
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* | val of auxcode_area_len (4 bytes)
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* | val of boot_code_area_len (4 bytes)
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* | val of total_boot_area_len (4 bytes)
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* | val of auxcode_enc_flag (4 bytes)
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* | val of boot_enc_flag (4 bytes)
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* | val of boot_entry_piont (4 bytes)
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* | val of auxcode_aes_iv (16 bytes)
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* | val of boot_aes_iv (16 bytes)
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* | config_param (6144 bytes)
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* | reserved_0 (392 bytes)
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* | sig_params (512 bytes)
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*
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*/
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/* key area */
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#define CONFIG_KEY_AREA_POS 0
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#define CONFIG_KEY_AREA_LEN 0x2800
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#define CONFIG_ROOT_RSA_PUB_KEY_N_POS CONFIG_KEY_AREA_POS
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#define CONFIG_ROOT_RSA_PUB_KEY_N_LEN 512
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#define CONFIG_ROOT_RSA_PUB_KEY_E_POS (CONFIG_KEY_AREA_POS + CONFIG_ROOT_RSA_PUB_KEY_N_LEN)
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#define CONFIG_ROOT_RSA_PUB_KEY_E_ZERO_LEN 508
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#define CONFIG_ROOT_RSA_PUB_KEY_E_V 0x0
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/* params area */
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#define CONFIG_PARAMS_AREA_POS 0x400 /* fixed, and equal to (CONFIG_KEY_AREA_POS + CONFIG_ROOT_RSA_PUB_KEY_N_LEN + CONFIG_ROOT_RSA_PUB_KEY_E_LEN) */
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#define CONFIG_PARAMS_AREA_LEN 0x23C0 /* fixed and not be changed */
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#define CONFIG_AUXCODE_AREA_LEN_POS (CONFIG_PARAMS_AREA_POS)
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#define CONFIG_BOOT_CODE_AREA_LEN_POS (CONFIG_AUXCODE_AREA_LEN_POS + 0x4)
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#define CONFIG_TOTAL_BOOT_AREA_LEN_POS (CONFIG_BOOT_CODE_AREA_LEN_POS + 0x4)
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#define CONFIG_AUXCODE_ENC_FLAG_POS (CONFIG_TOTAL_BOOT_AREA_LEN_POS + 0x4)
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#define CONFIG_BOOT_ENC_FLAG_POS (CONFIG_AUXCODE_ENC_FLAG_POS + 0x4)
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#define CONFIG_BOOT_ENTRY_PIONT_POS (CONFIG_BOOT_ENC_FLAG_POS + 0x4)
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#define CONFIG_AUXCODE_AES_IV_POS (CONFIG_BOOT_ENTRY_PIONT_POS + 0x4)
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#define CONFIG_BOOT_AES_IV_POS (CONFIG_AUXCODE_AES_IV_POS + 0x10)
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#define CONFIG_PARAMS_FORM_POS (CONFIG_BOOT_AES_IV_POS + 0x10)
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#define CONFIG_PARAMS_FORM_LEN (0x2000) /* fixed */
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#define CONFIG_PARAMS_FORM_LEN_POS (CONFIG_TOTAL_BOOT_AREA_LEN_POS + 0x4)
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#define CONFIG_LOAD_MCU_FW_FLAG_POS (CONFIG_PARAMS_FORM_POS + CONFIG_PARAMS_FORM_LEN)
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#define CONFIG_MCU_FW_AREA_LEN_POS (CONFIG_LOAD_MCU_FW_FLAG_POS + 0x4)
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#define CONFIG_LBIST_TEST_PATTERN_OFF_POS (CONFIG_MCU_FW_AREA_LEN_POS + 0x4)
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#define COFNIG_LBIST_TEST_PATTERN_LEN_POS (CONFIG_LBIST_TEST_PATTERN_OFF_POS + 0x4)
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#define COFNIG_LBIST_TEST_PATTERN_HASH_POS (COFNIG_LBIST_TEST_PATTERN_LEN_POS + 0x4)
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#define COFNIG_AUXCODE_ALG_FLAG_POS (COFNIG_LBIST_TEST_PATTERN_HASH_POS + 0x20)
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#define CONFIG_RESERVED0_POS (COFNIG_AUXCODE_ALG_FLAG_POS + 0x4)
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#ifdef CONFIG_AUXCODE_2048_ENABLE
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#define CONFIG_AUXCODE_2048_FLAG 0x20485AA5
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#else
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#define CONFIG_AUXCODE_2048_FLAG 0
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#endif
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#ifdef CONFIG_QS_MCU
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#define CONFIG_LOAD_MCU_FW_FLAG 0x875a693c
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#define CONFIG_MCU_FW_AREA_LEN 0x40000
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#else
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#define CONFIG_LOAD_MCU_FW_FLAG 0
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#define CONFIG_MCU_FW_AREA_LEN 0
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#endif
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#define CONFIG_RESERVED0_LEN (0x154)
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#define CONFIG_SIG_PARAMS_POS (CONFIG_RESERVED0_POS + CONFIG_RESERVED0_LEN)
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#define CONFIG_SIG_PARAMS_LEN (0x200)
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#ifndef CONFIG_AUXAREA_LEN
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#define CONFIG_AUXAREA_LEN 0x7000 /* 28k for auxcode total len */
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#endif
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#define CONFIG_AUXCODE_ENC_FLAG 0x12345678 /* crypto:0x2A13C812 nocrypto:other val */
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#define CONFIG_BOOT_ENC_FLAG 0x12345678 /* crypto:0x2A13C812 nocrypto:other val */
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#define CONFIG_BOOT_ENTRY_PIONT (CONFIG_SYS_TEXT_BASE_ORI + CONFIG_KEY_AREA_LEN + CONFIG_AUXAREA_LEN + CONFIG_MCU_FW_AREA_LEN)
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/* unchecked area */
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#define CONFIG_SCS_SIMULATE_FLAG_POS (CONFIG_PARAMS_AREA_POS + CONFIG_PARAMS_AREA_LEN)
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#define CONFIG_BOOT_STORE_ADDR_POS (CONFIG_SCS_SIMULATE_FLAG_POS + 0x4)
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#define CONFIG_FLASH_EMPYT_FLAG_POS (CONFIG_BOOT_STORE_ADDR_POS + 0x4)
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#define CONFIG_RESERVED1_POS (CONFIG_FLASH_EMPYT_FLAG_POS +0x4)
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#define CONFIG_RESERVED1_LEN (0x34)
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#define CONFIG_SCS_SIMULATE_FLAG 0x69875AB4 /* no verify */
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#define CONFIG_FLASH_EMPYT_FLAG 0x435A590D /* not empty */
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#define CONFIG_BOOT_STORE_ADDR 0x40700000 /* same with burn tool */
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/* auxcode area */
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#define CONFIG_IMAGE_INFO_POS (CONFIG_KEY_AREA_POS + CONFIG_KEY_AREA_LEN)
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#define CONFIG_AUX_IDENTITY_INFO_POS (CONFIG_IMAGE_INFO_POS + 0x20)
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#define CONFIG_AUX_CODE_OFFSET_POS (CONFIG_AUX_IDENTITY_INFO_POS + 0x10)
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#define CONFIG_AUX_CODE_OFFSET (0x40)
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#define CONFIG_AUX_CODE_LEN_POS (CONFIG_AUX_CODE_OFFSET_POS + 0x4)
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#define CONFIG_RESERVED2_POS (CONFIG_AUX_CODE_LEN_POS + 0x4)
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#define CONFIG_AUXILIARY_CODE_POS (CONFIG_RESERVED2_POS + 0x8)
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#define CONFIE_AUXILIART_CODE_LEN (CONFIG_AUXAREA_LEN - 0x240)
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#define CONFIG_SIG_AUXCODE_POS (CONFIG_AUXILIARY_CODE_POS + CONFIE_AUXILIART_CODE_LEN)
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#define CONFIG_SIG_AUXCODE_LEN (0x200)
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/* mcu fw area */
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#define CONFIG_MCU_FW_AREA_POS (CONFIG_KEY_AREA_POS + CONFIG_KEY_AREA_LEN + CONFIG_AUXAREA_LEN)
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/* boot code area */
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#define CONFIG_BOOT_CODE_AREA_POS (CONFIG_KEY_AREA_POS + CONFIG_KEY_AREA_LEN + CONFIG_AUXAREA_LEN + CONFIG_MCU_FW_AREA_LEN)
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#define CONFIG_BOOT_HEAD_SIZE (CONFIG_KEY_AREA_LEN + CONFIG_AUXAREA_LEN + CONFIG_MCU_FW_AREA_LEN)
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/* Magic code for boot code area */
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#define CONFIG_BOOT_CODE_AREA_MAGIC 0x96A5784B
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#define FLASH_ALIGNED_SIZE (0x2000) /* 8K */
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#define CONFIG_BL31_BASE (CONFIG_SYS_SDRAM_BASE + 0x8000)
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#define CONFIG_BL31_LIMIT (CONFIG_BL31_BASE + 0x40000) //256K limit
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#define CONFIG_BL32_BASE (CONFIG_SYS_SDRAM_BASE + 0x10000000)
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#define CONFIG_MCU_FW_BUF_ADDR CONFIG_BL31_LIMIT
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#define CONFIG_MCU_FW_BUF_SIZE (CONFIG_MCU_FW_AREA_LEN + 2 * FLASH_ALIGNED_SIZE)
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#define CONFIG_DTB_BASE (CONFIG_MCU_FW_BUF_ADDR + CONFIG_MCU_FW_BUF_SIZE)
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/*
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The arm64 kernel require that the device tree blob (dtb) must be placed
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on an 8-byte boundary within the first 512 megabytes from the start of
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the kernel image and must not cross a 2-megabyte boundary. This is to
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allow the kernel to map the blob using a single section mapping in the
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initial page tables. we limit the max dtb size to 128K, which is
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a safe and enough size for dtb.
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*/
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#define CONFIG_DTB_MAX_SIZE (0x20000)
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#endif /* __XMFALCON_H */
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