64 lines
1.3 KiB
C
64 lines
1.3 KiB
C
#ifndef H_PM_DDR_H
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#define H_PM_DDR_H
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#define HASH_SIZE_PER_BYTE 32
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#define DDR_CALIB_SIZE 832
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#define DDR_PARAM_UPDATE_CYCLE (7 * 24 * 60 * 60)
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struct lpds_param {
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xmedia_u8 lpds_hash[HASH_SIZE_PER_BYTE];
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xmedia_u8 ddr_hash[HASH_SIZE_PER_BYTE];
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xmedia_u32 data_start;
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xmedia_u32 data_size;
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xmedia_u32 hash_flag;
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xmedia_u32 str_flag;
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xmedia_u32 resume_addr;
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xmedia_u32 resume_addr_backup;
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xmedia_u8 reserve0[24];
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xmedia_u8 scrambling_key[16];
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xmedia_u8 ddr_calib[DDR_CALIB_SIZE];
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xmedia_u32 ddr_size;
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xmedia_u32 hpm_state;
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xmedia_u32 power_state;
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xmedia_u8 reserve1[20];
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xmedia_u32 ddr_suspend_crc;
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xmedia_u32 ddr_resume_crc;
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};
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struct ddr_calib_data {
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xmedia_u32 checksum;
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xmedia_u32 gate_dqs0_result;
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xmedia_u32 gate_dqs1_result;
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xmedia_u32 rx_dqs0_result;
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xmedia_u32 rx_dqsb0_result;
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xmedia_u32 rx_dqs1_result;
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xmedia_u32 rx_dqsb1_result;
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xmedia_u32 rx_dm0_result;
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xmedia_u32 rx_dm1_result;
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xmedia_u32 rx_dq_result[16];
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xmedia_u32 tx_dqs0_result;
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xmedia_u32 tx_dqsb0_result;
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xmedia_u32 tx_dqs1_result;
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xmedia_u32 tx_dqsb1_result;
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xmedia_u32 tx_dm0_result;
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xmedia_u32 tx_dm1_result;
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xmedia_u32 tx_dq_result[16];
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xmedia_u32 time_sec;
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};
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xmedia_bool is_ram_off_str(void);
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xmedia_s32 ddr_param_check_and_save(void);
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xmedia_s32 xmedia_pm_get_ddr_param(struct lpds_param *p_lpds_param);
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#endif
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