485 lines
15 KiB
C
485 lines
15 KiB
C
/*
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Copyright (c), 2001-2022, Shenshu Tech. Co., Ltd.
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*/
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#ifndef __ES8388_H__
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#define __ES8388_H__
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/* ES8388 Register Definition */
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#define ES8388_REG0_CHIP_CONTROL1 0
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#define ES8388_REG1_CHIP_CONTROL2 1
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#define ES8388_REG2_CHIP_POWER_MANAGEMENT 2
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#define ES8388_REG3_ADC_POWER_MANAGEMENT 3
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#define ES8388_REG4_DAC_POWER_MANAGEMENT 4
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#define ES8388_REG5_CHIP_LOW_POWER1 5
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#define ES8388_REG6_CHIP_LOW_POWER2 6
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#define ES8388_REG7_ANALOG_VOLTAGE_MANAGEMENT 7
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#define ES8388_REG8_MASTER_MODE_CONTROL 8
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#define ES8388_REG9_ADC_CONTROL1 9
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#define ES8388_REG10_ADC_CONTROL2 10
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#define ES8388_REG11_ADC_CONTROL3 11
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#define ES8388_REG12_ADC_CONTROL4 12
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#define ES8388_REG13_ADC_CONTROL5 13
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#define ES8388_REG14_ADC_CONTROL6 14
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#define ES8388_REG15_ADC_CONTROL7 15
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#define ES8388_REG16_ADC_CONTROL8 16
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#define ES8388_REG17_ADC_CONTROL9 17
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#define ES8388_REG18_ADC_CONTROL10 18
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#define ES8388_REG19_ADC_CONTROL11 19
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#define ES8388_REG20_ADC_CONTROL12 20
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#define ES8388_REG21_ADC_CONTROL13 21
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#define ES8388_REG22_ADC_CONTROL14 22
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#define ES8388_REG23_DAC_CONTROL1 23
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#define ES8388_REG24_DAC_CONTROL2 24
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#define ES8388_REG25_DAC_CONTROL3 25
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#define ES8388_REG26_DAC_CONTROL4 26
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#define ES8388_REG27_DAC_CONTROL5 27
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#define ES8388_REG28_DAC_CONTROL6 28
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#define ES8388_REG29_DAC_CONTROL7 29
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#define ES8388_REG30_DAC_CONTROL8 30
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#define ES8388_REG31_DAC_CONTROL9 31
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#define ES8388_REG32_DAC_CONTROL10 32
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#define ES8388_REG33_DAC_CONTROL11 33
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#define ES8388_REG34_DAC_CONTROL12 34
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#define ES8388_REG35_DAC_CONTROL13 35
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#define ES8388_REG36_DAC_CONTROL14 36
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#define ES8388_REG37_DAC_CONTROL15 37
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#define ES8388_REG38_DAC_CONTROL16 38
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#define ES8388_REG39_DAC_CONTROL17 39
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#define ES8388_REG40_DAC_CONTROL18 40
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#define ES8388_REG41_DAC_CONTROL19 41
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#define ES8388_REG42_DAC_CONTROL20 42
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#define ES8388_REG43_DAC_CONTROL21 43
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#define ES8388_REG44_DAC_CONTROL22 44
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#define ES8388_REG45_DAC_CONTROL23 45
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#define ES8388_REG46_DAC_CONTROL24 46
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#define ES8388_REG47_DAC_CONTROL25 47
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#define ES8388_REG48_DAC_CONTROL26 48
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#define ES8388_REG49_DAC_CONTROL27 49
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#define ES8388_REG50_DAC_CONTROL28 50
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#define ES8388_REG51_DAC_CONTROL29 51
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#define ES8388_REG52_DAC_CONTROL30 52
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/* register number */
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#define ES8388_REG_NUM 53
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/* master/slave mode */
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#define ES8388_MASTER_MODE 0x1
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#define ES8388_SLAVE_MODE 0x0
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/* I2S clk polarity */
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#define ES8388_I2S_POLARITY_NORMAL 0x0
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#define ES8388_I2S_POLARITY_INVERT 0x1
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/* PCM offset */
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#define ES8388_PCM_OFFSET_2ND 0x0
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#define ES8388_PCM_OFFSET_1ST 0x1
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/* BCLK direction */
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#define ES8388_BCLK_DIR_NORMAL 0x0
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#define ES8388_BCLK_DIR_INVERT 0x1
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/* BCLK clock dividers */
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#define ES8388_BCLK_DIV_AUTO 0x00
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#define ES8388_BCLK_DIV_1 0x01
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#define ES8388_BCLK_DIV_2 0x02
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#define ES8388_BCLK_DIV_4 0x04
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#define ES8388_BCLK_DIV_6 0x05
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#define ES8388_BCLK_DIV_8 0x06
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/* FSCLK clock dividers */
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#define ES8388_FSCLK_DIV_1536 0x0A
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#define ES8388_FSCLK_DIV_1024 0x07
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#define ES8388_FSCLK_DIV_768 0x06
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#define ES8388_FSCLK_DIV_512 0x04
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#define ES8388_FSCLK_DIV_384 0x03
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#define ES8388_FSCLK_DIV_256 0x02
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#define ES8388_FSCLK_DIV_128 0x00
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/* data format */
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#define ES8388_DATA_FORMAT_I2S 0x0
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#define ES8388_DATA_FORMAT_LEFT_JUSTIFY 0x1
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#define ES8388_DATA_FORMAT_RIGHT_JUSTIFY 0x2
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#define ES8388_DATA_FORMAT_PCM 0x3
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/* data length */
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#define ES8388_DATA_LENGTH_24BIT 0x0
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#define ES8388_DATA_LENGTH_20BIT 0x1
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#define ES8388_DATA_LENGTH_18BIT 0x2
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#define ES8388_DATA_LENGTH_16BIT 0x3
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#define ES8388_DATA_LENGTH_32BIT 0x4
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/* input select */
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#define ES8388_INPUT1 0x0
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#define ES8388_INPUT2 0x1
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#define ES8388_INPUT_DIFF 0x3
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/* power up/down */
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#define ES8388_POWER_UP 0x0
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#define ES8388_POWER_DOWN 0x1
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/* out enable/disable */
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#define ES8388_OUT_DISABLE 0x0
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#define ES8388_OUT_ENABLE 0x1
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/* PGA gain */
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#define ES8388_PGA_GAIN_0DB 0x0
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#define ES8388_PGA_GAIN_3DB 0x1
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#define ES8388_PGA_GAIN_6DB 0x2
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#define ES8388_PGA_GAIN_9DB 0x3
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#define ES8388_PGA_GAIN_12DB 0x4
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#define ES8388_PGA_GAIN_15DB 0x5
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#define ES8388_PGA_GAIN_18DB 0x6
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#define ES8388_PGA_GAIN_21DB 0x7
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#define ES8388_PGA_GAIN_24DB 0x8
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/* ADc/DAC mute */
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#define ES8388_MUTE_ENABLE 0x1
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#define ES8388_MUTE_DISABLE 0x0
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/* ADC volume */
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#define ES8388_ADC_VOLUME_0DB 0x00
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/* DAC volume */
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#define ES8388_DAC_VOLUME_0DB 0x00
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/* output volume */
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#define ES8388_OUTPUT_VOLUME_0DB 0x1E
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typedef enum {
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/* clk */
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ES8388_SET_ADC_MCLK_LRCLK_RATIO = 0x0,
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ES8388_SET_DAC_MCLK_LRCLK_RATIO,
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ES8388_SET_MCLK_BCLK_RATIO,
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ES8388_SET_ADC_POLARITY_AND_OFFSET,
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ES8388_SET_DAC_POLARITY_AND_OFFSET,
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ES8388_SET_MASTER_MODE,
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ES8388_SET_BCLK_DIR,
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/* data */
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ES8388_SET_ADC_DATA_WIDTH,
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ES8388_SET_DAC_DATA_WIDTH,
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ES8388_SET_ADC_DATA_FORMAT,
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ES8388_SET_DAC_DATA_FORMAT,
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/* input select */
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ES8388_SET_LEFT_INPUT_SELECT,
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ES8388_SET_RIGHT_INPUT_SELECT,
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/* input volume */
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ES8388_SET_LFET_INPUT_GAIN,
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ES8388_SET_RIGHT_INPUT_GAIN,
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ES8388_SET_LFET_ADC_VOLUME,
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ES8388_SET_RIGHT_ADC_VOLUME,
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ES8388_SET_ADC_MUTE,
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/* output volume */
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ES8388_SET_LFET_DAC_VOLUME,
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ES8388_SET_RIGHT_DAC_VOLUME,
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ES8388_SET_LFET_OUTPUT1_VOLUME,
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ES8388_SET_LFET_OUTPUT2_VOLUME,
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ES8388_SET_RIGHT_OUTPUT1_VOLUME,
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ES8388_SET_RIGHT_OUTPUT2_VOLUME,
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ES8388_SET_DAC_MUTE,
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/* input power */
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ES8388_SET_LFET_INPUT_POWER,
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ES8388_SET_RIGHT_INPUT_POWER,
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ES8388_SET_LFET_ADC_POWER,
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ES8388_SET_RIGHT_ADC_POWER,
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/* output power */
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ES8388_SET_LFET_DAC_POWER,
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ES8388_SET_RIGHT_DAC_POWER,
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ES8388_SET_LFET_OUTPUT1_ENABLE,
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ES8388_SET_RIGHT_OUTPUT1_ENABLE,
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ES8388_SET_LFET_OUTPUT2_ENABLE,
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ES8388_SET_RIGHT_OUTPUT2_ENABLE,
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/* control */
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ES8388_SOFT_RESET,
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ES8388_REG_DUMP,
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} ot_es8388_codec_ioctl;
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typedef union {
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struct {
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unsigned char int1_lp : 1;
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unsigned char flash_lp : 1;
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unsigned char pdn_adc_biasgen : 1;
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unsigned char pdn_micb : 1;
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unsigned char pdn_adcr : 1;
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unsigned char pdn_adcl : 1;
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unsigned char pdn_ainr : 1;
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unsigned char pdn_ainl : 1;
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} bit;
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unsigned char b8;
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} es8388_reg3_ctrl;
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typedef union {
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struct {
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unsigned char reserved : 2;
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unsigned char rout2 : 1;
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unsigned char lout2 : 1;
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unsigned char rout1 : 1;
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unsigned char lout1 : 1;
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unsigned char pdn_dacr : 1;
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unsigned char pdn_dacl : 1;
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} bit;
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unsigned char b8;
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} es8388_reg4_ctrl;
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typedef union {
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struct {
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unsigned char bclk_div : 5;
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unsigned char bclk_inv : 1;
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unsigned char mclk_div2 : 1;
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unsigned char msc : 1;
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} bit;
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unsigned char b8;
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} es8388_reg8_ctrl;
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typedef union {
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struct {
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unsigned char mic_amp_r : 4;
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unsigned char mic_amp_l : 4;
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} bit;
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unsigned char b8;
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} es8388_reg9_ctrl;
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typedef union {
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struct {
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unsigned char reserved : 2;
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unsigned char dsr : 1;
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unsigned char ds_sel : 1;
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unsigned char rin_sel : 2;
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unsigned char lin_sel : 2;
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} bit;
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unsigned char b8;
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} es8388_reg10_ctrl;
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typedef union {
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struct {
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unsigned char adc_format : 2;
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unsigned char adc_wl : 3;
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unsigned char adc_lr_p : 1;
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unsigned char dat_sel : 2;
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} bit;
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unsigned char b8;
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} es8388_reg12_ctrl;
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typedef union {
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struct {
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unsigned char adc_fs_ratio : 5;
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unsigned char adc_fs_mode : 1;
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unsigned char reserved : 2;
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} bit;
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unsigned char b8;
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} es8388_reg13_ctrl;
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typedef union {
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struct {
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unsigned char reserved_0 : 2;
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unsigned char adc_mute : 1;
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unsigned char adc_le_r : 1;
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unsigned char reserved_1 : 1;
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unsigned char adc_soft_ramp : 1;
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unsigned char adc_ramp_rate : 2;
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} bit;
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unsigned char b8;
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} es8388_reg15_ctrl;
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typedef union {
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struct {
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unsigned char ladc_vol : 8;
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} bit;
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unsigned char b8;
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} es8388_reg16_ctrl;
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typedef union {
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struct {
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unsigned char radc_vol : 8;
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} bit;
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unsigned char b8;
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} es8388_reg17_ctrl;
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typedef union {
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struct {
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unsigned char reserved : 1;
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unsigned char dac_format : 2;
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unsigned char dac_wl : 3;
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unsigned char dac_lr_p : 1;
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unsigned char dac_lr_swap : 1;
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} bit;
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unsigned char b8;
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} es8388_reg23_ctrl;
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typedef union {
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struct {
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unsigned char dac_fs_ratio : 5;
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unsigned char dac_fs_mode : 1;
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unsigned char reserved : 2;
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} bit;
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unsigned char b8;
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} es8388_reg24_ctrl;
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typedef union {
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struct {
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unsigned char reserved_0 : 2;
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unsigned char dac_mute : 1;
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unsigned char dac_le_r : 1;
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unsigned char reserved_1 : 1;
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unsigned char dac_soft_ramp : 1;
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unsigned char dac_ramp_rate : 2;
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} bit;
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unsigned char b8;
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} es8388_reg25_ctrl;
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typedef union {
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struct {
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unsigned char ldac_vol : 8;
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} bit;
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unsigned char b8;
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} es8388_reg26_ctrl;
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typedef union {
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struct {
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unsigned char rdac_vol : 8;
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} bit;
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unsigned char b8;
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} es8388_reg27_ctrl;
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typedef union {
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struct {
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unsigned char lout1_vol : 6;
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unsigned char reserved : 2;
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} bit;
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unsigned char b8;
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} es8388_reg46_ctrl;
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typedef union {
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struct {
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unsigned char rout1_vol : 6;
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unsigned char reserved : 2;
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} bit;
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unsigned char b8;
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} es8388_reg47_ctrl;
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typedef union {
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struct {
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unsigned char lout2_vol : 6;
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unsigned char reserved : 2;
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} bit;
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unsigned char b8;
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} es8388_reg48_ctrl;
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typedef union {
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struct {
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unsigned char rout2_vol : 6;
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unsigned char reserved : 2;
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} bit;
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unsigned char b8;
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} es8388_reg49_ctrl;
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typedef struct {
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unsigned int chip_num : 3;
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unsigned int audio_in_select : 2;
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unsigned int clk_div : 5;
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unsigned int clk_polarity : 1;
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unsigned int data_format : 2;
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unsigned int data_length : 3;
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unsigned int ctrl_mode : 1;
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unsigned int volume : 8;
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unsigned int if_mute : 1;
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unsigned int if_powerup : 1;
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unsigned int reserved : 5;
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} ot_es8388_audio_ctrl;
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#define ES8388_IOC_MAGIC 'E'
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/* clk */
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#define OT_ES8388_SET_ADC_MCLK_LRCLK_RATIO \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_ADC_MCLK_LRCLK_RATIO, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_DAC_MCLK_LRCLK_RATIO \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_DAC_MCLK_LRCLK_RATIO, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_MCLK_BCLK_RATIO \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_MCLK_BCLK_RATIO, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_ADC_POLARITY_AND_OFFSET \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_ADC_POLARITY_AND_OFFSET, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_DAC_POLARITY_AND_OFFSET \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_DAC_POLARITY_AND_OFFSET, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_MASTER_MODE \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_MASTER_MODE, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_BCLK_DIR \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_BCLK_DIR, ot_es8388_audio_ctrl)
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/* data */
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#define OT_ES8388_SET_ADC_DATA_WIDTH \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_ADC_DATA_WIDTH, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_DAC_DATA_WIDTH \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_DAC_DATA_WIDTH, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_ADC_DATA_FORMAT \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_ADC_DATA_FORMAT, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_DAC_DATA_FORMAT \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_DAC_DATA_FORMAT, ot_es8388_audio_ctrl)
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/* input select */
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#define OT_ES8388_SET_LEFT_INPUT_SELECT \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_LEFT_INPUT_SELECT, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_RIGHT_INPUT_SELECT \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_RIGHT_INPUT_SELECT, ot_es8388_audio_ctrl)
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/* input volume */
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#define OT_ES8388_SET_LFET_INPUT_GAIN \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_LFET_INPUT_GAIN, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_RIGHT_INPUT_GAIN \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_RIGHT_INPUT_GAIN, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_LFET_ADC_VOLUME \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_LFET_ADC_VOLUME, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_RIGHT_ADC_VOLUME \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_RIGHT_ADC_VOLUME, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_ADC_MUTE \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_ADC_MUTE, ot_es8388_audio_ctrl)
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/* output volume */
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#define OT_ES8388_SET_LFET_DAC_VOLUME \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_LFET_DAC_VOLUME, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_RIGHT_DAC_VOLUME \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_RIGHT_DAC_VOLUME, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_LFET_OUTPUT1_VOLUME \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_LFET_OUTPUT1_VOLUME, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_LFET_OUTPUT2_VOLUME \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_LFET_OUTPUT2_VOLUME, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_RIGHT_OUTPUT1_VOLUME \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_RIGHT_OUTPUT1_VOLUME, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_RIGHT_OUTPUT2_VOLUME \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_RIGHT_OUTPUT2_VOLUME, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_DAC_MUTE \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_DAC_MUTE, ot_es8388_audio_ctrl)
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/* input power */
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#define OT_ES8388_SET_LFET_INPUT_POWER \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_LFET_INPUT_POWER, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_RIGHT_INPUT_POWER \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_RIGHT_INPUT_POWER, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_LFET_ADC_POWER \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_LFET_ADC_POWER, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_RIGHT_ADC_POWER \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_RIGHT_ADC_POWER, ot_es8388_audio_ctrl)
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/* output power */
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#define OT_ES8388_SET_LFET_DAC_POWER \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_LFET_DAC_POWER, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_RIGHT_DAC_POWER \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_RIGHT_DAC_POWER, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_LFET_OUTPUT1_ENABLE \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_LFET_OUTPUT1_ENABLE, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_RIGHT_OUTPUT1_ENABLE \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_RIGHT_OUTPUT1_ENABLE, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_LFET_OUTPUT2_ENABLE \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_LFET_OUTPUT2_ENABLE, ot_es8388_audio_ctrl)
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#define OT_ES8388_SET_RIGHT_OUTPUT2_ENABLE \
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_IOW(ES8388_IOC_MAGIC, ES8388_SET_RIGHT_OUTPUT2_ENABLE, ot_es8388_audio_ctrl)
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/* control */
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#define OT_ES8388_SOFT_RESET \
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_IOW(ES8388_IOC_MAGIC, ES8388_SOFT_RESET, ot_es8388_audio_ctrl)
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#define OT_ES8388_REG_DUMP \
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_IOW(ES8388_IOC_MAGIC, ES8388_REG_DUMP, ot_es8388_audio_ctrl)
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#endif
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