433 lines
10 KiB
C
433 lines
10 KiB
C
/*
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Copyright (c), 2001-2022, Shenshu Tech. Co., Ltd.
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*/
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#ifndef __COMMON_H__
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#define __COMMON_H__
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unsigned char __I2CReadByte8(unsigned char devaddress, unsigned char address);
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void __I2CWriteByte8(unsigned char devaddress, unsigned char address, unsigned char data);
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#define gpio_i2c_read __I2CReadByte8
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#define gpio_i2c_write __I2CWriteByte8
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// device address define
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#define NVP6158_R0_ID 0xA1
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#define NVP6158C_R0_ID 0xA0 // 6158B AND 6158C USES THE SAME CHIPID,DIFF IN REV_ID
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#define NVP6158_REV_ID 0x00
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#define NVP6168_R0_ID 0xC1
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#define NVP6168C_R0_ID 0xC0
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#define CH_PER_CHIP 4
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#define NTSC 0x00
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#define PAL 0x01
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#define AHD_PELCO_16BIT
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#define CHIP_NUM 4
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enum {
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NC_AD_SAMPLE_RATE_8000 = 8000,
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NC_AD_SAMPLE_RATE_16000 = 16000,
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NC_AD_SAMPLE_RATE_32000 = 32000,
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NC_AD_SAMPLE_RATE_44100 = 44100,
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NC_AD_SAMPLE_RATE_MAX,
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};
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enum {
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NC_AD_AI = 0,
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NC_AD_AOC,
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NC_AD_MAX
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};
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enum {
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NC_AD_BIT_WIDTH_8 = 0,
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NC_AD_BIT_WIDTH_16,
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NC_AD_BIT_WIDTH_24,
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NC_AD_BIT_WIDTH_MAX
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};
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#define VIU_CH_CTRL 0x08
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#define VIU_ANC0_START 0x9c
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#define VIU_ANC0_SIZE 0xa0
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#define VIU_ANC1_START 0xa4
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#define VIU_ANC1_SIZE 0xa8
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#define VIU_BLANK_DATA_ADDR 0xac
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#define IOC_VDEC_GET_INPUT_VIDEO_FMT 0x08
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#define IOC_VDEC_SET_SYNC 0x0A
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#define IOC_VDEC_PTZ_ACP_READ 0x0D
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#define IOC_VDEC_SET_CHNMODE 0x13
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#define IOC_VDEC_SET_OUTPORTMODE 0x14
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#define IOC_VDEC_PTZ_ACP_READ_EACH_CH 0x31
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#define IOC_VDEC_INIT_MOTION 0x40
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#define IOC_VDEC_ENABLE_MOTION 0x41
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#define IOC_VDEC_DISABLE_MOTION 0x42
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#define IOC_VDEC_SET_MOTION_AREA 0x43
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#define IOC_VDEC_GET_MOTION_INFO 0x44
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#define IOC_VDEC_SET_MOTION_DISPLAY 0x45
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#define IOC_VDEC_SET_MOTION_SENS 0x46
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#define IOC_AUDIO_SET_CHNNUM 0x80
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#define IOC_AUDIO_SET_SAMPLE_RATE 0x81
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#define IOC_AUDIO_SET_BITWIDTH 0x82
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#define IOC_VDEC_ACP_POSSIBLE_FIRMUP 0xA0 // by Andy(2016-06-26)
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#define IOC_VDEC_ACP_CHECK_ISPSTATUS 0xA1 // by Andy(2016-07-12)
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#define IOC_VDEC_ACP_START_FIRMUP 0xA2 // by Andy(2016-07-12)
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#define IOC_VDEC_ACP_FIRMUP 0xA3 // by Andy(2016-06-26)
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#define IOC_VDEC_ACP_FIRMUP_END 0xA4 // by Andy(2016-06-26)
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#define IOC_VDEC_GET_ADC_CLK 0xB1
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#define IOC_VDEC_SET_ADC_CLK 0xB2
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/* ----------------------- Coaxial protocol --------------------- */
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// Coax UP Stream - 8bit
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#define IOC_VDEC_COAX_TX_INIT 0xA0
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#define IOC_VDEC_COAX_TX_CMD_SEND 0xA1
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// Coax UP Stream - 16bit only ACP 720P Support
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#define IOC_VDEC_COAX_TX_16BIT_INIT 0xB4
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#define IOC_VDEC_COAX_TX_16BIT_CMD_SEND 0xB5
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#define IOC_VDEC_COAX_TX_CVI_NEW_CMD_SEND 0xB6
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// Coax Down Stream
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#define IOC_VDEC_COAX_RX_INIT 0xA2
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#define IOC_VDEC_COAX_RX_DATA_READ 0xA3
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#define IOC_VDEC_COAX_RX_BUF_CLEAR 0xA4
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#define IOC_VDEC_COAX_RX_DEINIT 0xA5
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// Coax Test
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#define IOC_VDEC_COAX_TEST_TX_INIT_DATA_READ 0xA6
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#define IOC_VDEC_COAX_TEST_DATA_SET 0xA7
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#define IOC_VDEC_COAX_TEST_DATA_READ 0xA8
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// Coax FW Update
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#define IOC_VDEC_COAX_FW_ACP_HEADER_GET 0xA9
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#define IOC_VDEC_COAX_FW_READY_CMD_SET 0xAA
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#define IOC_VDEC_COAX_FW_READY_ACK_GET 0xAB
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#define IOC_VDEC_COAX_FW_START_CMD_SET 0xAC
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#define IOC_VDEC_COAX_FW_START_ACK_GET 0xAD
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#define IOC_VDEC_COAX_FW_SEND_DATA_SET 0xAE
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#define IOC_VDEC_COAX_FW_SEND_ACK_GET 0xAF
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#define IOC_VDEC_COAX_FW_END_CMD_SET 0xB0
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#define IOC_VDEC_COAX_FW_END_ACK_GET 0xB1
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// Bank Dump Test
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#define IOC_VDEC_COAX_BANK_DUMP_GET 0xB2
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// ACP Option
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#define IOC_VDEC_COAX_RT_NRT_MODE_CHANGE_SET 0xB3
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typedef struct _nvp6158_video_mode {
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unsigned int chip;
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unsigned int mode;
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unsigned char vformat[16];
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unsigned char chmode[16];
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} nvp6158_video_mode;
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typedef struct _nvp6158_chn_mode {
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unsigned char ch;
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unsigned char vformat;
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unsigned char chmode;
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} nvp6158_chn_mode;
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typedef struct _nvp6158_opt_mode {
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unsigned char chipsel;
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unsigned char portsel;
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unsigned char portmode;
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unsigned char chid;
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} nvp6158_opt_mode;
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typedef struct _nvp6158_input_videofmt {
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unsigned int inputvideofmt[16];
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unsigned int getvideofmt[16];
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unsigned int geteqstage[16];
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unsigned int getacpdata[16][8];
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} nvp6158_input_videofmt;
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typedef struct _nvp6158_input_videofmt_ch {
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unsigned char ch;
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nvp6158_input_videofmt vfmt;
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} nvp6158_input_videofmt_ch;
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typedef struct _nvp6124_i2c_mode {
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unsigned char flag; // 0: read, 1 : write
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unsigned char slaveaddr;
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unsigned char bank;
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unsigned char address;
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unsigned char data;
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} nvp6124_i2c_mode;
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typedef struct _nvp6158_video_adjust {
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unsigned char ch;
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unsigned char value;
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} nvp6158_video_adjust;
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typedef struct _nvp6158_motion_area {
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unsigned char ch;
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int m_info[12];
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} nvp6158_motion_area;
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typedef struct _nvp6158_audio_playback {
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unsigned char chip;
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unsigned char ch;
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} nvp6158_audio_playback;
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typedef struct _nvp6158_audio_da_mute {
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unsigned char chip;
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} nvp6158_audio_da_mute;
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typedef struct _nvp6158_audio_da_volume {
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unsigned char chip;
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unsigned char volume;
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} nvp6158_audio_da_volume;
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typedef struct _nvp6158_audio_format {
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unsigned char format; /* 0:i2s; 1:dsp */
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unsigned char mode; /* 0:slave 1:master */
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unsigned char dspformat; /* 0:dsp;1:ssp */
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unsigned char clkdir; /* 0:inverted;1:non-inverted */
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unsigned char chn_num; /* 2,4,8,16 */
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unsigned char bitrate; /* 0:256fs 1:384fs invalid for nvp6114 2:320fs */
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unsigned char precision; /* 0:16bit;1:8bit */
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unsigned char samplerate; /* 0:8kHZ;1:16kHZ; 2:32kHZ */
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} nvp6158_audio_format;
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enum __CABLE_TYPE_INFORMATION__ {
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CABLE_TYPE_COAX = 0,
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CABLE_TYPE_UTP,
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CABLE_TYPE_MAX
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};
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enum __DETECTION_TYPE_INFORMATION__ {
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DETECTION_TYPE_AUTO = 0,
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DETECTION_TYPE_AHD,
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DETECTION_TYPE_CHD,
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DETECTION_TYPE_THD,
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DETECTION_TYPE_CVBS,
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DETECTION_TYPE_MAX
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};
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#define NVP6158_IOC_MAGIC 'n'
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#define NVP6158_SET_AUDIO_PLAYBACK _IOW(NVP6158_IOC_MAGIC, 0x21, nvp6158_audio_playback)
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#define NVP6158_SET_AUDIO_DA_MUTE _IOW(NVP6158_IOC_MAGIC, 0x22, nvp6158_audio_da_mute)
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#define NVP6158_SET_AUDIO_DA_VOLUME _IOW(NVP6158_IOC_MAGIC, 0x23, nvp6158_audio_da_volume)
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/* set record format */
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#define NVP6158_SET_AUDIO_R_FORMAT _IOW(NVP6158_IOC_MAGIC, 0x24, nvp6158_audio_format)
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/* set playback format */
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#define NVP6158_SET_AUDIO_PB_FORMAT _IOW(NVP6158_IOC_MAGIC, 0x25, nvp6158_audio_format)
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#define _SET_BIT(data, bit) ((data) |= (1 << (bit)))
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#define _CLE_BIT(data, bit) ((data) &= (~(1 << (bit))))
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typedef enum _NC_VIDEO_ONOFF {
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VIDEO_LOSS_ON = 0,
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VIDEO_LOSS_OFF = 1,
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} NC_VIDEO_ONOFF;
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typedef struct _decoder_dev_ch_info_s {
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unsigned char ch;
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unsigned char devnum;
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unsigned char fmt_def;
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} decoder_dev_ch_info_s;
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typedef enum NC_VIVO_CH_FORMATDEF {
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NC_VIVO_CH_FORMATDEF_UNKNOWN = 0,
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NC_VIVO_CH_FORMATDEF_AUTO,
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AHD20_SD_H960_NT, // 960h*480i
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AHD20_SD_H960_PAL = 3, // 960h*576i
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AHD20_SD_SH720_NT, // 960h*576i
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AHD20_SD_SH720_PAL = 5, // 960h*576i
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AHD20_SD_H1280_NT,
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AHD20_SD_H1280_PAL,
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AHD20_SD_H1440_NT,
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AHD20_SD_H1440_PAL,
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AHD20_SD_H960_EX_NT, // 1920h*480i
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AHD20_SD_H960_EX_PAL = 11, // 1920h*576i
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AHD20_SD_H960_2EX_NT,
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AHD20_SD_H960_2EX_PAL = 13,
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AHD20_SD_H960_2EX_Btype_NT, // 3840h*480i
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AHD20_SD_H960_2EX_Btype_PAL = 15, // 3840h*576i
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AHD20_1080P_30P,
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AHD20_1080P_25P,
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AHD20_720P_60P,
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AHD20_720P_50P,
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AHD20_720P_30P,
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AHD20_720P_25P,
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AHD20_720P_30P_EX,
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AHD20_720P_25P_EX,
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AHD20_720P_30P_EX_Btype,
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AHD20_720P_25P_EX_Btype,
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AHD30_4M_30P,
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AHD30_4M_25P,
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AHD30_4M_15P,
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AHD30_3M_30P,
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AHD30_3M_25P,
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AHD30_3M_18P, // 2048 x 1536
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AHD30_5M_12_5P, // 2592 x 1944
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AHD30_5M_20P, // 2592 x 1944
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AHD30_5_3M_20P,
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AHD30_6M_18P,
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AHD30_6M_20P,
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AHD30_8M_X_30P,
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AHD30_8M_X_25P,
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AHD30_8M_7_5P,
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AHD30_8M_12_5P,
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AHD30_8M_15P,
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TVI_FHD_30P,
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TVI_FHD_25P,
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TVI_HD_60P,
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TVI_HD_50P,
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TVI_HD_30P,
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TVI_HD_25P,
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TVI_HD_30P_EX,
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TVI_HD_25P_EX,
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TVI_HD_B_30P,
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TVI_HD_B_25P,
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TVI_HD_B_30P_EX,
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TVI_HD_B_25P_EX,
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TVI_3M_18P, // 1920 x 1536
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TVI_5M_12_5P,
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TVI_5M_20P,
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TVI_4M_30P,
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TVI_4M_25P,
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TVI_4M_15P,
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TVI_8M_15P,
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TVI_8M_12_5P,
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CVI_FHD_30P,
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CVI_FHD_25P,
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CVI_HD_60P,
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CVI_HD_50P,
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CVI_HD_30P,
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CVI_HD_25P,
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CVI_HD_30P_EX,
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CVI_HD_25P_EX,
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CVI_4M_30P,
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CVI_4M_25P,
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CVI_5M_20P,
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CVI_8M_15P,
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CVI_8M_12_5P,
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AHD20_1080P_60P,
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AHD20_1080P_50P,
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AHD20_1080P_15P,
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AHD20_1080P_12_5P,
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TVI_FHD_60P,
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TVI_FHD_50P,
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AHD20_960P_30P,
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AHD20_960P_25P,
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AHD20_960P_60P,
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AHD20_960P_50P,
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AHD20_1080P_15P_EX, // Hidden For test
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AHD20_1080P_12_5P_EX, // Hidden For test
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AHD20_720P_15P_2EX_Btype, // Hidden For test
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AHD20_720P_12_5P_2EX_Btype, // Hidden For test
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AHD20_720P_15P_EX_Btype, // Hidden For test
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AHD20_720P_12_5P_EX_Btype, // Hidden For test
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NC_VIVO_CH_FORMATDEF_MAX,
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} NC_VIVO_CH_FORMATDEF;
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typedef enum NC_FORMAT_FPS {
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FMT_FPS_UNKNOWN = 0,
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FMT_NT = 1,
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FMT_PAL,
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FMT_12_5P,
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FMT_7_5P,
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FMT_30P,
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FMT_25P,
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FMT_50P,
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FMT_60P,
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FMT_15P,
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FMT_18P,
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FMT_18_75P,
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FMT_20P,
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FMT_FPS_MAX,
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} NC_FORMAT_FPS;
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typedef enum NC_FORMAT_STANDARD {
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FMT_STD_UNKNOWN = 0,
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FMT_SD,
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FMT_AHD20,
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FMT_AHD30,
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FMT_TVI,
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FMT_CVI,
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FMT_AUTO,
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FMT_STD_MAX,
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} NC_FORMAT_STANDARD;
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typedef enum NC_FORMAT_RESOLUTION {
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FMT_RESOL_UNKNOWN = 0,
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FMT_SH720,
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FMT_H960,
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FMT_H1280,
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FMT_H1440,
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FMT_H960_EX,
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FMT_H960_2EX,
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FMT_H960_Btype_2EX,
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FMT_720P,
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FMT_720P_EX,
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FMT_720P_Btype,
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FMT_720P_Btype_EX,
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FMT_1080P,
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FMT_1080P_EX,
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FMT_3M,
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FMT_4M,
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FMT_5M,
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FMT_5_3M,
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FMT_6M,
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FMT_8M_X,
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FMT_8M,
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FMT_H960_Btype_2EX_SP,
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FMT_720P_Btype_EX_SP,
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FMT_RESOL_MAX,
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} NC_FORMAT_RESOLUTION;
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typedef struct VDEC_DEV_INFORM_S {
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unsigned char chip_id[4];
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unsigned char chip_rev[4];
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unsigned char chip_addr[4];
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unsigned char Total_Port_Num;
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unsigned char Total_Chip_Cnt;
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} VDEC_DEV_INFORM_S;
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typedef struct _NVP6158_INFORMATION_S {
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unsigned char ch;
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NC_VIVO_CH_FORMATDEF curvideofmt[16];
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NC_VIVO_CH_FORMATDEF prevideofmt[16];
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unsigned char curvideoloss[16];
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unsigned char vfc[16];
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unsigned char debounce[16][5];
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unsigned char debounceidx[16];
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VDEC_DEV_INFORM_S chipinform;
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} NVP6158_INFORMATION_S;
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#endif
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